Host storage device
By using the secure memory chip U1 and its peripheral circuit to manage the encryption key in the host storage device, the data security threat caused by the encryption key being directly stored inside the hard disk in the prior art is solved, and higher data security and controllability are achieved.
Patent Information
- Application Number
- CN202421868068.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-02
- Publication Date
- 2025-06-13
- Estimated Expiration
- 2034-08-02
AI Technical Summary
Existing local storage devices have shortcomings in security protection, especially the encryption keys are stored directly inside the hard disk, which are easily illegally acquired and bypassed by the encryption mechanism, resulting in data security threats.
A host storage device is designed, using a secure memory chip U1 and its peripheral circuit, and data encryption, decryption and key management are carried out through a secure memory chip U1 to ensure that the encryption key is not directly stored inside the hard disk, and communicate with the host in real time through a communication circuit.
It effectively eliminates the risk of data being read directly after the hard disk is illegally acquired, improves the security and controllability of data, and enhances the response speed and effectiveness of storage devices in response to security threats.
Smart Images
Figure CN222980015U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of storage devices, and particularly relates to a host storage device. Background Art
[0002] In the current era of rapid development of information technology, information security has become an indispensable part of all walks of life. Especially in the fields of data processing and storage, the security of data is even more crucial. However, in the current storage device market, although mobile storage media such as USB flash drives and external hard drives have been widely protected, local storage devices such as hard drives installed inside computers are still inadequate in terms of security protection.
[0003] For local storage devices, the current security strategy generally uses encryption storage technology to protect data security. However, there is a hidden danger that cannot be ignored in this encryption method: the encryption key is usually directly stored inside the hard drive. Although this design simplifies the encryption and decryption processes, it also brings great risks to data security. Once the hard drive is illegally obtained by criminals and transferred to other hosts, they may be able to bypass the encryption mechanism through technical means and directly read the decrypted plaintext data, thus posing a serious threat to data security.
[0004] More critically, most existing host storage devices are only equipped with storage chips and lack a dedicated controller to manage data encryption, decryption, and key storage and access. This design makes the storage device have many deficiencies in terms of security, flexibility, and controllability. For example, the storage device cannot adjust the encryption strategy or access rights in real time according to the instructions of the host; once the storage device is attacked, it is difficult to take timely countermeasures due to the lack of an effective control mechanism. Summary of the Invention
[0005] The purpose of the utility model is to provide a host storage device to solve the problems existing in the prior art in view of the defects in the prior art.
[0006] To achieve the above purpose, the utility model provides the following technical solutions:
[0007] A host storage device includes a device housing, in which a main control circuit, a storage circuit, a communication circuit, and a power supply circuit for powering the entire device are provided. The main control circuit includes a secure storage chip U1 and a peripheral circuit connected to the secure storage chip U1. The storage circuit is connected to the storage pins of the secure storage chip U1, and the communication pins of the secure storage chip U1 are communicatively connected to the host through the communication circuit.
[0008] A further improvement of this technical solution is that the secure storage chip U1 uses a secure storage chip with the model T620.
[0009] A further improvement of this technical solution is that the power supply circuit includes a 3.3V power supply circuit, a 1.8V power supply circuit, and a 1V power supply circuit;
[0010] The 3.3V power supply circuit includes a power conversion chip U2, capacitors C1, C2, a resistor R1, capacitors C3, an inductor L1, capacitors C4, resistors R2, R3, R4, capacitors C5, and C6. The first pin of the power conversion chip U2, the first ends of capacitors C1 and C2, and the first end of resistor R1 are all connected to an external 5V power supply. The second end of resistor R1 is connected to the second pin of the power conversion chip U2. The third pin of the power conversion chip U2, the second ends of capacitors C1 and C2 are all grounded. The fourth pin of the power conversion chip U2 is connected to the first 3.3V output terminal through capacitor C3. The first end of inductor L1 and the fifth pin of the power conversion chip U2 are both connected to the first 3.3V output interface. The second end of inductor L1 is connected to the first end of capacitor C4, the first end of resistor R2, the first end of capacitor C5, the first end of capacitor C6, and the second 3.3V output interface. The second end of capacitor C4 and the first end of resistor R3 are both connected to the sixth pin of the power conversion chip U2. The second ends of resistors R2 and R3 are both grounded through resistor R4. The second ends of capacitors C5 and C6 are both grounded;
[0011] The 1.8V power supply circuit includes a power conversion chip U3, capacitors C7, C8, and C9. The input pin of the power conversion chip U3 and the first end of capacitor C7 are both connected to the second 3.3V output interface. The ground pin of the power conversion chip U3 and the second end of capacitor C7 are both grounded. The output pin of the power conversion chip U3 is connected to the 1.8V output interface and is grounded through capacitors C8 and C9 connected in parallel;
[0012] The 1V power supply circuit includes a power conversion chip U4, capacitors C10, C11, and C12. The input pin of the power conversion chip U4 and the first end of capacitor C10 are both connected to the second 3.3V output interface. The ground pin of the power conversion chip U4 and the second end of capacitor C10 are both grounded. The output pin of the power conversion chip U4 is connected to the 1V output interface and is grounded through capacitors C11 and C12 connected in parallel.
[0013] A further improvement of this technical solution is that the storage circuit includes a storage chip U5, resistors R5 and R6, capacitors C13 to C32, bead FB1 and bead FB2. The first ends of capacitor C13, capacitor C14 and bead FB1 are all connected to the second 3.3V output interface. The second end of bead FB1 is connected to the first ends of capacitor C15, capacitor C16 and the 3.3V bus interface. The second ends of capacitor C13, capacitor C14, capacitor C15 and capacitor C16 are all grounded. The first ends of capacitor C17, capacitor C18 and bead FB2 are all connected to the second 3.3V output interface. The second end of bead FB2 is connected to the first ends of capacitor C19, capacitor C20 and the 1.8V bus interface. The second ends of capacitor C17, capacitor C18, capacitor C19 and capacitor C20 are all grounded;
[0014] The first to ninth pins of the storage chip U5 are all connected to the secure storage chip U1. The tenth pin of the storage chip U5 is connected to the secure storage chip U1 through resistor R5. The eleventh pin of the storage chip U5 is connected to the secure storage chip U1. The twelfth pin of the storage chip U5 is connected to the secure storage chip U1. The twelfth pin of the storage chip U5 is connected to the 1.8V bus interface through resistor R6. The twelfth pin of the storage chip U5 is grounded through capacitor C21. The thirteenth pin of the storage chip U5 is grounded through the parallel connection of capacitor C22 and capacitor C23. The fourteenth to seventeenth pins of the storage chip U5 are all connected to the 3.3V bus interface. The fourteenth to seventeenth pins of the storage chip U5 are all grounded through the parallel connection of capacitors C24 to C27. The eighteenth to twenty-third pins of the storage chip U5 are all connected to the 3.3V bus interface through the parallel connection of capacitors C24 to C27. The eighteenth to twenty-third pins of the storage chip U5 are all grounded. The twenty-fourth to twenty-eighth pins of the storage chip U5 are all connected to the 1.8V bus interface. The twenty-fourth to twenty-eighth pins of the storage chip U5 are all grounded through the parallel connection of capacitors C28 to C32. The twenty-ninth to thirty-third pins of the storage chip U5 are all connected to the 1.8V bus interface through the parallel connection of capacitors C28 to C32. The twenty-ninth to thirty-third pins of the storage chip U5 are all grounded.
[0015] A further improvement of this technical solution is that the storage chip U5 uses a storage chip with the model THGBMHG7C1LBAIL.
[0016] A further improvement of this technical solution is that the communication circuit includes a SATA interface J1, capacitors C33, C34, C35, and C36. The first transmission pin of the SATA interface J1 is connected to the secure storage chip U1 through the capacitor C33, the second transmission pin of the SATA interface J1 is connected to the secure storage chip U1 through the capacitor C34, the first reception pin of the SATA interface J1 is connected to the secure storage chip U1 through the capacitor C35, and the second reception pin of the SATA interface J1 is connected to the secure storage chip U1 through the capacitor C36. The SATA interface J1 is plugged into the corresponding interface configured on the host.
[0017] The beneficial effects of the present utility model are as follows:
[0018] Firstly, by introducing the secure storage chip U1 and the peripheral circuit connected thereto, which is managed and protected by the secure storage chip U1. Different from traditional storage hard disks, the encryption key is no longer directly stored inside the hard disk. This design fundamentally eliminates the risk of data being directly read after the hard disk is illegally obtained, greatly improving the security of data.
[0019] Secondly, the communication pins of the secure storage chip U1 are communicatively connected to the host through the communication circuit, enabling the storage device to perform real-time data exchange and instruction transmission with the host, ensuring the security of data transmission and further enhancing the security of data.
[0020] In summary, the new host storage device proposed by this technical solution has significant beneficial effects in the field of information security. It not only improves the security, flexibility, and controllability of data, but also enhances the response speed and effectiveness of the storage device in dealing with security threats. The implementation of this technical solution will provide a more secure and reliable guarantee for data storage and processing in various industries.
[0021] In addition, the design principle of the present utility model is reliable, the structure is simple, and it has a very broad application prospect.
[0022] Thus, compared with the prior art, the present utility model has outstanding substantive features and significant progress, and the beneficial effects of its implementation are also obvious. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 It is a schematic block diagram of the structure of the host storage device.
[0024] Figure 2 It is a schematic diagram of the main control circuit.
[0025] Figure 3 It is a schematic diagram of the 3.3V power supply circuit.
[0026] Figure 4Schematic diagram of the 1.8V power supply circuit.
[0027] Figure 5 Schematic diagram of the 1V power supply circuit.
[0028] Figure 6 Schematic diagram of the storage circuit.
[0029] Figure 7 Schematic diagram of the communication circuit.
[0030] 110 is the device housing, 120 is the main control circuit, 130 is the storage circuit, 140 is the communication circuit, and 150 is the power supply circuit. Detailed implementation manners
[0031] In order to enable those skilled in the art of this technology to better understand the technical solutions in this utility model, the following will clearly and completely describe the technical solutions in the embodiments of this utility model in conjunction with the accompanying drawings in the embodiments of this utility model. Obviously, the described embodiments are only a part of the embodiments of this utility model, rather than all of the embodiments. Based on the embodiments in this utility model, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of this utility model.
[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this utility model belongs. The terms used in the specification of this utility model herein are only for the purpose of describing specific embodiments, and are not intended to limit this utility model.
[0033] The following explains the key terms that appear in this utility model.
[0034] SATA is the English abbreviation of Serial Advanced Technology Attachment, which is an industry-standard serial hardware drive interface. SATA transmits data in a continuous serial manner, reducing the number of connection cables, improving efficiency, while also reducing system power consumption and system complexity. SATA has a higher starting point and greater development potential. The data transfer rate of SATA 1.0 is 150MB / s, the data transfer rate of SATA 2.0 is 300MB / s, and ultimately SATA will achieve a maximum transfer rate of 600MB / s.
[0035] Such as Figure 1As shown in the figure, the present utility model provides a host storage device, which includes a device housing. Inside the device housing, there are a main control circuit, a storage circuit, a communication circuit, and a power supply circuit for powering the entire device. The main control circuit includes a secure storage chip U1 and its peripheral circuit connected to the secure storage chip U1. The storage circuit is connected to the storage pins of the secure storage chip U1. The communication pins of the secure storage chip U1 are communicatively connected to the host through the communication circuit. Among them, the secure storage chip U1 is a secure storage chip with the model T620.
[0036] The wiring principle of the main control circuit is as Figure 2 shown. The peripheral circuit of the main control circuit includes capacitors C37 to C65, beads FB3 to FB9, resistors R7 to R21, and crystal oscillator X1.
[0037] Before using this host storage device, it is necessary to first bind it to the host through the secure storage chip U1 in the main control circuit. If this host storage device is forcibly removed and attempts to be read by other hosts, since it has not been authenticated by the secure storage chip U1, this host storage device will always be in an unavailable state and it is also impossible to read the internal data.
[0038] As Figure 3 、 Figure 4 and Figure 5 shown, the power supply circuit includes a 3.3V power supply circuit, a 1.8V power supply circuit, and a 1V power supply circuit.
[0039] Among them, the 3.3V power supply circuit includes a power conversion chip U2, capacitors C1, C2, resistor R1, capacitor C3, inductor L1, capacitor C4, resistors R2, R3, R4, capacitor C5, and capacitor C6. The first pin of the power conversion chip U2, the first ends of capacitors C1, C2, and the first end of resistor R1 are all connected to an external 5V power supply. The second end of resistor R1 is connected to the second pin of the power conversion chip U2. The third pin of the power conversion chip U2, the second ends of capacitors C1 and C2 are all grounded. The fourth pin of the power conversion chip U2 is connected to the first 3.3V output terminal through capacitor C3. The first end of inductor L1 and the fifth pin of the power conversion chip U2 are both connected to the first 3.3V output interface. The second end of inductor L1 is connected to the first end of capacitor C4, the first end of resistor R2, the first end of capacitor C5, the first end of capacitor C6, and the second 3.3V output interface. The second end of capacitor C4 and the first end of resistor R3 are both connected to the sixth pin of the power conversion chip U2. The second ends of resistors R2 and R3 are both grounded through resistor R4. The second ends of capacitors C5 and C6 are both grounded.
[0040] The 1.8V power supply circuit includes a power conversion chip U3, a capacitor C7, a capacitor C8, and a capacitor C9. The input pin of the power conversion chip U3 and the first end of the capacitor C7 are both connected to the second 3.3V output interface. The ground pin of the power conversion chip U3 and the second end of the capacitor C7 are both grounded. The output pin of the power conversion chip U3 is connected to the 1.8V output interface and grounded through the parallel-connected capacitors C8 and C9.
[0041] The 1V power supply circuit includes a power conversion chip U4, a capacitor C10, a capacitor C11, and a capacitor C12. The input pin of the power conversion chip U4 and the first end of the capacitor C10 are both connected to the second 3.3V output interface. The ground pin of the power conversion chip U4 and the second end of the capacitor C10 are both grounded. The output pin of the power conversion chip U4 is connected to the 1V output interface and grounded through the parallel-connected capacitors C11 and C12.
[0042] Such as Figure 6As shown, the storage circuit includes a storage chip U5, resistors R5 and R6, capacitors C13 to C32, beads FB1 and FB2. The first ends of capacitor C13, capacitor C14, and bead FB1 are all connected to the second 3.3V output interface. The second end of bead FB1 is connected to the first ends of capacitor C15, capacitor C16, and the 3.3V bus interface. The second ends of capacitor C13, capacitor C14, capacitor C15, and capacitor C16 are all grounded. The first ends of capacitor C17, capacitor C18, and bead FB2 are all connected to the second 3.3V output interface. The second end of bead FB2 is connected to the first ends of capacitor C19, capacitor C20, and the 1.8V bus interface. The second ends of capacitor C17, capacitor C18, capacitor C19, and capacitor C20 are all grounded; the first to ninth pins of storage chip U5 are all connected to the secure storage chip U1. The tenth pin of storage chip U5 is connected to the secure storage chip U1 through resistor R5. The eleventh pin of storage chip U5 is connected to the secure storage chip U1. The twelfth pin of storage chip U5 is connected to the secure storage chip U1. The twelfth pin of storage chip U5 is connected to the 1.8V bus interface through resistor R6. The twelfth pin of storage chip U5 is grounded through capacitor C21. The thirteenth pin of storage chip U5 is grounded through the parallel connection of capacitor C22 and capacitor C23. The fourteenth to seventeenth pins of storage chip U5 are all connected to the 3.3V bus interface. The fourteenth to seventeenth pins of storage chip U5 are all grounded through the parallel connection of capacitors C24 to C27. The eighteenth to twenty-third pins of storage chip U5 are all connected to the 3.3V bus interface through the parallel connection of capacitors C24 to C27. The eighteenth to twenty-third pins of storage chip U5 are all grounded. The twenty-fourth to twenty-eighth pins of storage chip U5 are all connected to the 1.8V bus interface. The twenty-fourth to twenty-eighth pins of storage chip U5 are all grounded through the parallel connection of capacitors C28 to C32. The twenty-ninth to thirty-third pins of storage chip U5 are all connected to the 1.8V bus interface through the parallel connection of capacitors C28 to C32. The twenty-ninth to thirty-third pins of storage chip U5 are all grounded.
[0043] Among them, the storage chip U5 uses a storage chip with the model THGBMHG7C1LBAIL.
[0044] As Figure 7As shown in the figure, the communication circuit includes a SATA interface J1, capacitors C33, C34, C35, and C36. The first transmission pin of the SATA interface J1 is connected to the secure storage chip U1 through the capacitor C33. The second transmission pin of the SATA interface J1 is connected to the secure storage chip U1 through the capacitor C34. The first reception pin of the SATA interface J1 is connected to the secure storage chip U1 through the capacitor C35. The second reception pin of the SATA interface J1 is connected to the secure storage chip U1 through the capacitor C36. The SATA interface J1 is plugged into the corresponding interface configured on the host.
[0045] The above-disclosed are only the preferred embodiments of the present invention, but the present invention is not limited thereto. Any non-creative changes that can be conceived by those skilled in the art, as well as several improvements and refinements made without departing from the principles of the present invention, should fall within the protection scope of the present invention.
Claims
1. A host storage device, characterized in that: The device comprises a housing, in which a main control circuit, a storage circuit, a communication circuit and a power supply circuit for supplying power to the entire device are arranged. The main control circuit comprises a secure storage chip U1 and a peripheral circuit connected to the secure storage chip U1. The storage circuit is connected to a storage pin of the secure storage chip U1. The communication pin of the secure storage chip U1 is connected to the host through a communication circuit.
2. The host storage device according to claim 1, characterized in that: The secure storage chip U1 uses a secure storage chip model T620.
3. The host storage device according to claim 2, characterized in that: The power supply circuit includes a 3.3V power supply circuit, a 1.8V power supply circuit and a 1V power supply circuit; The 3.3V power supply circuit includes a power conversion chip U2, a capacitor C1, a capacitor C2, a resistor R1, a capacitor C3, an inductor L1, a capacitor C4, a resistor R2, a resistor R3, a resistor R4, a capacitor C5 and a capacitor C6. The first pin of the power conversion chip U2, the first end of the capacitor C1, the first end of the capacitor C2 and the first end of the resistor R1 are all connected to an external 5V power supply. The second end of the resistor R1 is connected to the second pin of the power conversion chip U2. The third pin of the power conversion chip U2, the second end of the capacitor C1 and the second end of the capacitor C2 are all grounded. The fourth pin of the power conversion chip U2 is connected to the external 5V power supply. The first pin is connected to the first 3.3V output terminal through the capacitor C3, the first end of the inductor L1 and the fifth pin of the power conversion chip U2 are both connected to the first 3.3V output interface, the second end of the inductor L1 is connected to the first end of the capacitor C4, the first end of the resistor R2, the first end of the capacitor C5, the first end of the capacitor C6 and the second 3.3V output interface, the second end of the capacitor C4 and the first end of the resistor R3 are both connected to the sixth pin of the power conversion chip U2, the second end of the resistor R2 and the second end of the resistor R3 are both grounded through the resistor R4, and the second end of the capacitor C5 and the second end of the capacitor C6 are both grounded; The 1.8V power supply circuit includes a power conversion chip U3, a capacitor C7, a capacitor C8 and a capacitor C9, an input pin of the power conversion chip U3 and a first end of the capacitor C7 are both connected to the second 3.3V output interface, a ground pin of the power conversion chip U3 and a second end of the capacitor C7 are both grounded, and an output pin of the power conversion chip U3 is connected to the 1.8V output interface and is grounded through the capacitors C8 and C9 connected in parallel; The 1V power supply circuit includes a power conversion chip U4, a capacitor C10, a capacitor C11 and a capacitor C12. The input pin of the power conversion chip U4 and the first end of the capacitor C10 are both connected to the second 3.3V output interface, the ground pin of the power conversion chip U4 and the second end of the capacitor C10 are both grounded, and the output pin of the power conversion chip U4 is connected to the 1V output interface and is grounded through the capacitors C11 and C12 connected in parallel.
4. The host storage device according to claim 3, characterized in that: The storage circuit includes a storage chip U5, a resistor R5, a resistor R6, capacitors C13 to C32, a magnetic bead FB1 and a magnetic bead FB2, a first end of the capacitor C13, a first end of the capacitor C14 and a first end of the magnetic bead FB1 are all connected to a second 3.3V output interface, a second end of the magnetic bead FB1 is connected to a first end of the capacitor C15, a first end of the capacitor C16 and a 3.3V bus interface, a second end of the capacitor C13, a second end of the capacitor C14, a second end of the capacitor C15 and a second end of the capacitor C16 are all grounded, a first end of the capacitor C17, a first end of the capacitor C18 and a first end of the magnetic bead FB2 are all connected to the second 3.3V output interface, a second end of the magnetic bead FB2 is connected to a first end of the capacitor C19, a first end of the capacitor C20 and a 1.8V bus interface, a second end of the capacitor C17, a second end of the capacitor C18, a second end of the capacitor C19 and a second end of the capacitor C20 are all grounded; The first to ninth pins of the memory chip U5 are all connected to the secure memory chip U1, the tenth pin of the memory chip U5 is connected to the secure memory chip U1 through the resistor R5, the eleventh pin of the memory chip U5 is connected to the secure memory chip U1, the twelfth pin of the memory chip U5 is connected to the secure memory chip U1, the twelfth pin of the memory chip U5 is connected to the 1.8V bus interface through the resistor R6, the twelfth pin of the memory chip U5 is grounded through the capacitor C21, the thirteenth pin of the memory chip U5 is grounded through the capacitor C22 and the capacitor C23 connected in parallel, the fourteenth to seventeenth pins of the memory chip U5 are all connected to the 3.3V bus interface, the fourteenth to seventeenth pins of the memory chip U5 are connected to the 3.3V bus interface, and the fourteenth to seventeenth pins of the memory chip U5 are connected to the 1.8V bus interface. The eighteenth to twenty-third pins of the memory chip U5 are connected to the 3.3V bus interface through capacitors C24 to C27 in parallel, the eighteenth to twenty-third pins of the memory chip U5 are connected to the ground, the twenty-fourth to twenty-eighth pins of the memory chip U5 are connected to the 1.8V bus interface, the twenty-fourth to twenty-eighth pins of the memory chip U5 are connected to the ground through capacitors C28 to C32 in parallel, the twenty-ninth to thirty-third pins of the memory chip U5 are connected to the 1.8V bus interface through capacitors C28 to C32 in parallel, and the twenty-ninth to thirty-third pins of the memory chip U5 are grounded.
5. The host storage device according to claim 4, characterized in that: The memory chip U5 uses a memory chip model THGBMHG7C1LBAIL.
6. The host storage device according to claim 1, characterized in that: The communication circuit includes a SATA interface J1, a capacitor C33, a capacitor C34, a capacitor C35 and a capacitor C36. The first sending pin of the SATA interface J1 is connected to the secure storage chip U1 through the capacitor C33, the second sending pin of the SATA interface J1 is connected to the secure storage chip U1 through the capacitor C34, the first receiving pin of the SATA interface J1 is connected to the secure storage chip U1 through the capacitor C35, the second receiving pin of the SATA interface J1 is connected to the secure storage chip U1 through the capacitor C36, and the SATA interface J1 is plugged into the corresponding interface configured on the host.