Cluster channel machine based on RF Transceiver software radio

Abstract

The utility model discloses a cluster channel machine based on RF Transceiver software radio, which comprises an FPGA, a DSP, an ARM, a clock management chip, an LNA, a PA, a DSA and a SAW Filter, the FPGA is respectively connected with the DSP, the ARM, a Flash3 and the clock management chip, the DSP is connected with an SDRAM1 and a Flash1, the ARM is connected with an SDRAM2 and a Flash2, the clock management chip is connected with a TCXO, the cluster channel machine comprises an RF Transceiver connected with the FPGA and the clock management chip, the input end and the output end of the RF Transceiver are both connected with the SAW Filter, and the input end and the output end of the RF Transceiver are connected with the LNA, the PA, the DSA and the SAW Filter. And the LNA, the PA, the DSA, the SAW Filter and the RF Transceiver are sequentially connected and arranged to form an RF RX receiving channel and an RF TX transmitting channel. According to the utility model, the circuit of an RF transmitting and receiving channel is simplified, multiple paths of radio frequency signals can be directly adopted, the radio frequency signals from 300MHz to 6GHz are output, and the functions of digital filtering, digital up and down converters, digital combination, modulation and demodulation, automatic power control and the like are integrally realized; different functions can be realized by loading different waveforms, different requirements can be met without changing hardware, the cost, the power consumption and the size are reduced, the debugging process is reduced, and the production is more convenient.

Description

Technical Field

[0001] The utility model relates to the technical field of wireless communication, in particular to a cluster channel machine based on RF Transceiver software radio. Background Art

[0002] There is no effective solution for the interconnection between various types of traditional communication equipment, and military and civilian communications have become a major problem. In order to solve this problem, the United States has formulated and researched the "EasyTalk" universal software radio station for the three services, the United Kingdom has launched the "Archer" combat radio system program, and Canada has promoted the "Reconfigurable Full-Band Radio Program", and so on.

[0003] At present, similar equipment abroad generally adopts software radio structure for design. The radio uses the same hardware platform to achieve multi-function loading and multi-system compatibility, can complete multi-function and multi-mode communication, and is flexible in equipment upgrades. It breaks through the spectrum limits of shortwave and ultra-shortwave, and can form a general software radio communication platform by connecting different functional components. The radio communication mode can be quickly switched through RF reconstruction and waveform dynamic loading, which reduces the types and quantity of equipment and the difficulty of guarantee. The communication waveform design is componentized and standardized, and different waveform components can realize specific communication functions through mutual combination, and the communication rate covers narrowband to broadband requirements.

[0004] In addition, intelligent anti-interference technology has been widely used in new research and development projects in the United States. Through intelligent anti-interference technology, wireless communication anti-interference waveforms suitable for the interference characteristics of the current environment can be extracted from the waveform component library, thereby achieving the best anti-interference effect.

[0005] Software radio uses an open, universal and scalable general hardware platform to adapt to the different needs of different users and different application environments by loading various application software to realize various radio functions. Compared with traditional designs, software radio has obvious advantages. Therefore, the research and development of software radio communication technology is extremely important. Utility Model Content

[0006] The technical solution adopted by the utility model to solve the above technical problems is:

[0007] A general hardware platform (FPGA+DSP+RF Transceiver) is used to load software to realize a cluster channel machine based on RF Transceiver software radio with simple circuit, high system stability, low R&D and production cost, and convenient debugging.

[0008] The trunking channel unit based on RF Transceiver software radio includes an FPGA, a DSP, an ARM, a clock management chip, an LNA, a PA, a DSA, and a SAW Filter. The FPGA is respectively connected to the DSP, the ARM, Flash3, and the clock management chip. The DSP is connected to SDRAM1 and Flash1. The ARM is connected to SDRAM2 and Flash2. The clock management chip is connected to a TCXO. It also includes an RF Transceiver connected to the FPGA and the clock management chip. The input end and the output end of the RF Transceiver are both connected to a SAW Filter. The LNA, the PA, the DSA, the SAW Filter, and the RF Transceiver are connected in sequence to form an RF RX receiving channel and an RF TX transmitting channel.

[0009] Further, the trunking channel unit can simultaneously complete the reception and transmission of four channels, with different frequencies for reception and transmission, a frequency separation of 10 MHz between reception and transmission, and a frequency band of 350 MHz to 390 MHz. When the modulation method is GMSK with BT = 0.3, the channel spacing is 25 kHz. When the modulation method is 4FSK, the channel spacing is 12.5 kHz.

[0010] Further, for the receiving channel: The signal is received from the antenna and sent to the duplexer. The signal output from the duplexer enters the RF RX receiving channel, is processed and amplified by the LNA and the PA, then attenuated by the DSA, and finally filtered by the SAW Filter. The data after filtering is sent to the RF Transceiver for radio frequency AD sampling, digital mixing, CIC, FIR, and AGC to obtain the baseband IQ signal. The baseband IQ signal is sent to the FPGA, where relevant decisions, GMSK demodulation, 4FSK demodulation, etc. are performed. The demodulated signal is sent to the DSP for subsequent processing, including channel decoding, deinterleaving, and related processing at the MAC layer, etc.

[0011] Furthermore, the transmitting channel: The signal received from the receiving channel is processed in the DSP and then enters the transmitting channel. First, channel coding, interleaving, formation of burst frames, and related MAC layer processing are performed. Then, the signal is sent to the FPGA at a rate of 16 kHz. In the FPGA, GMSK modulation and 4FSK modulation for four channels are completed to form a baseband zero-IF IQ signal with a rate of 2.048 MHz. The baseband IQ signals of the four channels after digital multiplexing are sent into the RF Transceiver. The RF Transceiver completes digital filtering, interpolation, direct digital frequency synthesizer DDS, and a high-performance high-speed 14-bit digital-to-analog converter DAC, providing baseband upconversion for data transmission in the wireless communication system. The frequency of the output analog signal is 350 MHz - 390 MHz. This analog signal is connected to a multi-carrier linear power amplifier module, and after being amplified by the multi-carrier linear power amplifier module, it is transmitted by the antenna.

[0012] Furthermore, clock control: The clock is uniformly provided by a clock management chip. The entire system clock is provided by a temperature-controlled crystal oscillator with a frequency stability of 0.01 PPB and a frequency of 30.72 MHz, ensuring clock homology and in-phase. The clock is divided into two paths by the clock management chip for output. One path of 122.88 MHz is provided to the FPGA, and in the FPGA, the DCM module provides the clocks required inside the FPGA; the other path of 122.88 MHz is provided to the RF Transceiver; the clock provided by the FPGA to the DSP is 30.72 MHz, and after the DSP performs 20-fold frequency multiplication, the DSP obtains a working frequency of 614.4 MHz.

[0013] Furthermore, instruction control: The DSP is also connected to a host computer. The instructions of the host computer include various parameters such as software update of the DSP, working mode of the cluster channel machine, working frequency, power, and IP address. The instructions of the host computer are sent to the DSP through the network port and processed by the DSP, or forwarded by the DSP to the FPGA for relevant processing.

[0014] Preferably, the model of the RF Transceiver is AD9371.

[0015] Preferably, the model of the clock management chip is AD9528.

[0016] Preferably, the model of the FPGA is XC7A200T.

[0017] Preferably, the model of the ARM is AT91SAM9X25, and the model of the DSP is TMS320C6416.

[0018] The beneficial effects of the present utility model are as follows: Firstly, based on the design concept of software radio, the present utility model is implemented by loading software on a general hardware platform (FPGA + DSP + RF Transceiver). The circuits of the radio frequency receiving and transmitting channels are greatly simplified. The multiplex radio frequency signals of the RF Transceiver are directly adopted, and radio frequency signals from 300 MHz to 6 GHz can be output. In the FPGA, functions such as digital filtering, digital up and down converters, digital combining, modulation and demodulation, and automatic power control are implemented by software, greatly simplifying the circuit design.

[0019] Secondly, different functions are realized by loading different waveforms on a general hardware platform (FPGA + DSP + RF Transceiver). Currently, the implemented waveforms include MDT waveform and PDT waveform; when users need to add new functions or waveforms, they can be upgraded by updating the software without changing the hardware.

[0020] Thirdly, compared with traditional base station channel machines, traditional base station channel machines include a radio frequency receiving board, a transmitting board, and a clock board, which are no longer needed in the present utility model, reducing costs, power consumption, and volume. At the same time, due to its standardized hardware design, the production of the product is more convenient. Especially for the debugging process of the product, the requirements will be greatly reduced, which is more conducive to improving production efficiency, enhancing the technical level of R & D personnel, improving the company's scientific research strength, and accelerating the development cycle of other products of the company. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of the connection and framework of each component of the present utility model.

[0022] As shown in the figure: 1. SDRAM1; 2. Flash1; 3. DSP; 4. ARM; 5. SDRAM2; 6. Flash2; 7. TCXO; 8. Clock management chip; 9. FPGA; 10. Flash3; 11. LNA; 12. PA; 13. DSA; 14. SAW Filter; 15. RFTransceiver. DETAILED IMPLEMENTATION MANNER

[0023] The terms used in this utility model are all commonly defined in the field of wireless communication technology. Specifically, SDRAM is synchronous dynamic random access memory, Flash is flash memory, DSP is digital signal processor, ARM is instruction set processor, TCXO is temperature compensated crystal oscillator, FPGA is programmable logic device, LNA is low noise amplifier, PA is power amplifier, DSA is digital control attenuator, SAW Filter is surface acoustic wave filter, RF Transceiver is radio frequency transceiver, RF RX is radio frequency reception, and RF TX is radio frequency transmission. For other terms not listed, those skilled in the art should understand their term definitions and interpretations in accordance with the common term definitions in this technical field.

[0024] The following further describes this utility model in conjunction with the drawings and embodiments.

[0025] As Figure 1 shown, the trunking channel machine based on the RF Transceiver software radio includes SDRAM1, SDRAM2, Flash1, Flash2, Flash3, DSP, ARM, TCXO, clock management chip, FPGA, LNA, PA, DSA, SAW Filter, and RF Transceiver. The FPGA programmable logic device is respectively connected to the DSP digital signal processor, RF Transceiver radio frequency transceiver, clock management chip, ARM, and Flash3. The DSP digital signal processor is connected to SDRAM1 and Flash1. The RF Transceiver radio frequency transceiver is connected to the clock management chip, and SAW Filter surface acoustic wave filters are connected to both the input end and the output end of the RF Transceiver radio frequency transceiver. The ARM is connected to SDRAM2 and Flash2. The clock management chip is also connected to TXCO. It also includes an RF RX receiving channel and an RF TX transmitting channel composed of an LNA low noise amplifier, a PA power amplifier, a DSA digital control attenuator, a SAW Filter surface acoustic wave filter, and an RF Transceiver radio frequency transceiver connected in sequence.

[0026] For the signal of the RF RX receiving channel, it first passes through the LNA low noise amplifier, then is amplified by the PA power amplifier, then is attenuated by the DSA digital control attenuator, and finally is filtered by the SAW Filter surface acoustic wave filter. The filtered signal is sent to the RF Transceiver radio frequency transceiver for radio frequency AD sampling and subsequent processing.

[0027] The RF TX transmission channel signal is output by the DA of the RF Transceiver. The signal output by the DA is filtered by the SAW Filter and then output to the multi-carrier linear power amplifier module.

[0028] The utility model can simultaneously complete the reception and transmission of four channels, with different frequencies for reception and transmission. The frequency interval between reception and transmission is 10 MHz, and the frequency band is 350 MHz - 390 MHz. When the modulation mode is GMSK (BT = 0.3), the channel interval is 25 kHz. When the modulation mode is 4FSK, the channel interval is 12.5 kHz. The specific implementation methods include a receiving channel, a transmitting channel, clock control, and instruction control.

[0029] For the receiving channel, first, the signal is received from the antenna and sent to the duplexer. The signal output from the duplexer enters the RFRX receiving channel, is amplified by the LNA low-noise amplifier, then amplified by the PA power amplifier, attenuated by the digital control attenuator DSA, and finally filtered by the SAW Filter. The filtered data is sent to the RF Transceiver for radio frequency AD sampling, digital mixing, CIC, FIR, and AGC to obtain the baseband IQ signal. The baseband IQ signal is sent to the FPGA programmable logic device, where relevant decisions, GMSK demodulation, and 4FSK demodulation are performed. The demodulated signal is sent to the DSP digital signal processor for subsequent processing, including channel decoding, deinterleaving, and related processing at the MAC layer.

[0030] For the transmitting channel, the signal received from the receiving channel is processed in the DSP digital signal processor and then enters the transmitting channel. First, channel coding, interleaving, formation of burst frames, and related processing at the MAC layer are performed. Then the signal is sent to the FPGA programmable logic device at a rate of 16 kHz. In the FPGA programmable logic device, GMSK modulation and 4FSK modulation of four channels are completed to form a baseband zero-intermediate-frequency IQ signal with a rate of 2.048 MHz. The baseband IQ signals of the four channels after digital multiplexing are sent to the RF Transceiver, where digital filtering, interpolation, direct digital frequency synthesizer (DDS), and a high-performance high-speed 14-bit digital-to-analog converter (DAC) are completed to provide baseband upconversion for data transmission in the wireless communication system. The frequency of the output analog signal is 350 MHz - 390 MHz. The analog signal is connected to the multi-carrier linear power amplifier module, and the signal is amplified by the multi-carrier linear power amplifier module and then transmitted by the antenna.

[0031] Regarding the clock control, the present utility model has rather strict requirements for timing. The clock is uniformly provided by a clock management chip. The system clock is provided by a temperature-compensated crystal oscillator with a frequency stability of 0.01 PPB and a frequency of 30.72 MHz, thus ensuring that the clocks are of the same source and in-phase. The clock is divided into two output paths by the clock management chip. One path of 122.88 MHz is provided to the FPGA programmable logic device, and in this device, the DCM module provides the clocks required inside the FPGA. The other path of 122.88 MHz is provided to the RF Transceiver radio frequency transceiver. The clock provided by the FPGA programmable logic device to the DSP digital signal processor is 30.72 MHz. After the DSP digital signal processor performs 20 times frequency multiplication, the operating frequency of the DSP digital signal processor of 614.4 MHz can be obtained.

[0032] The clock management chip can adopt a clock chip with the model number AD9528, which supports remote optical fiber clock recovery and facilitates the near-end and far-end synchronization of the communication system.

[0033] Regarding the instruction control, the DSP digital signal processor is also connected to a host computer. The instructions of the host computer include various parameters such as software update of the DSP digital signal processor, operating mode of the cluster channel machine, operating frequency, power, and IP address. The instructions of the host computer are sent to the DSP digital signal processor through the network port and are processed by the DSP digital signal processor, or are forwarded by the DSP digital signal processor to the FPGA programmable logic device for relevant processing.

[0034] The ARM processor mainly completes the configuration of the RF Transceiver radio frequency transceiver, the clock management chip, and the processing of the cluster protocol stack, etc.

[0035] The RF Transceiver radio frequency transceiver can adopt an RF Transceiver with the model number AD9371, which has the characteristics of ultra-high integration and flexible high performance, supports a receiving bandwidth of 100 MHz, a transmitting bandwidth of 250 MHz, and an RF receiving and transmitting frequency range of 300 MHz to 6 GHz. The LNA, DSA, and SAW Filter on the radio frequency link cooperate with the AD9371 RF Transceiver to provide excellent system radio frequency performance.

[0036] In addition, preferably, the FPGA programmable logic device can adopt an FPGA with the model number XC7A200T, the DSP digital signal processor can adopt a DSP with the model number TMS320C6416, and the ARM can adopt an ARM with the model number AT91SAM9X25.

[0037] The present utility model is not limited to the above-mentioned optimal implementation manner. Any other products identical or similar to the present utility model obtained by anyone under the inspiration of the present utility model shall fall within the protection scope of the present utility model.

Claims

1. A cluster channel machine based on RF Transceiver software radio, including FPGA, DSP, ARM, clock management chip, LNA, PA, DSA, SAW Filter, FPGA is connected to DSP, ARM, Flash3 and clock management chip respectively, DSP is connected to SDRAM1 and Flash1, ARM is connected to SDRAM2 and Flash2, and clock management chip is connected to TCXO, characterized in that: It also includes an RF Transceiver connected to the FPGA and the clock management chip, the input and output ends of the RF Transceiver are both connected to the SAW Filter, and the LNA, PA, DSA, SAW Filter and RF Transceiver are sequentially connected to form an RFRX receiving channel and an RF TX transmitting channel.

2. The trunking channel machine based on RF Transceiver software radio according to claim 1, characterized in that: The cluster channel machine can complete four channel reception and transmission at the same time, with different frequencies for transmission and reception, a transmission and reception frequency interval of 10MHz, and a frequency band of 350MHz to 390MHz; when the modulation mode is GMSK with BT=0.3, the channel interval is 25kHz; when the modulation mode is 4FSK, the channel interval is 12.5kHz.

3. The trunking channel machine based on RF Transceiver software radio according to claim 1 or 2, characterized in that: Receiving channel: After the signal is received from the antenna, it is sent to the duplexer. The signal output from the duplexer enters the RF RX receiving channel, is processed and amplified by the LNA and PA, is attenuated by the DSA, and is finally filtered by the SAW Filter. The filtered data is sent to the RF Transceiver for RF AD sampling, digital mixing, CIC, FIR, and AGC to obtain the baseband IQ signal. The baseband IQ signal is sent to the FPGA, where relevant decisions, GMSK demodulation, and 4FSK demodulation are performed. The demodulated signal is sent to the DSP for subsequent processing, including channel decoding, deinterleaving, and related processing of the MAC layer.

4. The trunking channel machine based on RF Transceiver software radio according to claim 1 or 2, characterized in that: Transmitting channel: The signal received from the receiving channel is processed in the DSP and then enters the transmitting channel. First, channel coding, interleaving, burst frame formation and related processing of the MAC layer are performed. Then the signal is sent to the FPGA at a rate of 16kHz. The FPGA completes the GMSK modulation and 4FSK modulation of the four channels to form a baseband zero intermediate frequency IQ signal with a rate of 2.048 MHz. After digital combination, the baseband IQ signals of the four channels are sent to the RF Transceiver. The RF Transceiver completes digital filtering, interpolation, direct digital frequency synthesizer DDS, and high-performance and high-speed 14-bit digital-to-analog converter DAC, providing baseband up-conversion for data transmission in the wireless communication system. The frequency of the output analog signal is 350 MHz-390 MHz. The analog signal is connected to the multi-carrier linear power amplifier module. The signal is amplified by the multi-carrier linear power amplifier module and then transmitted by the antenna.

5. The trunking channel machine based on RF Transceiver software radio according to claim 1 or 2, characterized in that: Clock control: The clock is provided by the clock management chip. The clock of the entire system is provided by a constant temperature crystal oscillator with a frequency stability of 0.01PPB and a frequency of 30.72MHz to ensure the same source and phase of the clocks. The clock is divided into two outputs by the clock management chip. One 122.88 MHz clock is provided to the FPGA, and the DCM module in the FPGA provides the clock required inside the FPGA; the other 122.88 MHz clock is provided to the RF Transceiver; the clock provided by the FPGA to the DSP is 30.72 MHz, and the DSP is multiplied by 20 times to obtain a working frequency of 614.4MHz.

6. The trunking channel machine based on RF Transceiver software radio according to claim 1 or 2, characterized in that: Instruction control: DSP is also connected to the host computer. The instructions of the host computer include DSP software update, cluster channel machine working mode, working frequency, power, IP address and other parameters. The instructions of the host computer are sent to DSP through the network port, and DSP performs relevant processing, or forwarded by DSP to FPGA for relevant processing.

7. The trunking channel machine based on RF Transceiver software radio according to claim 1, characterized in that: The model of the RF Transceiver is AD9371.

8. The trunking channel machine based on RF Transceiver software radio according to claim 1, characterized in that: The model of the clock management chip is AD9528.

9. The trunking channel machine based on RF Transceiver software radio according to claim 1, characterized in that: The model of the FPGA is XC7A200T.

10. The trunking channel machine based on RF Transceiver software radio according to claim 1, characterized in that: The model of the ARM is AT91SAM9X25, and the model of the DSP is TMS320C6416.

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