Chip structure and electronic equipment

Abstract

The utility model discloses a chip structure and an electronic device, the chip structure comprises a first chip and a fuse, the first chip is provided with a suspension potential structure and a fixed potential structure, and the fuse is used for connecting the suspension potential structure and the fixed potential structure. The fuse has a first state of connecting the suspended potential structure and the fixed potential structure in the manufacturing process of the chip structure, and a second state of disconnecting the chip structure after the chip structure is manufactured or packaged. The electronic equipment comprises the chip structure. According to the utility model, the floating potential structure is allowed to exist in the chip design and processing scheme through the design of the fuse, and more possibilities are provided for the chip process design; meanwhile, wafer or chip damage caused by Arcling in the machining process can be effectively avoided, and economic losses are reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of chip manufacturing. More specifically, the utility model relates to a chip structure and an electronic device. Background Art

[0002] For the wafer manufacturing technology of a general CMOS (Complementary Metal Oxide Semiconductor) circuit, the general design rules require that conductive structures at floating potential be avoided in the circuit. Otherwise, during the etching process in the wafer manufacturing process, subsequent packaging processing, and the use process of the wafer and the chip, breakdown phenomena caused by arcing are likely to occur at this structure, resulting in the damage of the wafer or the chip. However, in some chip design solutions with unique requirements, there may be a situation where the intermediate metal layer is at floating potential and needs to be connected to a fixed potential during subsequent or top metal layer processing; or, in some sensor chip design solutions, other functional film layer structures are processed on the silicon chip, and these functional film layer structures need to be connected through the floating potential structure in the silicon chip and led out from the pad. At this time, it is necessary to combine the packaging processing process to connect the floating potential structure on the wafer to the fixed potential structure. The above design requirements urgently need a solution to avoid arcing during the processing. Summary of the Utility Model

[0003] Aiming at the deficiencies of the prior art, the utility model innovatively provides a chip structure and an electronic device, which allow the existence of floating potential in the chip design and processing solutions through the design of the fuse, providing more possibilities for the chip process design; at the same time, it can effectively avoid the damage of the wafer or the chip caused by arcing during the processing and reduce economic losses.

[0004] To achieve the above technical purpose, the first aspect of the utility model discloses a chip structure, including a first chip and a fuse.

[0005] The first chip is provided with a floating potential structure and a fixed potential structure. The fuse is used to connect the floating potential structure and the fixed potential structure. The fuse includes a first state in which the floating potential structure and the fixed potential structure are connected during the manufacturing process of the chip structure, and a second state in which the connection is broken after the chip structure is manufactured or after the packaging is completed.

[0006] Further, the fuse is arranged on the upper surface of the first chip.

[0007] Further, the floating potential structure extends a first connecting member, the fixed potential structure extends a second connecting member, one end of the fuse is connected to the first connecting member, and the other end of the fuse is connected to the second connecting member.

[0008] Further, it further includes a second chip, and the fuse is disposed in a scribe lane between the first chip and the second chip.

[0009] Further, the floating potential structure extends a third connecting member, the third connecting member extends to the edge of the first chip, the fixed potential structure extends a fourth connecting member, the fourth connecting member extends to the edge of the first chip, one end of the fuse is connected to the end of the third connecting member at the edge of the first chip, and the other end of the fuse is connected to the end of the fourth connecting member at the edge of the first chip.

[0010] Further, the fuse is switched from the first state to the second state by laser fusing.

[0011] Further, the fuse is switched from the first state to the second state by current fusing.

[0012] Further, the width of the fuse is the minimum width in the electrical structure of the layer where the fuse is located.

[0013] Further, a spacing is maintained between the fuse and other structures in the layer where the fuse is located to form a safety window.

[0014] Further, the fuse is switched from the first state to the second state by cutting.

[0015] Further, a protective structural member is provided around the fuse, the protective structural member is connected to the fuse, and the width of the protective structural member is greater than the width of the fuse.

[0016] Further, the protective structural member is in a finger-like shape.

[0017] To achieve the above technical objectives, a second aspect of the present invention discloses an electronic device, including the chip structure described in the first aspect.

[0018] The beneficial effects of the present invention are as follows:

[0019] The chip structure of the present invention, through the design of the fuse, allows a floating potential structure to exist in the chip design and processing scheme, providing more possibilities for chip process design; at the same time, it can effectively avoid damage to the wafer or chip caused by Arcing during the processing, reducing economic losses. Description of the Drawings

[0020] Figure 1 It is a schematic structural diagram of the chip structure of the first embodiment of the present utility model.

[0021] Figure 2 It is a schematic structural diagram of the chip structure of the second embodiment of the present utility model.

[0022] Figure 3 It is a schematic structural diagram of the chip structure of the third embodiment of the present utility model.

[0023] Figure 4 It is a flowchart of the fuse of the first embodiment of the present utility model from the first state to the second state.

[0024] Figure 5 It is a flowchart of the fuse of the second embodiment of the present utility model from the first state to the second state.

[0025] Figure 6 It is a flowchart of the fuse of the second embodiment of the present utility model from the first state to the second state.

[0026] In the figure,

[0027] 1. First chip; 11. Floating potential structure; 111. First connecting member; 112. Third connecting member; 12. Fixed potential structure; 121. Second connecting member; 122. Fourth connecting member; 2. Fuse; 3. Protective structural member; 4. Second chip; 5. Sawing lane; 6. Metal layer; 7. Functional film layer; 71. Upper electrode; 8. Encapsulation wire bonding; 9. Encapsulation structure. Detailed implementation manners

[0028] The following combines the description drawings of the specification to make a detailed explanation and description of the chip structure and electronic device provided by the present utility model.

[0029] This embodiment specifically discloses a chip structure, such as Figure 1-3As shown in the figure, it includes a first chip 1 and a fuse 2. A floating potential structure 11 and a fixed potential structure 12 are provided on the first chip 1. The fuse 2 is used to connect the floating potential structure 11 and the fixed potential structure 12. The fuse 2 includes a first state in which the floating potential structure 11 and the fixed potential structure 12 are connected during the chip structure manufacturing process, and a second state in which they are disconnected after the chip structure manufacturing is completed or after the packaging is completed. That is, during the chip structure manufacturing process, the floating potential structure 11 and the fixed potential structure 12 are connected through the fuse 2 to avoid breakdown phenomena caused by arc discharge at the floating potential structure 11 during subsequent chip manufacturing or subsequent packaging processes, which may cause damage to the wafer or chip and reduce economic losses. Then, the floating potential structure 11 is connected to the fixed potential structure 12 through a subsequent metal layer or packaging structure, and the fuse 2 is disconnected after the chip structure manufacturing is completed or after the packaging is completed.

[0030] The design of the fuse 2 allows the simultaneous presence of the floating potential structure 11 and the fixed potential structure 12 on the first chip 1, meeting the special design requirements of some chip design schemes, such as a design scheme where the intermediate metal layer is at a floating potential and is connected to the fixed potential structure 12 only during subsequent or top metal layer processing; or in some sensor chip design schemes, other functional film layers 7 are processed on the silicon chip, and these functional film layers 7 need to be connected and led out from the pads through the floating potential structure 11 on the silicon chip. In this case, it is necessary to combine the packaging processing process to connect the floating potential structure 11 on the silicon chip to the fixed potential structure 12. The design of the fuse 2 in this application can meet the above special design requirements and provide more possibilities for chip process design.

[0031] In this application, the floating potential structure 11 refers to a structure at a floating potential in the circuit, including but not limited to pads at a floating potential, etc. The fixed potential structure 12 refers to a structure at a fixed potential in the circuit, including but not limited to pads at a fixed potential, etc.

[0032] Optionally, as Figure 1 shown, the fuse 2 is arranged on the upper surface of the first chip 1, and the fuse 2 connects the floating potential structure 11 and the fixed potential structure 12. The fuse 2 can be integrally formed with other structures of the same metal layer on the upper surface of the first chip 1 through an etching process.

[0033] Specifically, as Figure 1 shown, the floating potential structure 11 extends a first connecting member 111, the fixed potential structure 12 extends a second connecting member 121, one end of the fuse 2 is connected to the first connecting member 111, and the other end of the fuse 2 is connected to the second connecting member 121. Preferably, the fuse 2 can be arranged between the floating potential structure 11 and the fixed potential structure 12 to reduce the size of the first chip 1.

[0034] In some embodiments, as Figure 2 shown, the chip structure of the present application further includes a second chip 4, and the fuse 2 is disposed in the scribe line 5 between the first chip 1 and the second chip 4.

[0035] Specifically, as Figure 2 shown, the floating potential structure 11 extends a third connecting member 112, the third connecting member 112 extends to the edge of the first chip 1, the fixed potential structure 12 extends a fourth connecting member 122, the fourth connecting member 122 extends to the edge of the first chip 1, one end of the fuse 2 is connected to the end of the third connecting member 112 at the edge of the first chip 1, and the other end of the fuse 2 is connected to the end of the fourth connecting member 122 at the edge of the first chip 1.

[0036] Optionally, the fuse 2 is switched from the first state to the second state by laser fusing, that is, the fuse 2 is disconnected by laser fusing after the chip structure is manufactured or after packaging. When laser fusing is used, no metal structure is provided above the fuse 2 to ensure that the laser can pass through the structure above the fuse 2 and irradiate the fuse 2. The intensity of the laser is adjusted according to actual needs as long as it can fuse the fuse 2. Preferably, the width of the fuse 2 is the minimum width in the structure of the layer where the fuse 2 is located, which makes it easier to operate during laser fusing. The present application does not limit the specific width of the fuse 2 when using the laser fusing disconnection method. Figure 2 In the embodiment shown, the fuse 2 is disposed in the scribe line 5, and it is only necessary to ensure that the structure above the scribe line 5 can transmit the laser and no metal structure is provided.

[0037] Optionally, the fuse 2 is switched from the first state to the second state by current fusing, that is, the fuse 2 is disconnected by current fusing after the chip structure is manufactured or after packaging. When current fusing is used, direct current is directly added to fuse the fuse 2. The width of the fuse 2 is the minimum width in the electrical structure of the layer where the fuse 2 is located. Since the intensity of the fusing current is proportional to the width of the fuse 2, the minimum width design of the fuse 2 can ensure that the added fusing current can fuse the fuse 2 without damaging other effective structures in the same layer as the fuse 2. The specific width of the fuse 2 is adjusted according to the actual application and design requirements of the chip. A safety window is formed by maintaining a spacing between the fuse 2 and other structures in the layer where the fuse 2 is located, that is, a sufficient distance is maintained between the fuse 2 and other structures on the upper surface of the first chip 1 to form a sufficiently large safety window. No metal structure is provided in the safety window to prevent the heat generated during the burning of the fuse 2 and the changes of the fuse 2 itself from affecting the effective structures around the fuse 2. The size of the safety window is set according to the width of the fuse 2 and the magnitude of the added current. Figure 2In the illustrated embodiment, the scribe lane 5 can be directly used as a safety window. Therefore, when the fuse 2 is disposed within the scribe lane 5, there is no need to specifically fabricate a safety window during the manufacturing process of the chip structure.

[0038] The fuse 2 can serve as protection for the floating potential structure 11Arcing and can itself be used as a simple protective device. After selecting the corresponding fusing current, it can be used as the fuse 2 in the entire circuit.

[0039] Figure 2 In the illustrated embodiment, by placing the fuse 2 in the scribe lane 5, it is easy to meet both the light transmission requirements for laser fusing and the safety window requirements for current fusing, and it will not affect the effective structures in the chip structure.

[0040] Optionally, Figure 2 In the illustrated embodiment, the fuse 2 is disposed within the scribe lane 5, and the fuse 2 is switched from the first state to the second state by cutting. The fuse 2 in the scribe lane 5 can be cut by a wafer dicing process. As long as it does not interfere with the application design, wafer dicing is the most economical and effective solution, and there is no risk of damaging other structures, which is both economical and safe. It is applicable to the production of design solutions where the floating potential structure 11 on the chip is connected to an FPC (Flexible Printed Circuit) or the like through module processing.

[0041] In some embodiments, as Figure 3 shown, a protective structural member 3 is provided around the fuse 2. The protective structural member 3 is connected to the fuse 2, and the width of the protective structural member 3 is greater than the width of the fuse 2 for protecting the fuse 2. Figure 2 In the figure, the arrow direction is the current path direction, and the structure through which the current does not flow is the protective structural member 3. The number, position, and shape of the protective structural member 3 are set according to actual needs. The setting of the protective structural member 3 also needs to ensure the size of the safety window around the fuse 2. Preferably, a plurality of protective structural members 3 surround the fuse 2. The protective structural member 3 is used to increase the local metal density of the overall chip structure, improve the process uniformity, facilitate the processing and manufacturing of the fuse 2, protect the fuse 2, and prevent the fuse 2 from breaking during the manufacturing process or packaging process of the chip structure. When the fuse 2 is disposed within the scribe lane 5, the protective structural member 3 around the fuse 2 is also disposed within the scribe lane 5; when the fuse 2 is disposed on the upper surface of the first chip 1, the specific length of the protective structural member 3 around the fuse 2 is not limited.

[0042] Preferably, as Figure 3 shown, the protective structural member 3 is in the shape of a dummy finger.

[0043] Optionally, the fuse 2 can be manufactured by the metal layer in the wafer manufacturing process or by the RDL (redistribution layer) in the packaging process. The specific manufacturing method is adjusted according to the actual application and design requirements. The shape of the fuse 2 can be linear, curved, bent, U-shaped, arc-shaped, etc. The present application does not limit the specific shape of the fuse 2.

[0044] In some chip structure design solutions, due to the wiring design requirements in the chip structure, there are floating potentials in some manufacturing stages. For example, there is a floating potential structure 11 in the middle metal layer during the chip manufacturing process, and in the subsequent metal layer, such as the top metal layer, the floating potential structure 11 is connected to a fixed potential. In this case, there is a risk of Arcing before the top metal layer is processed.

[0045] Figure 4 It is a manufacturing flowchart of the chip structure according to the first embodiment of the present application, where Figure 4 a is a top view of the middle manufacturing process of the chip structure, Figure 4 b is a cross-sectional view taken along the A-A direction after the chip structure is manufactured; as Figure 4 shown in a, when the middle metal layer is processed, the fuse 2 is used to connect the floating potential structure 11 and the fixed potential structure 12, that is, the floating potential structure 11 is connected to the fixed potential of the circuit. The fuse 2 is arranged on the upper surface of the first chip 1, and the fuse 2 plays a protective role in the subsequent processing; as Figure 4 shown in b, after all the metal layers 6 are processed, that is, after the top metal layer is processed, the top metal layer connects the floating potential structure 11 and the fixed potential structure 12, and the fuse 2 is disconnected by current fusing or laser fusing, restoring to the chip structure in the original design scheme, which not only avoids Arcing during the manufacturing process but also meets the chip design requirements with a floating potential.

[0046] Figure 5 It is a manufacturing flowchart of the chip structure according to the second embodiment of the present application, where Figure 5 a is a top view of the middle manufacturing process of the chip structure, Figure 5 b is a cross-sectional view taken along the B-B direction after the chip structure is manufactured; as Figure 5 shown in a, when the middle metal layer is processed, the fuse 2 is used to connect the floating potential structure 11 and the fixed potential structure 12, that is, the floating potential structure 11 is connected to the fixed potential of the circuit. The fuse 2 is arranged in the scribe line 5 between the first chip 1 and the second chip 4, and the fuse 2 plays a protective role in the subsequent processing; as Figure 5As shown in Figure b, after all metal layers 6 are processed, that is, after the top metal layer is processed, the top metal layer connects the floating potential structure 11 and the fixed potential structure 12, disconnects the fuse 2 by means of current fusing, laser fusing or cutting, and restores it to the chip structure in the original design scheme, which not only avoids Arcing during the manufacturing process, but also meets the chip design requirements with a floating potential.

[0047] In some chip structure design schemes, there are special functional structures such as the functional film layer 7 in the entire chip structure in addition to the silicon chip. Some of these functional structures are conductive. For the consideration of the packaging structure, these functional film layers 7 will be connected through the pads of the silicon chip and led out through the packaging wire bonding 8. In this case, the addition of the floating potential structure 11 in the silicon chip is inevitable, and it is necessary to connect the functional film layer 7 to the floating potential structure 11 in the silicon chip during the packaging process. For example, the structural design of a certain sensor chip requires connecting the upper electrode 71 of the functional film layer 7 to the floating potential pad of the underlying silicon chip, and subsequent packaging operations can be performed through the silicon chip pads; the advantage of doing this is that in the overall packaging body structure design, it saves the thickness space of the packaging body, and at the same time integrates the signal interfaces of the functional film layers 7 other than the silicon chip into the original pad array, facilitating the processing and application of the chip. Therefore, during the manufacturing process of the chip structure, the floating potential structure 11 always exists.

[0048] Figure 6 It is the packaging flow chart of the chip structure of the second embodiment of the present application, where Figure 6 Figure a is a top view of the intermediate manufacturing process of the chip structure, Figure 6 Figure b is a cross-sectional view taken along the C-C direction after the chip structure is packaged; as Figure 6 shown in Figure a, the floating potential structure 11 (floating potential pad) connecting the upper electrode 71 of the functional film layer 7 is connected to the fixed potential structure 12 (fixed potential pad, usually a pad grounded or connected to the power supply) of the first chip 1 (silicon chip) through the fuse 2. The fuse 2 is arranged in the scribe lane 5 between the first chip 1 and the second chip 4, and the fuse 2 plays a protective role during subsequent processing and packaging; as Figure 6 shown in Figure b, after packaging is completed, the floating potential structure 11 and the fixed potential structure 12 are connected through the packaging structure 9, and the fuse 2 is disconnected by means of current fusing, laser fusing or directly cutting the fuse 2 in the scribe lane 5 during the chip cutting process, so that it functions as a pad connecting the upper electrode 71 of the functional film layer 7 in the application.

[0049] Through the design of fuse 2 and the switching between the first state and the second state, this application can introduce a floating potential structure in chip design while avoiding breakdown phenomena caused by arc discharge during the production process, ensuring the realization of a unique design solution while avoiding breakdown and burning of wafers or chips, and reducing economic losses. This application is very suitable for chip design solutions that require additional processing of special functional material films in the packaging process and the connection between the processed materials and the original floating potential structure of the chip during the packaging process.

[0050] This application also discloses an electronic device including the chip structure described in the above embodiment.

[0051] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by terms such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present utility model.

[0052] In the present utility model, unless otherwise clearly specified and limited, terms such as "installed", "connected", "connected to", "fixed", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements or the interaction relationship between two elements, unless otherwise clearly limited. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0053] In the description of this specification, the description with reference to terms such as "this embodiment", "one embodiment", "some embodiments", "examples", "specific examples", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present utility model. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any at least one embodiment or example. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0054] Furthermore, the terms "first" and "second" are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present utility model, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise specifically defined.

[0055] The above are only the preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent replacements, and simple improvements made to the substantial content of the present utility model shall be included within the protection scope of the present utility model.

Claims

1. A chip structure, characterized in that: It comprises a first chip (1) and a fuse (2), The first chip (1) is provided with a floating potential structure (11) and a fixed potential structure (12); the fuse (2) is used to connect the floating potential structure (11) and the fixed potential structure (12); the fuse (2) comprises a first state of connecting the floating potential structure (11) and the fixed potential structure (12) during the manufacturing process of the chip structure, and a second state of disconnecting after the chip structure is manufactured or packaged.

2. The chip structure according to claim 1, characterized in that: The fuse (2) is arranged on the upper surface of the first chip (1).

3. The chip structure according to claim 2, characterized in that: The floating potential structure (11) extends a first connecting piece (111), the fixed potential structure (12) extends a second connecting piece (121), one end of the fuse (2) is connected to the first connecting piece (111), and the other end of the fuse (2) is connected to the second connecting piece (121).

4. The chip structure according to claim 1, characterized in that: It also includes a second chip (4), and the fuse (2) is arranged in a cutting path (5) between the first chip (1) and the second chip (4).

5. The chip structure according to claim 4, characterized in that: The floating potential structure (11) extends a third connector (112), the third connector (112) extends to the edge of the first chip (1), the fixed potential structure (12) extends a fourth connector (122), the fourth connector (122) extends to the edge of the first chip (1), one end of the fuse (2) is connected to the end of the third connector (112) at the edge of the first chip (1), and the other end of the fuse (2) is connected to the end of the fourth connector (122) at the edge of the first chip (1).

6. The chip structure according to any one of claims 1 to 5, characterized in that: The fuse (2) is switched from the first state to the second state by laser fusing.

7. The chip structure according to any one of claims 1 to 5, characterized in that: The fuse (2) switches from the first state to the second state by current fusing.

8. The chip structure according to claim 7, characterized in that: The width of the fuse (2) is the minimum width in the electrical structure of the layer where the fuse (2) is located.

9. The chip structure according to claim 7, characterized in that: A safety window is formed by maintaining a distance between the fuse (2) and other structures in the layer where the fuse (2) is located.

10. The chip structure according to claim 4 or 5, characterized in that: The fuse (2) is switched from the first state to the second state by cutting.

11. The chip structure according to any one of claims 1 to 5, characterized in that: A protective structural member (3) is provided around the fuse (2), the protective structural member (3) is connected to the fuse (2), and the width of the protective structural member (3) is greater than the width of the fuse (2).

12. The chip structure according to claim 11, characterized in that: The protective structural member (3) is in the shape of an interdigitated finger.

13. An electronic device, characterized in that: A chip structure comprising any one of claims 1 to 12.

Images