Piezoelectric valve

Abstract

The utility model provides a piezoelectric valve. The piezoelectric valve comprises a valve body with a fulcrum structure and a valve blade which is arranged on a first gap maintaining pad and a second gap maintaining pad of the valve blade and is coupled with the valve body. A plurality of membrane compressive stresses in one or more layers of the valve body deflect the valve blades to the valve body into a normally closed configuration. The first gap maintaining pad and the second gap maintaining pad are located on two opposite sides of the fulcrum structure.

Description

Technical Field

[0001] The utility model relates to a piezoelectric valve. Background Art

[0002] Multiple integrated circuits can be fabricated on a semiconductor wafer. Multiple semiconductor wafers can be stacked or bonded on top of each other to form a so-called three-dimensional integrated circuit. Some semiconductor wafers include multiple micro-electromechanical-system (MEMS) devices, which involve processes for forming multiple micro-structures and multiple nano-structures. Generally, multiple MEMS devices are built on multiple silicon wafers and implemented in multiple types of thin film materials. Applications of MEMS include inertial sensor applications (e.g., motion sensors, accelerometers, gyroscopes), pressure sensors, microfluidic devices (e.g., valves, pumps), movable mirrors, and imaging devices (e.g., micromachined ultrasonic transducers), etc. Summary of the Utility Model

[0003] In some cases, a micro-valve may consume a large amount of power and / or may be prone to leakage or diffusion due to the need to continuously apply voltage or other electrical input to configure the micro-valve into a closed structure. For applications in portable and wearable devices, this may result in low operational effectiveness of the micro-valve and / or additional power consumption, and may render the micro-valve unsuitable for implementation in small form factor (SFF) embodiments, such as in-ear headphones or microfluidics (e.g., lab-on-a-chip) operations.

[0004] The piezoelectric valve of the utility model can be formed through multiple semiconductor process technologies, causing the piezoelectric valve to deflect into a normally closed structure. The actuation of the piezoelectric valve can be achieved through the use of a piezoelectric drive layer of the piezoelectric valve. The piezoelectric valve can be implemented in various use cases, such as a dispensing valve for precise drug delivery, a pressure relief valve in a speaker device (e.g., in-ear headphones) to reduce the occlusion effect, a pressure control valve, and / or other types of valves configured for microfluidic control, etc. The normally closed structure of the piezoelectric valve enables the piezoelectric valve to operate as a normally closed valve in a power-saving manner.

[0005] The present utility model provides a piezoelectric valve. The piezoelectric valve includes a valve body comprising a fulcrum structure. The piezoelectric valve includes coupling a valve vane to the valve body on a first gap maintaining pad and a second gap maintaining pad of the valve vane. The first gap maintaining pad and the second gap maintaining pad are located on opposite sides of the fulcrum structure of the valve body. The thin film compressive stress in one or more layers of the valve body offsets the valve vane relative to the valve body into a normally closed structure.

[0006] A piezoelectric valve of the present utility model. The piezoelectric valve includes a valve vane. The piezoelectric valve includes a valve body, wherein a first valve driver is coupled to the valve body at a first end of the valve body, and a second valve driver is coupled to the valve body at a second end of the valve body relative to the first end, wherein the thin film compressive stress in one or more first layers of the first valve driver and the thin film compressive stress in one or more second layers of the second valve driver offset the valve vane relative to the valve body. Wherein the first valve driver includes: a first bottom electrode, a first piezoelectric driving layer on the first bottom electrode, and a first top electrode on the first piezoelectric driving layer. Wherein the second valve driver includes: a second bottom electrode, a second piezoelectric driving layer on the second bottom electrode, and a second top electrode on the second piezoelectric driving layer.

[0007] To make the above features and advantages of the present utility model more obvious and understandable, specific embodiments are given below and described in detail in conjunction with the accompanying drawings as follows. Description of the Drawings

[0008] Figure 1 is an exemplary diagram of an environment in which the systems and / or methods described herein can be implemented.

[0009] Figure 2A and 2B is an exemplary diagram of the piezoelectric valve described herein.

[0010] Figure 3A and 3B is a structural exemplary diagram of the piezoelectric valve described herein.

[0011] Figures 4A to 4F illustrates an embodiment of forming the valve body described herein.

[0012] Figures 5A to 5D illustrates an embodiment of forming the valve vane described herein.

[0013] Figures 6A to 6F illustrates an embodiment of forming the piezoelectric valve described herein.

[0014] Figures 7A to 7CIt is an example diagram of the valve actuator described herein.

[0015] Figures 8A to 8D It is an example diagram of the piezoelectric valve described herein.

[0016] Figure 9A and 9B It is an example diagram of the piezoelectric valve drive described herein.

[0017] Figures 10A to 10C It is an example diagram of the piezoelectric valve array configuration described herein.

[0018] Figure 11 It is an example diagram of the components of the device described herein.

[0019] Figure 12 It is a flowchart of an example process related to forming a piezoelectric valve.

[0020] Figures 13A to 13J It is illustrated as an example of forming a piezoelectric valve described herein.

[0021] Explanation of reference numerals:

[0022] 100: Environmental example

[0023] 102: Deposition tool

[0024] 104: Exposure tool

[0025] 106: Developer tool

[0026] 108: Etching tool

[0027] 110: Planarization tool

[0028] 112: Electroplating tool

[0029] 114: Bonding tool

[0030] 116: Wafer / die transfer tool

[0031] 200, 800, 1000, 1306: Piezoelectric valves

[0032] 202: Valve body

[0033] 204: Valve vane

[0034] 206, 206a, 206b: Valve actuators

[0035] 208: Valve port

[0036] 210: Valve plug

[0037] 212: Bonding pad

[0038] 214: Gap-maintaining pad

[0039] 216: Bonding pad

[0040] 218, 502: Substrate

[0041] 220: Dorsal cavity

[0042] 222, 222a, 222b: Fulcrum structure

[0043] 224: Buried oxide layer

[0044] 226: Semiconductor layer

[0045] 228: Isolation layer

[0046] 230: Crack

[0047] 232: Bottom electrode

[0048] 234: Top electrode

[0049] 236: Piezoelectric driving layer

[0050] 238: Metal interlayer dielectric

[0051] 240: Bottom contact structure

[0052] 242: Top contact structure

[0053] 300: Closing structure

[0054] 302: Opening structure

[0055] 400, 500, 600, 700, 702, 704, 900, 902, 1300: Embodiment

[0056] 402, 1302: Silicon-on-insulator wafer

[0057] 404, 408, 1304, 1308: Conductive layer

[0058] 406, 1306: Piezoelectric layer

[0059] 504: Groove

[0060] D1, D2, D3, D4: Dimension

[0061] 1002, 1004, 1006: Piezoelectric valve array structure

[0062] 1100: Device

[0063] 1110: Bus

[0064] 1120: Processor

[0065] 1130: Memory

[0066] 1140: Input component

[0067] 1150: Output component

[0068] 1160: Communication component

[0069] 1200: Process example

[0070] 1210, 1220, 1230, 1240, 1250, 1260: Block diagram Detailed implementation manners

[0071] The following disclosure provides many different embodiments or examples for implementing different features of the present utility model. Specific examples of components and configurations are described below to simplify the present utility model. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first feature and the second feature are formed in direct contact, and may also include embodiments where additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, the present utility model may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes, and in itself does not specify the relationship between the various embodiments and / or configurations discussed.

[0072] Furthermore, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", and the like may be used herein to describe the relationship of one component or feature to another component or feature as shown in the figures. In addition to the orientation depicted in the figures, the spatially relative terms are intended to cover different orientations of the components in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0073] A microvalve is a type of valve configured to control the flow of fluids, such as gases or liquids. The microvalve can be selectively operated into a closed configuration (preventing or restricting fluid flow through the microvalve) or an open configuration (allowing fluid flow through the microvalve via selective application of voltage or other electrical input to the microvalve). In some cases, the microvalve may consume a large amount of power and / or may be prone to leakage or diffusion due to the need to continuously apply voltage or other electrical input to the microvalve to configure it into a closed configuration. For applications in portable and / or wearable devices, this may result in low operational efficiency of the microvalve and / or additional power consumption, and may render the microvalve unsuitable for implementation in small form factor (SFF) embodiments, such as earbuds or microfluidics (e.g., lab-on-a-chip) operations.

[0074] Some embodiments described herein provide embodiments of piezoelectric valves and manufacturing methods. The piezoelectric valves described herein are a type of micro-electro-mechanical system (MEMS) valve that can be used for microfluidic control. The piezoelectric valve can be biased into a normally closed configuration and piezoelectric actuation of the piezoelectric valve can be achieved through the use of a piezoelectric-based actuation layer of the piezoelectric valve. The piezoelectric valve can be implemented in various use cases, such as a dispensing valve for precise drug delivery, a relief valve in a speaker device (e.g., earbuds) to reduce the occlusion effect, a pressure control valve, and / or other types of valves configured for microfluidic control, etc.

[0075] The piezoelectric valve can be formed through a plurality of semiconductor processing techniques described herein such that the piezoelectric valve is biased into a normally closed configuration without the use of an external power source. In the absence of an applied external power source, the piezoelectric actuation layer causes the valve leaf of the piezoelectric valve to be biased into a closed state. An external power source can be applied to the piezoelectric actuation layer to overcome the compressive film stress in the piezoelectric actuation layer to open the valve leaf from the normally closed configuration.

[0076] In this method, the normally closed structure of the plurality of piezoelectric valves described herein enables each piezoelectric valve to operate as a normally closed valve in a manner that reduces power consumption (e.g., as compared to a normally closed valve that achieves a normally closed structure by using an external power source). The plurality of piezoelectric valves offset to a normally closed structure can reduce the leakage and / or diffusion of the plurality of piezoelectric valves because the piezoelectric drive layers of the plurality of piezoelectric valves can be formed to maintain a thin film compressive stress, with the plurality of piezoelectric valves offset to a closed state, thereby reducing the likelihood of leakage and diffusion.

[0077] Figure 1 is an exemplary diagram of an environment in which the systems and / or methods described herein can be implemented. As Figure 1 shown, the exemplary environment 100 can include a plurality of semiconductor processing tools 102 to 114 and a wafer / die transport tool 116. The plurality of semiconductor processing tools 102 to 114 can include a deposition tool 102, an exposure tool 104, a developer tool 106, an etch tool 108, a planarization tool 110, a plating tool 112, a bonding tool 114 and / or other types of semiconductor processing tools. The plurality of tools in the exemplary environment 100 can be included in a semiconductor cleanroom, a semiconductor foundry, a semiconductor processing facility and / or a manufacturing facility, etc.

[0078] The deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various material types onto a substrate. In some embodiments, the deposition tool 102 includes a spin coating tool that can deposit a photoresist layer onto a substrate such as a wafer. In some embodiments, the deposition tool 102 includes a chemical vapor deposition (CVD) tool such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, a low-pressure CVD (LPCVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or other types of chemical vapor deposition tools. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or other types of physical vapor deposition tools. In some embodiments, the deposition tool 102 includes an epitaxial tool configured to form multiple layers and / or multiple regions of a device through epitaxial growth. In some embodiments, the environment example 100 includes multiple deposition tools 102 and / or multiple types of the deposition tools 102.

[0079] The exposure tool 104 is a semiconductor processing tool that can expose a photoresist layer to a radiation source, such as an ultraviolet light (UV) source (such as a deep UV light source, an extreme UV light (EUV) source, and / or a similar UV light source), an x-ray source, an electron beam (e-beam) source, and / or a similar radiation source. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern can include one or more semiconductor device layer patterns for forming one or more semiconductor devices, can include a pattern for forming one or more structures of a semiconductor device, can include a pattern for etching various parts of a semiconductor device, and / or a similar pattern. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or the same type of exposure tool. In some embodiments, the environment example 100 includes multiple exposure tools 104 and / or multiple types of exposure tools 104.

[0080] The developer tool 106 is a semiconductor processing tool that can develop a photoresist layer by exposing the photoresist layer to a radiation source to transfer a pattern from the exposure tool 104 to the photoresist layer for pattern development. In some embodiments, the developer tool 106 develops the pattern by removing multiple unexposed portions of the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by removing multiple exposed portions of the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by using a chemical developer to dissolve multiple exposed or unexposed portions of the photoresist layer. In some embodiments, the environment example 100 includes multiple developer tools 106 and / or multiple types of developer tools 106.

[0081] The etch tool 108 is a semiconductor processing tool that can etch various material types of a substrate, wafer, or semiconductor device. For example, the etch tool 108 can include a wet etch tool, a dry etch tool (e.g., an ion beam etch tool), and / or similar tools. In some embodiments, the etch tool 108 includes a reaction chamber filled with an etchant and a specific amount of substrate placed in the reaction chamber for a certain period of time to remove one or more portions of the substrate. In some embodiments, the etch tool 108 can use plasma etch or plasma-assisted etch to etch one or more portions of the substrate, which can involve using an ionized gas to etch one or more portions isotropically or directionally. In some embodiments, an ion beam is used to etch the substrate. In some embodiments, a wet chemical etchant is used to etch the substrate. In some embodiments, the environment example 100 includes multiple etch tools 108 and / or multiple types of developer tools 108.

[0082] The planarization tool 110 is a semiconductor processing tool capable of polishing or planarizing multiple layers of a wafer or semiconductor device. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or other types of planarization tools for polishing or planarizing layers or surfaces of deposited or plated materials. The planarization tool 110 can polish or planarize the surface of a semiconductor device using a combination of chemical or mechanical forces (e.g., chemical etching or free abrasive polishing). The planarization tool 110 can use abrasive grains and a corrosive chemical slurry together with a polishing pad and a retaining ring (e.g., typically having a diameter larger than the semiconductor device). The polishing pad and the semiconductor device can be pressed together by a dynamic polishing head and held in place by the retaining ring. The dynamic polishing head can rotate with different axes to remove material and even out any irregular topography of the semiconductor device, making the semiconductor device flat or planar. In some embodiments, the planarization tool 110 includes a wafer grinding tool configured to perform a wafer grinding operation to mechanically grind away material on a substrate. The wafer grinding tool can include a grinding wheel that rotates and uses abrasive grains on the grinding wheel to grind away material on the substrate when the grinding wheel rotates. In some embodiments, the environment example 100 includes multiple planarization tools 110 and / or multiple types of planarization tools 110.

[0083] The electroplating tool 112 is a semiconductor processing tool capable of electroplating a substrate (e.g., a wafer, a semiconductor device, and / or the like) or a portion thereof with one or more metals. For example, the electroplating tool 112 may include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a compound or alloy (e.g., a wafer, a semiconductor device, and / or the like) electroplating device, and / or one or more other electroplating devices of conductive materials, metals, and / or similar material types. In some embodiments, the environment example 100 includes a plurality of electroplating tools 112 and / or a plurality of types of electroplating tools 112.

[0084] The wafer / die transfer tool 116 includes a mobile robot, a robot arm, a tram or rail car, a tram or rail car, an overhead hoist transport (OHT) system, an automated material handling system (AMHS), and / or other device types configured to transfer a plurality of substrates and / or a plurality of semiconductor devices between a plurality of semiconductor processing tools 102 to 112; configured to transfer a plurality of substrates and / or a plurality of semiconductor devices between a plurality of different process chambers of the same semiconductor processing tool; and / or configured to transfer a plurality of substrates and / or a plurality of semiconductor devices to or from other locations, such as a wafer rack, a storage chamber, and / or similar locations. In some embodiments, the wafer / die transfer tool 116 may be a programmed device configured to travel along a specific path and / or may operate semi-automatically or fully automatically. In some embodiments, the environment example 100 includes a plurality of wafer / die transfer tools 116 and / or a plurality of types of wafer / die transfer tools 116.

[0085] For example, the wafer / die transfer tool 116 can be included in a cluster tool or other tool types, the tools including multiple process reaction chambers, and can be configured to transfer multiple substrates and / or multiple semiconductor devices among the multiple process reaction chambers; can be configured to transfer multiple substrates and / or multiple semiconductor devices between a process reaction chamber and a buffer area; can be configured to transfer multiple substrates and / or multiple semiconductor devices between a process reaction chamber and an interface tool such as an equipment front end module (EFEM); and / or can be configured to transfer multiple substrates and / or multiple semiconductor devices between a process reaction chamber and a transport carrier (e.g., a front opening unified pod (FOUP)), and so on. In some embodiments, the wafer / die transfer tool 116 can be included in a deposition tool 102 of a multi-reaction chamber (or cluster), the tool including a pre-cleaning process reaction chamber (e.g., for cleaning or removing oxides, oxidation, and / or other types of contamination or by-products from the substrate and / or semiconductor device) and multiple types of deposition process reaction chambers (e.g., process reaction chambers for depositing different material types, process reaction chambers for performing different types of deposition operations). In these embodiments, the wafer / die transfer tool 116 is configured to transfer multiple substrates and / or multiple semiconductor devices among the multiple process reaction chambers of the deposition tool 102 without breaking or removing the vacuum state (or at least a partial vacuum state) between the multiple process reaction chambers and / or between the multiple process operations in the deposition tool 102, as described above.

[0086] In some embodiments, one or more semiconductor process tools 102 to 114 can perform one or more semiconductor process operations as described above. For example, one or more semiconductor process tools 102 to 114 can perform multiple other semiconductor process operations as described above, such as those related to Figures 4A to 4F , Figures 5A to 5D , Figures 6A to 6F , Figure 12 and / or Figures 13A to 13J and so on.

[0087] Providing the number and arrangement of several devices as shown in Figure 1 as one or more examples. In reality, there can be multiple additional devices, fewer devices, multiple different devices, or multiple devices with different arrangements compared to Figure 1 . Furthermore, two or more devices as shown in Figure 1 can be implemented in a single device, or as shown in Figure 1The single device shown can be implemented as multiple, separate devices. Additionally, or alternatively, a set of devices (e.g., one or more devices) of the environmental paradigm 100 can perform one or more functions described by another set of devices of the environmental paradigm 100.

[0088] Figure 2A and Figure 2B For the exemplary diagram of the piezoelectric valve 200 described herein. The piezoelectric valve 200 can be a microelectromechanical system device, which can be fabricated using the multiple semiconductor processing techniques and operations described herein. The piezoelectric valve 200 can be used as a dispensing valve for precise drug delivery, a pressure relief valve for reducing the occlusion effect in speaker devices (e.g., earbuds), a pressure control valve, and / or other types of valves configured for microfluidic control, etc.

[0089] Figure 2A Shown is a cross-sectional view of the piezoelectric valve 200. As Figure 2A shown, the piezoelectric valve 200 can include a valve body 202 and a valve vane 204 coupled to the valve body 202. The valve vane 204 can be configured to selectively press against the valve body 202 to selectively open and close the piezoelectric valve 200. For example, when the valve vane 204 presses against the valve body 202, the piezoelectric valve 200 is in a closed configuration, and when the valve vane 204 is driven away from the valve body 202, the piezoelectric valve 200 is in an open configuration.

[0090] The valve body 202 can include a valve actuator 206, which is configured to drive the valve vane 204 to selectively open and close the valve port 208 of the piezoelectric valve 200. The valve actuator 206 can include an actuation lever, an actuation spring, an actuation beam, and / or other types of valve drive devices. The valve vane 204 can be configured to selectively press against the valve body 202 to selectively open and close the valve port 208 of the piezoelectric valve 200. The valve vane 204 can include a valve plug 210, which closes the valve port 208 when the valve plug 210 presses against the valve body 202 through the valve actuator 206, and opens the valve port 208 when the valve plug 210 is moved away from the valve body 202 through the valve actuator 206.

[0091] Multiple bonding pads 212 may be included on the valve driver 206 and may function as bonding positions for engaging the valve vane 204 with the valve body 202. The valve vane 204 may include a plurality of standoff pads 214 that interface with the multiple bonding pads 212. In other words, the valve vane 204 may engage with the multiple bonding pads 212 of the valve body 202 on the multiple standoff pads 214 of the valve vane 204. Multiple bonding layers 216 may be included on the multiple standoff pads 214 to assist and / or facilitate the bonding of the multiple bonding pads 212 and the multiple standoff pads 214.

[0092] The multiple bonding pads 212 may include one or more material types, such as silver (Ag), gold (Au), aluminum (Al), aluminum-copper (AlCu) alloy, silicon dioxide (SiO x such as SiO2), tin (Sn), and / or other materials, etc. The multiple standoff pads 214 may include one or more material types, such as silver, gold, aluminum, germanium (Ge), and / or silicon (Si), etc. In some embodiments, the multiple bonding pads 212 include gold and the multiple bonding layers 216 include gold. In some embodiments, the multiple bonding pads 212 include germanium and the multiple bonding layers 216 include aluminum-copper alloy. In some embodiments, the multiple bonding pads 212 include gold and the multiple bonding layers 216 include aluminum-copper alloy. In some embodiments, the multiple bonding pads 212 include silicon and the multiple bonding layers 216 include aluminum-copper alloy. In some embodiments, the multiple bonding pads 212 include silicon and the multiple bonding layers 216 include silicon dioxide (SiO x such as SiO2). In some embodiments, the multiple bonding pads 212 include gold and the multiple bonding layers 216 include tin. However, other material combinations of the multiple bonding pads 212 and the multiple bonding layers 216 are within the scope of the present utility model.

[0093] The valve body 202 may include a substrate 218 on which the valve driver 206 is supported. The substrate 218 may include a silicon substrate, a substrate formed of a silicon material, a group III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a germanium substrate, a silicon-germanium (SiGe) substrate, or other semiconductor substrate types, etc.

[0094] Multiple dorsal cavities 220 may be included within the substrate 218 to assist in driving the valve actuator 206. The multiple dorsal cavities 220 may further extend into the buried oxide layer 224 (e.g., to reduce the overall stiffness of the valve actuator 206). A fulcrum structure 222 may be included within the substrate 218, and the valve actuator 206 may be coupled to the fulcrum structure 222 at the end of the valve actuator 206 to enable the valve actuator 206 to drive the valve blade 204 to selectively open and close the valve port 208. The valve blade 204 may be coupled to the valve body 202 on a first gap-maintaining pad 214 at a first end of the valve actuator 206 within the valve body 202, and on a second gap-maintaining pad 214 at a second end of the valve actuator 206 relative to the first end, where the first gap-maintaining pad 214 and the second gap-maintaining pad 214 are located on opposite sides of the fulcrum structure 222.

[0095] The valve body 202 (and the valve actuator 206) may further include a buried oxide layer 224 above the substrate 218, a semiconductor layer 226 above and / or on the buried oxide layer 224, and an isolation layer 228 above and / or on the semiconductor layer 226. A plurality of cracks 230 may be formed through the semiconductor layer 226 and through the isolation layer 228 to separate multiple portions of the semiconductor layer 226 and multiple portions of the isolation layer 228 included within the valve actuator 206 from multiple portions of the semiconductor 226 and multiple portions of the isolation layer 228 included within the remainder of the valve body 202. The plurality of cracks 230 enables the valve actuator 206 to be driven freely relative to the valve body 202.

[0096] The buried oxide layer 224 may include an oxide-containing material such as silicon oxide (SiO x ), silicon oxynitride (SiO N ), tetraethyl orthosilicate oxide, carbon doped silicon oxide, and / or other oxide-containing materials. The semiconductor layer 226 may include silicon (Si), group III-V compound semiconductor materials such as gallium arsenide (GaAs), germanium (Ge), silicon germanium (SiGe), and / or other types of semiconductor substrates. The isolation layer 228 may include one or more dielectric materials such as silicon oxide (SiO x ), silicon nitride (Si x N y) Silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), carbon doped silicon oxide, and / or other dielectric materials.

[0097] The valve driver 206 of the valve body 202 may include a bottom electrode 232 and a top electrode 234. The bottom electrode 232 may be included above and / or on the isolation layer 228, and the top electrode 234 may be included above the bottom electrode 232. The bottom electrode 232 and the top electrode 234 may each include one or more electrically conductive metallic materials, such as silver (Ag), gold (Au), aluminum (Al), copper, tin (Sn), cobalt (Co), ruthenium (Ru), platinum (Pt), tungsten (W), molybdenum (Mo), titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), electrically conductive metallic materials, electrically conductive ceramic materials, metal alloy materials, other electrically conductive materials, or combinations thereof.

[0098] The valve driver 206 of the valve body 202 may include a piezoelectric drive layer 236 between the bottom electrode 232 and the top electrode 234. The piezoelectric drive layer 236 may provide the actuation mechanism of the valve driver 206. The actuation mechanism of the piezoelectric drive layer 236 may be based on the inverse piezoelectric effect. For example, an electrical input (e.g., voltage, electrical current) may be provided to the piezoelectric drive layer 236 through the bottom electrode 232 and / or the top electrode 234. The electrical input may cause an electric field to be generated in the piezoelectric drive layer 236, resulting in the piezoelectric drive layer 236 bending, deflecting, and / or undergoing other deformations relative to the initial position of the piezoelectric drive layer. The deformation may be in a direction nearly perpendicular to the top surface of the piezoelectric drive layer 236. This causes the remaining portion of the valve driver 206 to bend, shift, expand, extend, and / or undergo other deformations, resulting in the valve driver 206 being actuated relative to the fulcrum structure 222. When the electrical input to the piezoelectric drive layer 236 is removed or not applied, the piezoelectric drive layer 236 (and the valve driver 206) may return to the initial position.

[0099] The piezoelectric drive layer 236 may include lead zirconate titanate (PZT) and / or other piezoelectric materials. Additionally and / or alternatively, the piezoelectric drive layer 236 may include aluminum nitride (AlN), gallium phosphate (GaPO4), lanthanum gallium silicate (La3Ga5SiO 14 ), barium titanate (BaTiO3), potassium niobate (KNbO3), lithium niobate (LiNbO3), lithium tantalate (LiTaO3), sodium tungstate (Na2WO3), zinc oxide (ZnO), or a combination thereof.

[0100] The intermetal dielectric (IMD) layer 238 may be included above the valve body 202 and above the valve driver 206. The intermetal dielectric layer 238 may include providing electrical isolation for one or more layers and / or structures of the valve body 202 and / or the valve driver 206. The intermetal dielectric layer 238 may include one or more dielectric materials, such as silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), carbon doped silicon oxide, and / or other dielectric materials. In some embodiments, a plurality of bonding pads 212 may be included above and / or on the intermetal dielectric layer 238.

[0101] The bottom electrode 232 can be electrically and / or physically coupled to the bottom contact structure 240, and the top electrode 234 can be electrically and / or physically coupled to the top contact structure 242. The bottom contact structure 240 can be electrically coupled to the bottom electrode 232 by a power source (e.g., a voltage source, a current source), and the top contact structure 242 can be electrically coupled to the top electrode 234 by a power source. The bottom contact structure 240 and the top contact structure 242 can each include a via, a trench, a pillar, a columnar structure, a metallization layer, a conductive trace, a dual damascene structure, and / or other types of conductive structures. The bottom contact structure 240 and the top contact structure 242 can each include one or more electrically conductive materials, such as silver (Ag), gold (Au), aluminum (Al), copper (Cu), tin (Sn), cobalt (Co), ruthenium (Ru), platinum (Pt), tungsten (W), molybdenum (Mo), titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), an electrically conductive metal material, an electrically conductive ceramic material, a metal alloy material, other electrically conductive materials, or a combination thereof.

[0102] Figure 2B Shown is a top view of the piezoelectric valve 200. As Figure 2B shown, the valve blade 204 can be approximately rectangular in the top view of the piezoelectric valve 200. In other embodiments, the valve blade 204 can be other shapes, such as approximately square, approximately circular, approximately spiral, approximately annular, irregular, and / or other shapes. A plurality of gap-maintaining pads 214 can extend laterally outward from multiple sides of the valve blade 204 and be above one or more valve drivers 206. In some embodiments, the piezoelectric valve 200 includes a plurality of valve drivers 206. For example, the piezoelectric valve 200 can include a first valve driver 206 coupled to one or more first gap-maintaining pads 214 on a first side of the valve blade 204, and also include a second valve driver 206 coupled to one or more second gap-maintaining pads 214 on a second side of the valve blade 204 opposite the first side. The (plural) valve drivers 206 can include a plurality of elongated structures that extend substantially parallel to the valve blade 204.

[0103] As described above, provide Figure 2A and 2B as an example. Other multiple examples can be different from Figure 2A and 2B the related description.

[0104] Figure 3A and 3BIt is an exemplary diagram of the structure of the piezoelectric valve described herein. Figure 3A It is shown as the closed structure 300 and Figure 3B It is shown as the open structure 302.

[0105] As Figure 3A shown, the valve plug 210 of the valve vane 204 presses against the valve body 202 to form the closed structure 300, causing the valve port 208 to close. In the case of the closed structure 300, fluid (e.g., gas, liquid) is prevented from flowing through the valve port 208. The piezoelectric valve 200 can be manufactured as a normally closed piezoelectric valve. In these embodiments, the closed structure 300 is a normally closed structure, in which the valve vane 204 is deflected with respect to the valve body 202 without applying an electrical input to the valve actuator 206. An electrical input can be applied to the valve actuator 206 (e.g., through the bottom electrode 232 and / or through the top electrode 234 to the piezoelectric drive layer 236) to overcome the deflection and open the valve port 208 by moving the valve plug 210 of the valve vane 204 away from the valve body 202.

[0106] The deflection of the valve vane 204 with respect to the valve body 202 can be achieved by manufacturing the valve actuator 206 to include a mechanical deflection that presses the valve vane 204 against the valve body 202 without using an electrical input. For example, and as Figure 3A shown, the valve actuator 206 can be an actuation lever that includes a bend or deflection that biases the valve vane 204 with respect to the valve body 202 without applying an electrical input to the valve actuator 206. The valve actuator 206 can be deflected downward from the fulcrum structure 222 due to the compressive stress of one or more layers of the valve body 202 and / or the valve actuator 206. For example, the thin film compressive stress in the isolation layer 228, the thin film compressive stress in the piezoelectric drive layer 236, and / or the thin film compressive stress in the metal interlayer dielectric 238 may cause the end of the valve actuator 206 (e.g., the remote end of the valve actuator 206 from the fulcrum structure 222) to be deflected downward from the fulcrum structure 222. The thin film compressive stress of one or more layers may cause a combined overall compressive stress in the valve actuator 206, resulting in the valve actuator 206 being deflected downward with respect to the back cavity 220.

[0107] As described above, the compressive stress of the thin films in the multiple layers may be achieved by forming the multiple layers and butt-joining the multiple layers with other multiple layers having different coefficients of thermal expansion (CTE). For example, the compressive stress of the thin film in the isolation layer 228 may result from a CTE mismatch (e.g., a difference in the coefficients of thermal expansion) between the coefficient of thermal expansion of the isolation layer 228 and that of the semiconductor layer 226, and / or may result from a CTE mismatch between the coefficient of thermal expansion of the isolation layer 228 and that of the bottom electrode 232. The coefficient of thermal expansion of the isolation layer 228 (e.g., it may be silicon dioxide (SiO2), and its coefficient of thermal expansion is about 5.6×10 -6 K -1 ) may be greater than the coefficient of thermal expansion of the semiconductor layer 226 (e.g., it may be silicon (Si), and its coefficient of thermal expansion is about 2.5×10 -6 K -1 ), and the coefficient of thermal expansion of the isolation layer 228 may be less than the coefficient of thermal expansion of the bottom electrode 232 (e.g., it may be platinum (Pt), and its coefficient of thermal expansion is about 9×10 -6 K -1 ).

[0108] As another example, the compressive stress of the thin film in the piezoelectric driving layer 236 may result from a CTE mismatch between the coefficient of thermal expansion of the piezoelectric driving layer 236 and that of the bottom electrode 232, and / or may result from a CTE mismatch between the coefficient of thermal expansion of the piezoelectric driving layer 236 and that of the top electrode 234. The coefficient of thermal expansion of the piezoelectric driving layer 236 (e.g., it may be lead zirconate titanate (PZT), and its coefficient of thermal expansion is about 6.7×10 -6 K -1 ) may be less than the coefficient of thermal expansion of the bottom electrode 232. The coefficient of thermal expansion of the piezoelectric driving layer 236 may also be greater than the coefficient of thermal expansion of the top electrode 234 (e.g., it may be platinum (Pt), and its coefficient of thermal expansion is about 9×10 -6 K -1 ).

[0109] As another example, the compressive stress of the thin film in the metal interlayer dielectric 238 may result from a CTE mismatch between the coefficient of thermal expansion of the metal interlayer dielectric 238 and that of the top electrode 234. The coefficient of thermal expansion of the metal interlayer dielectric 238 (e.g., it may be silicon dioxide (SiO2), and its coefficient of thermal expansion is about 5.6×10 -6 K -1 ) may be less than the coefficient of thermal expansion of the top electrode 234.

[0110] As Figure 3BAs shown, the valve plug 210 of the valve vane 204 is spaced apart from the valve body 202 to form an open structure 302, enabling the valve port 208 to open. In the case of the open structure 302, fluid (e.g., gas, liquid) is allowed to flow through the valve port 208.

[0111] As Figure 3B Further shown, the open structure 302 can be achieved by applying an electrical input 304 through the bottom electrode 232 and / or the top electrode 234 to the piezoelectric drive layer 236. The electrical input 304 can include voltage, current, and / or other types of electrical inputs. The electrical input 304 causes the piezoelectric drive layer 236 to change from pressure to tension, enabling the valve actuator 206 to overcome the (multiple) thin-film compressive stresses in the valve actuator 206. In this method, the valve actuator 206 changes from a downward deflection (e.g., deflecting towards the dorsal cavity 220) to an upward deflection or bending, thereby lifting the valve plug 210 from the valve body 202 and opening the valve port 208.

[0112] In this method, the piezoelectric valve 200 can include a valve body 202 and a valve vane 204 coupled to the valve body 202, where the thin-film compressive stresses in one or more layers (e.g., the isolation layer 228, the piezoelectric drive layer 236, the metal interlayer dielectric layer 238) offset the valve vane 204 relative to the valve body 202 to a normally closed structure (e.g., the closed structure 300).

[0113] In some alternative embodiments, the piezoelectric valve 200 can be fabricated as a normally closed piezoelectric valve 200. In these embodiments, the open structure 302 is a normally open structure, where due to the thin-film tension in one or more layers in the valve actuator 206, the valve vane 204 is spaced apart from the valve body 202 without applying an electrical input to the valve actuator 206. An electrical input can be applied to the valve actuator 206 (e.g., through the bottom electrode 232 and / or through the top electrode 234 to the piezoelectric drive layer 236) to overcome the offset and move the valve plug 210 of the valve vane 204 away from the valve body 202 to close the valve port 208 into the closed structure 300.

[0114] As described above, provide Figure 3A and Figure 3B as an example. Multiple other examples can be different from Figure 3A and Figure 3B the related description.

[0115] Figures 4A to 4F An embodiment 400 of forming the valve body 202 is illustrated herein. FIG. Figures 4A to 4F One or more semiconductor process operations related to the above are performed using one or more semiconductor devices 102 to 114. In some embodiments, Figures 4A to 4FOne or more of the semiconductor processing operations described above are performed using another semiconductor tool.

[0116] Returning Figure 4A a silicon-on-insulator (SOI) wafer 402 can be provided. The silicon-on-insulator (SOI) wafer 402 can include a substrate 218, a buried oxide layer 224, and a semiconductor 226. The silicon-on-insulator (SOI) wafer 402 can be a circular substrate with a diameter of about 200 millimeters, about 300 millimeters, or other sizes such as 450 millimeters, etc. The silicon-on-insulator (SOI) wafer 402 can alternatively be any square, rectangular, curved, or other non-circular workpiece, such as a polygonal substrate.

[0117] In some embodiments, the thickness of the substrate 218 can be in the range of about 200 micrometers to about 1000 micrometers. If the thickness of the substrate 218 is less than about 200 micrometers, the substrate 218 may not be rigid enough to form the valve body 202. Conversely, if the thickness of the substrate 218 is at least about 200 micrometers, the substrate 218 may be rigid enough. If the thickness of the substrate 218 is greater than about 1000 micrometers, the valve body 202 may be too thick and may result in an inefficient valve body 202 process, such as during subsequent thinning operations of the substrate 218. However, other thickness values of the substrate 218 and other ranges outside of about 200 micrometers to about 1000 micrometers are within the scope of the present invention.

[0118] In some embodiments, the thickness of the buried oxide layer 224 can be in the range of about 1000 angstroms to about 5 micrometers. If the thickness of the buried oxide layer 224 is less than about 1000 angstroms, the buried oxide layer 224 may not provide an etch stop barrier sufficient to form the plurality of backside cavities 220 in the substrate 218. Conversely, the buried oxide layer 224 can provide an etch stop barrier sufficient to form the plurality of backside cavities 220 in the substrate 218. If the thickness of the buried oxide layer 224 is greater than about 5 micrometers, the silicon-on-insulator (SOI) wafer 402 may be too thick and may result in an inefficient valve body 202 process. However, other thickness values of the buried oxide layer 224 and other ranges outside of about 1000 angstroms to about 5 micrometers are within the scope of the present invention.

[0119] In some embodiments, the thickness of the semiconductor layer 226 can be in the range of about 1000 angstroms to about 50 micrometers. If the thickness of the semiconductor layer 226 is less than about 1000 angstroms, the semiconductor layer 226 may not provide sufficient stiffness for the valve driver 206, and vice versa, the semiconductor layer 226 may provide sufficient stiffness for the valve driver 206; if the thickness of the semiconductor layer 226 is greater than about 50 micrometers, the semiconductor layer 226 is too rigid for the valve driver 206 to open the valve port 208, and vice versa, when the thickness of the semiconductor layer 226 is less than or equal to about 50 micrometers, the valve driver 206 may be able to open the valve port 208. However, other thickness values of the semiconductor layer 226 and other ranges outside of about 1000 angstroms to about 50 micrometers are within the scope of the present utility model.

[0120] As Figure 4B shown, one or more layers can be formed over and / or on top of the silicon-on-insulator wafer 402. For example, the isolation layer 228 can be formed over and / or on top of the semiconductor layer 226 of the silicon-on-insulator wafer 402. As another example, the conductive layer 404 can be formed over and / or on top of the isolation layer 228. As another example, the piezoelectric layer 406 can be formed over and / or on top of the conductive layer 404. As another example, the conductive layer 408 can be formed over and / or on top of the piezoelectric layer 406.

[0121] In some embodiments, the deposition tool 102 can perform physical vapor deposition (PVD) operations, atomic layer deposition (ALD) operations, chemical vapor deposition (CVD) operations, epitaxy operations, oxidation operations, as Figure 1 described in relation to other types of deposition operations and / or other suitable deposition operation methods, for depositing the isolation layer 228. In some embodiments, after depositing the isolation layer 228, the planarization tool 110 can be used to planarize the isolation layer 228.

[0122] In some embodiments, the deposition tool 102 and / or the electroplating tool 112 can perform chemical vapor deposition (CVD) operations, physical vapor deposition (PVD) operations, atomic layer deposition (ALD) operations, electroplating operations, as Figure 1 described in relation to other types of deposition operations and / or other suitable deposition operation methods, to deposit the conductive layer 404. In some embodiments, a seed layer is deposited first, and the conductive layer 404 is deposited on the seed layer. In some embodiments, after depositing the conductive layer 404, the planarization tool 110 can be used to planarize the conductive layer 404.

[0123] In some embodiments, a physical vapor deposition operation is performed using deposition tool 102 to form piezoelectric layer 406. In some embodiments, deposition tool 102 is used to perform a solution gelling (sol-gel) process to form piezoelectric layer 406. The sol-gel process may include using deposition tool 102 to deposit a piezoelectric material (e.g., lead zirconate titanate (PZT) and / or other piezoelectric materials) or a precursor for forming a piezoelectric material. The precursor may be deposited in a solution (i.e., a "sol") that also includes a solvent. Deposition tool 102 may use spin coating techniques and / or other techniques suitable for depositing the solution.

[0124] Deposition tool 102 may be used to perform a cure (or dry) operation, where the solution may then be cured for a period of time. After the cure operation, deposition tool 102 may be used to raise the temperature of the solution to perform a calcination operation. The calcination operation may be performed to initiate the crystallization of the precursor into a piezoelectric material. Deposition tool 102 may then be used to further raise the temperature to perform a rapid thermal oxidation (RTO) operation to fully crystallize the piezoelectric material in a well-defined crystal orientation. Deposition tool 102 may be used to perform multiple curing-RTO cycles to form piezoelectric layer 406. For example, deposition tool 102 may be used to perform a first cure operation, then a first RTO operation, then a second cure operation, then a second RTO operation, and so on until a predetermined thickness for piezoelectric layer 406 is reached. In some embodiments, four curing-RTO cycles (referred to as a 4C4R process) are performed to form piezoelectric layer 406. However, other numbers of curing-RTO cycles are also within the scope of the present invention.

[0125] In some embodiments, deposition tool 102 and / or plating tool 112 may be used to deposit conductive layer 408 in a chemical vapor deposition operation, a physical vapor deposition operation, an atomic layer deposition operation, a plating operation, as Figure 1 described in relation to other types of deposition operations and / or other suitable deposition operations. In some embodiments, a seed layer is first deposited, and conductive layer 408 is deposited on the seed layer. In some embodiments, after depositing conductive layer 408, planarization tool 110 may be used to planarize conductive layer 408.

[0126] In some embodiments, the thickness of the isolation layer 228 is in the range of about 1000 angstroms to about 10 micrometers. If the thickness of the isolation layer 228 is less than about 1000 angstroms, the thin film compressive stress in the isolation layer 228 may not be sufficient to deflect the valve vane 204 relative to the valve body 202. Conversely, the thin film compressive stress in the isolation layer 228 may enable the isolation layer 228 to deflect the valve vane 204 relative to the valve body 202 and may enable the isolation layer 228 to resist the electrical input when an electrical input is applied to open the valve port 208. If the thickness of the isolation layer 228 is greater than about 10 micrometers, the isolation layer 228 may be too rigid for the valve actuator 206 to open the valve port 208, and film peeling may occur. However, other thickness values of the isolation layer 228 and other ranges outside of about 1000 angstroms to about 10 micrometers are within the scope of the present invention.

[0127] In some embodiments, the thickness of the conductive layer 404 is in the range of about 500 angstroms to about 1 micrometer. If the thickness of the conductive layer 404 is less than about 500 angstroms, multiple voids may occur in the conductive layer 404 and / or the conductive layer 404 may have a higher power consumption (which may cause an increase in the resistance-capacitance (RC) time constant of the valve actuator 206). If the thickness of the conductive layer 404 is at least about 500 angstroms, the likelihood of void formation in the conductive layer 404 may be reduced and / or minimized, and / or the power consumption may be reduced. If the thickness of the conductive layer 404 is greater than about 1 micrometer, the cost of manufacturing the piezoelectric valve 200 may be too high, and / or the valve actuator 206 may not be able to deflect the valve vane 204 relative to the valve body 202. However, other thickness values of the conductive layer 404 and other ranges outside of about 500 angstroms to about 1 micrometer are within the scope of the present invention.

[0128] In some embodiments, the thickness of the piezoelectric layer 406 can be in the range of about 2000 angstroms to about 5 micrometers. If the thickness of the piezoelectric layer 406 is less than about 2000 angstroms, the grain size in the piezoelectric layer 406 may be too small, and it may cause a reduction in piezoelectric performance. If the thickness of the piezoelectric layer 406 is at least 2000 angstroms, the piezoelectric performance may enable the valve actuator 206 to operate. If the thickness of the piezoelectric layer 406 is greater than about 5 micrometers, the cost of manufacturing the piezoelectric valve 200 may be too high. However, other thickness values of the piezoelectric layer 406 and other ranges outside of about 2000 angstroms to about 1 micrometer are within the scope of the present invention.

[0129] In some embodiments, the thickness of the conductive layer 408 can be in the range of about 500 angstroms to about 1 micron. If the thickness of the conductive layer 408 is less than about 500 angstroms, multiple voids may occur in the conductive layer 408 and / or the conductive layer 408 may have a higher power consumption (which may lead to an increase in the resistance-capacitance time constant of the valve driver 206); if the thickness of the conductive layer 408 is at least 500 angstroms, the possibility of void formation in the conductive layer 408 may be reduced and / or minimized, and / or the power consumption may be reduced; if the thickness of the conductive layer 408 is greater than about 1 micron, the cost of manufacturing the piezoelectric valve 200 may be too high, and / or the valve driver 206 may not be able to deflect the valve blade 204 relative to the valve body 202. However, other thickness values of the conductive layer 408 and other ranges outside of about 500 angstroms to about 1 micron are within the scope of the present utility model.

[0130] As Figure 4C shown, the conductive layer 404, the piezoelectric layer 406, and the conductive layer 408 can be etched to form the bottom electrode 232, the top electrode 234, and the piezoelectric drive layer 236. In some embodiments, the pattern in the photoresist layer is used to etch the conductive layer 404, the piezoelectric layer 406, and the conductive layer 408 to form the bottom electrode 232, the top electrode 234, and the piezoelectric drive layer 236. In these embodiments, the deposition tool 102 can be used to form the photoresist layer on the conductive layer 408. The exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The developer tool 106 can be used to develop and remove multiple portions of the photoresist layer to expose the pattern. The etch tool 108 can be used to etch the conductive layer 404, the piezoelectric layer 406, and the conductive layer 408 according to the pattern to form the bottom electrode 232, the top electrode 234, and the piezoelectric drive layer 236. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some embodiments, a photoresist removal tool can be used to remove multiple remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique for etching the conductive layer 404, the piezoelectric layer 406, and the conductive layer 408 according to the pattern.

[0131] As Figure 4D shown, the metal interlayer dielectric layer 238 can be formed on the valve body 202. For example, the metal interlayer dielectric layer 238 can be deposited on multiple portions of the isolation layer 238, multiple portions of the multiple bottom electrodes 232, multiple portions of the multiple top electrodes 234, and / or multiple portions of the multiple piezoelectric drive layers 236. The deposition portion 102 can perform a physical vapor deposition operation, an atomic layer deposition operation, a chemical vapor deposition operation, an epitaxial operation, an oxidation operation, asFigure 1 Other types of deposition operations and / or other suitable ways of deposition operations as described above are used to deposit the metal interlayer dielectric layer 238.

[0132] As Figure 4E As shown, a plurality of bonding pads 212, a plurality of bottom contact structures 240, and a plurality of top contact structures 242 can be formed on the valve body 202. For example, a plurality of bonding pads can be formed on the metal interlayer dielectric layer 238. As another example, the bottom contact structure 240 can be formed on the bottom electrode 232 (e.g., such that the bottom electrode 232 and the bottom contact structure 240 are physically and / or electrically coupled) and on the metal interlayer dielectric layer 238. As another example, the top contact structure 242 can be formed on the top electrode 234 (e.g., such that the top electrode 234 and the top contact structure 242 are physically and / or electrically coupled) and on the metal interlayer dielectric layer 238.

[0133] The deposition tool 102 and / or the electroplating tool 112 can perform chemical vapor deposition operations, physical vapor deposition operations, atomic layer deposition operations, electroplating operations, such as Figure 1 Other types of deposition operations and / or other suitable ways of deposition operations as described above are used to deposit the plurality of bonding pads 212, the plurality of bottom contact structures 240, and / or the plurality of top contact structures 242. In some embodiments, a seed layer is first deposited, and the plurality of bonding pads 212, the plurality of bottom contact structures 240, and / or the plurality of top contact structures 242 are deposited on the seed layer.

[0134] In some embodiments, the etching tool 108 is used to remove multiple portions of the metal interlayer dielectric layer 238 above the bottom electrode 232 and above the top electrode 234 to form multiple openings in the metal interlayer dielectric layer 238 above the bottom electrode 232 and above the top electrode 234. The deposition tool 102 and / or the electroplating tool 112 can be used to deposit the bottom contact structure 240 in the opening above the bottom electrode 232 and to deposit the top contact structure 242 in the opening above the top electrode 234.

[0135] As Figure 4FAs shown, multiple portions of the metal interlayer dielectric layer 238, multiple portions of the isolation layer 238, multiple portions of the semiconductor layer 226, and / or multiple portions of the buried oxide layer 224 may be removed to define the valve driver 206 of the valve body 202. In some embodiments, a pattern in a photoresist layer is used to etch the metal interlayer dielectric layer 238, the isolation layer 228, the semiconductor layer 226, and / or the buried oxide layer 224 to form multiple cracks 230 in the metal interlayer dielectric layer 238, the isolation layer 228, the semiconductor layer 226, and / or the buried oxide layer 224 to define the valve driver 206. In these embodiments, a deposition tool 102 may be used to form a photoresist layer on multiple bonding pads 212, the metal interlayer dielectric layer 238, the bottom contact structure 240, and / or on the top contact structure 242. An exposure tool 104 may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developer tool 106 may be used to develop and remove multiple portions of the photoresist layer to expose the pattern. An etch tool 108 may be used to etch the metal interlayer dielectric layer 238, the isolation layer 228, the semiconductor layer 226, and / or the buried oxide layer 224 according to the pattern to form multiple cracks 230 in the metal interlayer dielectric layer 238, the isolation layer 228, the semiconductor layer 226, and / or the buried oxide layer 224. In some embodiments, the etch operation includes a plasma etch operation, a wet chemical etch operation, and / or other types of etch operations. In some embodiments, a photoresist removal tool may be used to remove multiple remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique to etch the metal interlayer dielectric layer 238, the isolation layer 228, the semiconductor layer 226, and / or the buried oxide layer 224 according to the pattern.

[0136] As described above, provide Figures 4A to 4F as an example. Multiple other examples may differ from Figures 4A to 4F the relevant description.

[0137] Figures 5A to 5D Illustrated is embodiment 500 for forming the valve vane 204 described herein. In some embodiments, Figures 5A to 5D one or more of the semiconductor process operations described above are performed using one or more semiconductor devices 102 to 114. In some embodiments, Figures 5A to 5D one or more of the semiconductor process operations described above are performed using another semiconductor tool.

[0138] Return to Figure 5A, the valve vane 204 can be formed from a substrate 502. The substrate 502 includes a silicon substrate, a substrate formed of a silicon material, a group III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a germanium substrate, a silicon germanium (SiGe) substrate, or other semiconductor substrate types, etc. The substrate 502 can include a circular substrate having a diameter of about 200 mm, about 300 mm, or other dimensions such as 450 mm, etc. The substrate 502 can alternatively be any square, rectangular, curved, or other non-circular workpiece, such as a polygonal substrate.

[0139] As Figure 5B shown, multiple portions of the substrate 502 can be removed to form the valve vane 204 and to form the valve plug(s) 210 extending from the valve vane 204 and multiple gap-maintaining pads 214.

[0140] In some embodiments, a pattern of a photoresist layer is used to etch the substrate 502 to form the valve vane 204, the valve plug(s) 210, and multiple gap-maintaining pads 214. In some embodiments, a deposition tool 102 can be used to form a photoresist layer on the substrate 502. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developer tool 106 can be used to develop and remove multiple portions of the photoresist layer to expose the pattern. An etch tool 108 can be used to etch the substrate 502 according to the pattern to form the valve vane 204, the valve plug(s) 210, and multiple gap-maintaining pads 214. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some embodiments, the etching operation includes a dry reactive ion etch (DRIE) operation or a Bosch etching operation (e.g., an etching operation including multiple deposition and etching cycles). In some embodiments, a photoresist removal tool can be used to remove multiple remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique for etching the substrate 502 according to the pattern.

[0141] In some embodiments, the height of the valve plug 210 (e.g., the distance from the valve vane 204 to the top surface of the valve plug 210) can be in the range of about 700 microns to about 800 microns. However, other values within this range are all within the scope of the present utility model.

[0142] As Figure 5CAs shown, multiple bonding layers 216 may be formed over and / or on top of multiple gap-maintaining pads 214. A deposition tool 102 and / or an electroplating tool 112 may be used to deposit the multiple bonding layers 216 in a chemical vapor deposition operation, a physical vapor deposition operation, an atomic layer deposition operation, an electroplating operation, other types of deposition operations as described related to Figure 1 and / or other suitable deposition operation manners. In some embodiments, a seed layer is deposited first, and the multiple bonding layers 216 are deposited on the seed layer. In some embodiments, a blanket layer is deposited, and an etching tool 108 is used to etch the blanket layer to form the multiple bonding layers 216.

[0143] As Figure 5D shown, multiple trenches 504 may be formed in multiple ends of the valve vane 204. When the valve vane 204 is engaged with the valve body 202 to form the piezoelectric valve 200, the multiple trenches 504 may enable the valve vane 204 to fit over the valve body 202. In some embodiments, a pattern of a photoresist layer is used to etch the valve vane 204 to form the multiple trenches 504. In these embodiments, a deposition tool 102 may be used to form the photoresist layer on the valve vane 204. An exposure tool 104 may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developer tool 106 may be used to develop and remove multiple portions of the photoresist layer to expose the pattern. An etching tool 108 may be used to etch the valve vane 204 according to the pattern to form the multiple trenches 504. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some embodiments, the etching operation includes a reactive ion dry etching operation or a Bosch etching operation. In some embodiments, a photoresist removal tool may be used to remove multiple remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique for etching the valve vane 204 according to the pattern. In some embodiments, the multiple trenches 504 may be formed to a height of about 10 micrometers to about 300 micrometers. However, other values within this range are within the scope of the present utility model.

[0144] As described above, provided Figures 5A to 5D as an example. Other multiple examples may be different from Figures 5A to 5D the related description.

[0145] Figures 6A to 6F Illustrated is an embodiment 600 of forming the piezoelectric valve 200 described herein. In some embodiments, Figures 6A to 6F one or more semiconductor process operations related as described are performed using one or more semiconductor devices 102 to 114. In some embodiments, Figures 6A to 6FOne or more of the semiconductor processing operations described above are performed using another semiconductor tool. In some embodiments, Figures 6A to 6F One or more of the semiconductor processing operations described above are performed Figures 4A to 4F and / or Figures 5A to 5D after one or more of the semiconductor processing operations described above.

[0146] As Figure 6A and 6B shown, the valve vane 204 may be attached to the valve body 202. Specifically, the valve vane 204 may be joined to the valve body 202. The valve vane 204 and the valve body 202 may be joined on a plurality of bonding pads 212 of the valve body 202 and on a plurality of gap-maintaining pads 214 of the valve vane 204. The bonding layer 216 on the plurality of gap-maintaining pads 214 may assist and / or facilitate the joining of the plurality of bonding pads 212 and the plurality of gap-maintaining pads 214.

[0147] A bonding tool 114 may be used to join the valve vane 204 and the valve body 202. The bonding tool 114 may perform a eutectic bonding operation, a metal-to-metal bonding operation, a dielectric-to-dielectric bonding operation, a hybrid bonding operation (which may include a combination of metal-to-metal bonding and dielectric-to-dielectric bonding), a fusion bonding operation (also known as direct bonding) and / or other types of bonding operations to join the valve vane 204 to the valve body 202.

[0148] As Figure 6CAs shown, multiple portions of the substrate 218 and multiple portions of the buried oxide layer 224 can be removed to form a dorsal cavity 220 and a fulcrum structure 222 in the substrate 218. Multiple portions of the substrate 218 and multiple portions of the buried oxide layer 224 can be removed from the dorsal side of the substrate 218, leaving the valve driver 206 from the substrate 218. In some embodiments, a pattern in a photoresist layer is used to etch the substrate 218 and the buried oxide layer 224 to remove multiple portions of the substrate 218 and multiple portions of the buried oxide layer 224. In these embodiments, a deposition tool 102 can be used to form a photoresist layer on the dorsal side of the substrate 218. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developer tool 106 can be used to develop and remove multiple portions of the photoresist layer to expose the pattern. An etch tool 108 can be used to etch the substrate 218 and the buried oxide layer 224 according to the pattern to remove multiple portions of the substrate 218. In some embodiments, the etch operation includes a plasma etch operation, a wet chemical etch operation, and / or other types of etch operations. In some embodiments, the etch operation includes a reactive ion dry etch operation or a Bosch etch operation (e.g., an etch operation including multiple deposition and etch cycles). In some embodiments, a photoresist removal tool can be used to remove multiple remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique to etch the substrate 218 and the buried oxide layer 224 according to the pattern.

[0149] Before removing multiple portions of the substrate 218, a wafer grinding operation can be performed to thin the substrate 218 (e.g., reduce the thickness of the substrate 218). The substrate 218 can be thinned to shorten the process time of the etch process and / or reduce the etchant consumption of the etch process to remove multiple portions of the substrate 218. A planarization tool 110 (e.g., a grinding tool) can perform the wafer grinding operation to mechanically grind away the silicon material on the substrate 218.

[0150] As Figure 6D shown, the piezoelectric valve 200 can be located on a frame 602 for further processing. The frame 602 can support the piezoelectric valve 200 during subsequent semiconductor processing operations.

[0151] As Figure 6EAs shown, a wafer grinding operation can be performed to thin the valve blade 204 (e.g., reduce the thickness of the valve blade 204). The valve blade can be thinned such that the overall height of the piezoelectric valve 200 meets a height threshold. The height threshold can correspond to design parameters of a specific package or application of the piezoelectric valve 200, etc. A planarization tool 110 (e.g., a grinding tool) can perform the wafer grinding operation to mechanically grind away the silicon material on the valve blade 204. In some embodiments, after the wafer grinding operation, the thickness of the valve blade 204 can be in the range of about 10 microns to about 300 microns. If the thickness of the valve blade 204 is less than about 10 microns, the valve blade 204 may not be rigid enough to prevent fluid from flowing through the valve orifice 208; if the thickness of the valve blade 204 is at least about 10 microns, the valve blade 204 may be rigid enough to prevent fluid from flowing through the valve orifice 208; if the thickness of the valve blade 204 is greater than about 300 microns, the weight of the valve blade 204 may prevent the actuator 206 from lifting the valve blade 204; if the thickness of the valve blade 204 is close to about 300 microns, the weight of the valve blade 204 may be such that the actuator 206 is sufficient to lift the valve blade 204. However, other thickness values of the valve blade 204 and other ranges outside of about 10 microns to about 300 microns are within the scope of the present invention.

[0152] As Figure 6F shown, the piezoelectric valve 200 can be diced (e.g., from a silicon-on-insulator wafer 402) and packaged. In this method, the piezoelectric valve 200 can be fabricated such that the piezoelectric valve 200 is a normally closed piezoelectric valve. The piezoelectric valve 200 can be in a closed configuration 300 (e.g., a normally closed configuration), where in the absence of an electrical input applied to the valve actuator 206, the valve blade 204 is offset with respect to the valve body 202. The mismatch in the coefficient of thermal expansion between the isolation layer 228 and the bottom electrode 232, the mismatch in the coefficient of thermal expansion between the piezoelectric drive layer 236, the bottom electrode 232, and the top electrode 234, and / or the mismatch in the coefficient of thermal expansion between the metal interlayer dielectric 238 and the top electrode 234 may cause bending of the valve actuator 206, thereby offsetting the valve blade 204 with respect to the valve body 202.

[0153] As described above, provided Figures 6A to 6F as an example. Other examples may be different from Figures 6A to 6F the relevant description.

[0154] Figures 7A to 7C is an example diagram of the valve actuator 206 described herein. The example of the valve actuator 206 shown in Figures 7A to 7C can be included in a piezoelectric valve, such as the piezoelectric valve 200, the piezoelectric valve 800 described in relation to Figures 8A to 8B and / or other piezoelectric valves.

[0155] Figure 7A Embodiment 700 showing a valve driver 206 including a drive lever, the drive lever being cantilevered by a fulcrum structure 222. As Figure 7A Further shown, the valve driver 206 can be deflected downward into a closed configuration 302, and when an electrical input is applied to the valve driver 206, the valve driver 206 can be deflected upward into an open configuration 302.

[0156] Figure 7B Embodiment 702 showing a valve driver 206 including a rotary drive lever, as Figure 7B Further shown, the valve driver 206 can be approximately straight into a closed configuration 302, and when an electrical input is applied to the valve driver 206, the valve driver 206 can be partially rotated and deflected upward into an open configuration 302.

[0157] Figure 7C Embodiment 704 showing a valve driver 206 including a drive spring, as Figure 7C Further shown, the valve driver 206 can be approximately straight into a closed configuration 302, and when an electrical input is applied to the valve driver 206, the valve driver 206 can extend into an open configuration 302.

[0158] As described above, provided Figures 7A to 7C as an example. Many other examples may differ from Figures 7A to 7C the relevant description.

[0159] Figures 8A to 8D is an embodiment diagram of the piezoelectric valve 800 described herein. Figure 8A Shown is a cross-sectional view of the piezoelectric valve 800, and Figure 8B Shown is a top view of the piezoelectric valve 800.

[0160] As Figure 8A shown, the piezoelectric valve 800 can include an arrangement similar to that of the plurality of components 202 to 242 of the piezoelectric valve 200. However, the piezoelectric valve 200 includes a plurality of valve drivers 206, including valve driver 206a and valve driver 206b. Valve drivers 206a and 206b may enable composite driving of the valve vane 204, such that the valve vane 204 can be precisely moved and / or may enable a wider or larger opening of the valve port 208 (e.g., relative to a single valve driver 206 of the piezoelectric valve).

[0161] The plurality of valve drivers 206a and the plurality of valve drivers 206b can include, as shown in Figure 2AA multi-layer and / or multi-structure arrangement such as the associated valve driver 206. For example, the valve driver 206a may include a portion of the buried oxide layer 224, a portion of the semiconductor layer 226, a portion of the isolation layer 228, a bottom electrode 232, a top electrode 234, a piezoelectric drive layer 236 between the bottom electrode 232 and the top electrode 234, and a portion of the metal interlayer dielectric layer 238. The valve driver 206b may similarly include a portion of the buried oxide layer 224, a portion of the semiconductor layer 226, a portion of the isolation layer 228, a bottom electrode 232, a top electrode 234, a piezoelectric drive layer 236 between the bottom electrode 232 and the top electrode 234, and a portion of the metal interlayer dielectric layer 238. The plurality of valve drivers 206a and 206b may also include respective pluralities of bottom contact structures 240 and pluralities of top contact structures 242. The plurality of thin film compressive stresses in one or more layers of the valve driver 206a (e.g., in the isolation layer 228, in the piezoelectric drive layer 236, and / or in the metal interlayer dielectric layer 238) and the plurality of thin film compressive stresses in one or more layers of the valve driver 206b (e.g., in the isolation layer 228, in the piezoelectric drive layer 236, and / or in the metal interlayer dielectric layer 238) can offset the valve vane 204 relative to the valve body 202 into the closed configuration 300, the same as Figure 3A the piezoelectric valve 200 shown. The valve driver 206a may be supported and deflected relative to the fulcrum structure 222a in the substrate 218, and the valve driver 206b may be supported and deflected relative to the fulcrum structure 222b in the substrate 218.

[0162] As Figure 8A Further shown, the valve vane 204 may be joined to and / or otherwise attached to the valve driver 206a on the first bonding pad 212 of the valve driver 206a. The valve vane 204 may be joined to the first bonding pad 212 on the first gap-maintaining pad 214 and the first bonding layer 216; the valve vane 204 may be joined to and / or otherwise attached to the valve driver 206b on the second bonding pad 212 of the valve driver 206b. The valve vane 204 may be joined to the second bonding pad 212 on the second gap-maintaining pad 214 and the second bonding layer 216. Attaching the valve vane 204 to the plurality of valve drivers 206a and 206b enables the opposite ends of the valve vane 204 to move independently, thereby enabling the valve vane 204 to be compound-driven. In some embodiments, the length of the valve driver 206a (corresponding to Figure 8A the dimension D1) is greater than the length of the valve driver 206b (corresponding to Figure 8AThe length of the valve actuator 206a (dimension D1) can be longer than the length of the valve actuator 206b (dimension D2). The longer length of the valve actuator 206a can cause the valve actuator 206a to lift the first end of the valve vane 204 (i.e., the position where the valve plug 210 is located) to a higher height than the valve actuator 206b lifts the second end of the valve vane 204. This can make the opening of the valve port 208 wider or larger (e.g., compared to a piezoelectric valve with a single valve actuator). In some embodiments, the length of the valve actuator 206a (dimension D1) and the length of the valve actuator 206b (dimension D2) are approximately the same length. In other embodiments, the length of the valve actuator 206b (dimension D2) is greater than the length of the valve actuator 206a (dimension D1).

[0163] Figure 8B Shown is a top view of the piezoelectric valve 800. As Figure 8B shown, the valve vane 204 can include a shape that is approximately rectangular in the top view of the piezoelectric valve 800. In other embodiments, the valve vane 204 can include other shapes, such as approximately square, approximately circular, approximately spiral, approximately annular, irregular, and / or other shapes. A plurality of gap maintenance pads 214 can extend laterally outward from multiple sides of the valve vane 204 and cover one or more valve actuators 206a and one or more valve actuators 206b. In some embodiments, the piezoelectric valve 800 includes a plurality of valve actuators 206a and / or a plurality of valve actuators 206b. For example, the piezoelectric valve 800 can include a plurality of valve actuators 206a that are coupled to respective multiple first gap maintenance pads 214 at the first end and on opposite sides of the valve vane 204, and a plurality of valve actuators 206b that are coupled to respective multiple second gap maintenance pads 214 at the second end (relative to the first end) and on opposite sides of the valve vane 204. The plurality of valve actuators 206a and 206b can include a plurality of extension structures that extend out nearly parallel to the valve vane 204.

[0164] The piezoelectric valve 800 can be formed using multiple semiconductor process technologies and methods related to Figures 4A to 4F , Figures 5A to 5D and / or Figures 6A to 6F . During the operation of forming a plurality of cracks 230 through the metal interlayer dielectric layer 238, the isolation layer 228, the semiconductor layer 226, and the buried oxide layer 224 (shown in Figure 4F ), additional cracks 230 can be formed to define the valve actuator 206a and the valve actuator 206b. In addition, during the operation of removing multiple portions of the substrate 218 (shown in Figure 6C ), additional multiple portions of the substrate 218 can be removed to define a plurality of fulcrum structures 222a and 222b and leave the valve actuator 206a and the valve actuator 206b.

[0165] Figure 8CAnd Figure 8D is an embodiment diagram of the structure of the piezoelectric valve 800 described herein. Figure 8C It is shown as the closed structure 300 and Figure 8D is shown as the open structure 302.

[0166] As Figure 8C shown, the valve plug 210 of the valve vane 204 presses against the valve body 202 to form the closed structure 800, so that the valve port 208 is closed. In the case of the closed structure 800, fluids (e.g., gases, liquids) are prevented from flowing through the valve port 208. The piezoelectric valve 800 can be manufactured as a normally closed piezoelectric valve. In these embodiments, the closed structure 300 is a normally closed structure, in which the valve vane 204 is offset against the valve body 202 without applying an electrical input to the valve drivers 206a and 206b. An electrical input can be applied to the valve drivers 206a and 206b (e.g., through a plurality of bottom electrodes 232 and / or through a plurality of top electrodes 234 to a plurality of piezoelectric drive layers 236) to overcome the offset, and the valve plug 210 of the valve vane 204 is moved away from the valve body 202 to open the valve port 208.

[0167] As Figure 8D further shown, the open structure 302 can be achieved by applying an electrical input 304 through a plurality of bottom electrodes 232 and / or a plurality of top electrodes 234 to a plurality of piezoelectric drive layers 236. The electrical input 304 can include voltage, current, and / or other types of electrical input. The electrical input 304 causes the plurality of piezoelectric drive layers 236 to change from pressure to tension, enabling the valve driver 206 to overcome the (multiple) thin film compressive stress in the valve driver 206. In this method, the valve driver 206 changes from deflecting downward (e.g., deflecting towards the dorsal cavity 220) to deflecting upward or bending, thereby lifting the valve plug 210 from the valve body 202 and opening the valve port 208.

[0168] As described above, provide Figure 8A and 8D as examples. Other multiple examples can be different from Figure 8A and 8D the relevant descriptions.

[0169] Figure 9A and 9B are embodiment diagrams of the piezoelectric valve drive described herein. As Figure 9A shown in the embodiment 900 of Figure 9AIn Embodiment 900, valve drivers 206a and 206b lift valve vane 204 from valve body 202 to the same distance, such that valve port 208 is opened to a size of D3.

[0170] As Figure 9B shown in Embodiment 902, valve vane 204 can be lifted from valve body 202 of gasket valve 800 into an open configuration 302 to open valve port 208. Valve driver 206a can drive from pivot structure 222a, and valve driver 206b can drive from pivot structure 222b. In Figure 9B Embodiment 902, valve drivers 206a and 206b lift valve vane 204 from valve body 202 to different distances. Specifically, valve driver 206a can lift valve vane 204 from valve body 202 to a greater distance than valve driver 206b. This enables valve port 208 to be opened to a size of D4, which is larger than D3. This enables a larger effective pressure relief area of the gasket valve. Valve driver 206a can form a longer length (dimension D1) than the length of valve driver 206b (dimension D2), such that valve driver 206a can lift valve vane 204 from valve body 202 to a greater distance than valve driver 206b.

[0171] As described above, provide Figure 9A and 9B as examples. Multiple other examples can be different from Figure 9A and 9B the related descriptions.

[0172] Figures 10A to 10C is an example diagram of a piezoelectric valve array structure described herein. In some embodiments, the multiple piezoelectric valve array structures related to Figures 10A to 10C can include multiple piezoelectric valves 1000. Multiple piezoelectric valves 1002 can be implemented through multiple piezoelectric valves 200, through multiple piezoelectric valves 800, and / or through a combination of multiple piezoelectric valves 200 and multiple piezoelectric valves 800. Generally, multiple piezoelectric valves 1000 can be arranged in a piezoelectric valve array to improve valve performance and / or meet one or more performance parameters.

[0173] Figure 10A is an example diagram of a piezoelectric valve array structure 1002 including multiple piezoelectric valves 1000. The multiple piezoelectric valves 1000 in the embodiment of piezoelectric valve array structure 1002 can be approximately square piezoelectric valves and can be arranged in a grid pattern.

[0174] Figure 10BAn example diagram showing a piezoelectric valve array structure 1004 including a plurality of piezoelectric valves 1000. The plurality of piezoelectric valves 1000 in the piezoelectric valve array structure 1004 embodiment can be a plurality of piezoelectric valves in an approximate triangular shape and can be arranged in a hexagon pattern.

[0175] Figure 10C An example diagram showing a piezoelectric valve array structure 1006 including a plurality of piezoelectric valves 1000. The plurality of piezoelectric valves 1000 in the piezoelectric valve array structure 1006 embodiment can be a plurality of piezoelectric valves in an approximate triangular shape and can be arranged in an octagon pattern.

[0176] As described above, provided Figures 10A to 10C as an example. Other examples may be different from Figures 10A to 10C the relevant description.

[0177] Figure 11 is an example diagram of components of the device 1100 described herein. In some embodiments, one or more semiconductor process tools 102 to 114 and / or wafer / die transfer tools 116 may include one or more devices 1100 and / or one or more components of the device 1100. As Figure 11 shown, the device 1100 may include a bus 1110, a processor 1120, a memory 1130, an input component 1140, an output component 1150, and / or a communication component 1160.

[0178] The bus 1110 may include one or more components to enable wired and / or wireless communication among the plurality of components of the device 1100. The bus 1110 may be connected to two or more Figure 11The components are coupled together, for example, via operative coupling, communicative coupling, electronic coupling, and / or electric coupling. For example, bus 1110 may include an electrical connection (e.g., wire, trace, and / or lead) and / or a wireless bus. Processor 1120 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field-programmable gate array, an application-specific integrated circuit, and / or other types of processing components. Processor 1120 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 1120 may include one or more processors that can be programmed to implement one or more of the operations or processes described elsewhere herein.

[0179] Memory 1130 may include volatile and / or nonvolatile memory. For example, memory 1130 may include random access memory (RAM), read only memory (ROM), hard disk drive, and / or other types of memory (e.g., flash memory, magnetic memory, and / or optical memory). Memory 1130 may include internal memory (e.g., random access memory, read only memory, or hard disk drive) and / or removable memory (e.g., removable via universal serial bus). Memory 1130 may be a non-transitory computer-readable medium. Memory 1130 may store information related to the operation of device 1100, one or more instructions, and / or software (e.g., one or more software applications). In some embodiments, memory 1130 may include one or more memories coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 1120), such as via bus 1110. The communicative coupling between processor 1120 and memory 1130 may enable processor 1120 to read and / or process information stored in memory 1130 and / or store data in memory 1130.

[0180] The input component 1140 may enable the device 1100 to receive inputs, such as user inputs and / or sensed inputs. For example, the input component 1140 may include a touch screen, a keyboard, a keypad, a mouse, buttons, a microphone, a switch, sensors, a global positioning system sensor, a global navigation satellite system sensor, an accelerometer, a gyroscope, and / or a driver. The output component 1150 may enable the device 1100 to provide outputs, such as via a display, a speaker, and / or a light-emitting diode. The communication component 1160 may enable the device 1100 to communicate with a plurality of other devices via a wired connection and / or a wireless connection. For example, the communication component 1160 may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and / or an antenna.

[0181] The device 1100 may implement one or more of the operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., the memory 1130) may store a set of instructions (e.g., one or more instructions or program codes) to be executed by the processor 1120. The processor 1120 may execute the set of instructions to implement one or more of the operations or processes described herein. In some embodiments, through one or more processors 1120, the execution of the set of instructions causes one or more processors 1120 and / or the device 1100 to perform one or more of the operations or processes described herein. In some embodiments, hardware circuitry may be used, instead of or in combination with the plurality of instructions, to perform one or more of the operations or processes described herein. Additionally, or alternatively, the processor 1120 may be configured to perform one or more of the operations or processes described herein. Thus, the embodiments described herein are not limited to hardware circuitry and software.

[0182] Provided Figure 11 The number and arrangement of the components shown are illustrative. The device 1100 may include more than Figure 11additional components, fewer components, different components, or different arrangements of components than the apparatus shown. Additionally, or alternatively, one or a group of components (e.g., one or more components) of apparatus 1100 may perform one or more of the functions performed by another group of components of apparatus 1100.

[0183] Figure 12 is a flowchart of process example 1200 related to forming a piezoelectric valve. In some embodiments, Figure 12 one or more process blocks of are performed using one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102 to 114). Additionally, or alternatively, Figure 12 one or more process blocks of may be performed using one or more components of apparatus 1100, such as processor 1120, memory 1130, input component 1140, output component 1150, and / or communication component 1160.

[0184] As Figure 12 shown, process 1200 may include forming an isolation layer (block 1210) over a substrate. For example, one or more of semiconductor processing tools 102 to 114 may be used to form isolation layer 228 over a substrate (e.g., substrate 218, silicon-on-insulator wafer 402), as described herein.

[0185] As Figure 12 further shown, process 1200 may include forming a bottom electrode of a piezoelectric valve over the isolation layer (block 1220). For example, one or more of semiconductor processing tools 102 to 114 may be used to form bottom electrode 232 of a piezoelectric valve (e.g., piezoelectric valve 200, piezoelectric valve 800) over isolation layer 228, as described herein.

[0186] As Figure 12 further shown, process 1200 may include forming a piezoelectric drive layer of a piezoelectric valve over the bottom electrode (block 1230). For example, one or more of semiconductor processing tools 102 to 114 may be used to form piezoelectric drive layer 236 of a piezoelectric valve over bottom electrode 232, as described herein.

[0187] As Figure 12 further shown, process 1200 may include forming a top electrode of a piezoelectric valve over the piezoelectric drive layer (block 1240). For example, one or more of semiconductor processing tools 102 to 114 may be used to form top electrode 234 of a piezoelectric valve over piezoelectric drive layer 236, as described herein.

[0188] As Figure 12As further shown, process 1200 may include removing multiple portions of the isolation layer and multiple portions of the substrate after forming the top electrode to form the valve driver (block diagram 1250) of the piezoelectric valve. For example, one or more semiconductor process tools 102 to 114 may be used to remove multiple portions of the isolation layer 228 and multiple portions of the substrate 218 after forming the top electrode 234 to form the valve driver 206 of the piezoelectric valve, as described herein.

[0189] As Figure 12 As further shown, process 1200 may include attaching the valve blade to the valve driver (block diagram 1260). For example, one or more semiconductor process tools 102 to 114 may be used to attach the valve blade 204 to the valve driver 206, as described herein.

[0190] Process 1200 may include additional embodiments, such as those described below and / or any combination of any single embodiment or multiple embodiments related to one or more other processes described elsewhere.

[0191] In a first embodiment, the mismatch in the coefficient of thermal expansion between the piezoelectric drive layer 236, the bottom electrode 232, and the top electrode 234 causes the bending of the valve driver 206 after removing multiple portions of the isolation layer 228 and multiple portions of the substrate 218 to form the valve driver 206.

[0192] In a second embodiment, whether used alone or in combination with the first embodiment, the bending of the valve driver 206 offsets the valve blade 204 of the piezoelectric valve 200 with respect to the valve body 202.

[0193] In a third embodiment, whether used alone or in combination with one or more of the first and second embodiments, attaching the valve blade 204 to the valve driver 206 includes joining the plurality of gap maintenance pads 214 of the valve blade 204 to the valve driver 206 using a plurality of bonding pads 212.

[0194] In a fourth embodiment, whether used alone or in combination with one or more of the first to third embodiments, process 1200 includes forming a plurality of bonding pads 216 on the plurality of gap maintenance pads 214, wherein the plurality of gap maintenance pads 214 of the valve blade 204 are joined to the valve driver 206 using a plurality of bonding layers 216 and a plurality of bonding pads 212.

[0195] In a fifth embodiment, whether used alone or in combination with one or more of the first to fourth embodiments, process 1200 includes attaching the valve blade 204 to another valve driver 206b of the piezoelectric valve 200.

[0196] In the sixth embodiment, whether used alone or in combination with one or more of the first through fifth embodiments, process 1200 includes removing a plurality of portions on the back side of substrate 218 after attaching valve vane 204 to valve body 202 to form a valve cavity (e.g., back cavity 220) of piezoelectric valve 200.

[0197] In some embodiments, although Figure 12 showing a plurality of exemplary block diagrams of process 1200, process 1200 includes additional block diagrams, fewer block diagrams, different block diagrams, or differently arranged block diagrams than those shown in the block diagrams. Additionally, or alternatively, two or more block diagrams of process 1200 may be executed simultaneously. Figure 12

[0198] Figures 13A to 13J Illustrating embodiment 1300 of forming piezoelectric valve 800 as shown herein. In some embodiments, one or more semiconductor process operations associated with Figures 13A to 13J are performed using one or more semiconductor devices 102 to 104. In some embodiments, one or more semiconductor process operations associated with Figures 13A to 13J are performed using another semiconductor tool.

[0199] Returning to Figure 13A , a silicon-on-insulator wafer 1302 may be provided. The silicon-on-insulator wafer 1302 may include substrate 218, buried oxide layer 224, and semiconductor layer 226.

[0200] As Figure 13B shown, one or more layers may be formed above (over) and / or on the silicon-on-insulator wafer 1302. For example, isolation layer 228 may be formed above (over) and / or on semiconductor layer 226 of the silicon-on-insulator wafer 1302. As another example, conductive layer 1304 may be formed above (over) and / or on isolation layer 228. As another example, piezoelectric layer 1306 may be formed above (over) and / or on conductive layer 1304. As another example, conductive layer 1308 may be formed above (over) and / or on piezoelectric layer 1306.

[0201] As Figure 13C shown, conductive layer 1304, piezoelectric layer 1306, and conductive layer 1308 may be etched to form a plurality of bottom electrodes 232, a plurality of top electrodes 234, and a plurality of piezoelectric drive layers 236.

[0202] As Figure 13D ​As shown, the inter-metal dielectric layer 238 may be formed on the valve body 202. For example, the inter-metal dielectric layer 238 may be deposited on multiple portions of the isolation layer 228, multiple portions of the multiple bottom electrodes 232, multiple portions of the multiple top electrodes 234, and / or multiple portions of the piezoelectric drive layer 236.

[0203] As Figure 13E shown, multiple bonding pads 212, multiple bottom contact structures 240, and multiple top contact structures 242 may be formed on the valve body 202. For example, the multiple bonding pads 212 may be formed on the inter-metal dielectric layer 238. As another example, the bottom contact structures 240 may be formed on the bottom electrodes 232 (e.g., such that the bottom electrodes 232 are physically and / or electrically coupled to the bottom contact structures 240) and on the inter-metal dielectric layer 238. As another example, the top contact structures 242 may be formed on the top electrodes 234 (e.g., such that the top electrodes 234 are physically and / or electrically coupled to the top contact structures 242) and on the inter-metal dielectric layer 238.

[0204] As Figure 13F shown, multiple portions of the inter-metal dielectric layer 238, multiple portions of the isolation layer 228, multiple portions of the semiconductor layer 226, and / or multiple portions of the buried oxide layer 224 are removed to define multiple valve drivers 206a and 206b of the valve body 202.

[0205] As Figure 13G and 13H shown, the valve vane 204 may be attached to the valve body 202. The valve vane 204 may be formed using multiple processing techniques related to Figures 5A to 5D as described. The valve vane 204 may be bonded to the valve body 202. The valve vane 204 and the valve body 202 may be bonded to multiple bonding pads 212 on the valve body 202 and to multiple gap-maintaining pads 214 on the valve vane 204. A bonding layer 216 on the multiple gap-maintaining pads 214 may assist and / or facilitate the bonding of the multiple bonding pads 212 and the multiple gap-maintaining pads 214.

[0206] As Figure 13IAs shown, multiple portions of the substrate 218 and multiple portions of the buried oxide layer 224 can be removed to form multiple backside cavities 220 and multiple fulcrum structures 222a and 222b in the substrate 218. Multiple portions of the substrate 218 and multiple portions of the buried oxide layer 224 can be removed from the backside of the substrate 218, leaving multiple valve drivers 206a and 206b on the substrate 218. After previously removing multiple portions of the substrate 218 and multiple portions of the buried oxide layer 224, a wafer grinding operation can be performed to thin the substrate 218 (e.g., reduce the thickness of the substrate 218). The substrate 218 can be thinned to reduce the process time and / or etchant consumption of an etching operation to remove multiple portions of the substrate 218. A planarization tool 110 (e.g., a grinding tool) can perform a wafer grinding operation to mechanically grind away the silicon material on the substrate 218.

[0207] As Figure 13J shown, a wafer grinding operation can be performed to thin the valve vane 204 (e.g., reduce the thickness of the valve vane 204). The valve vane 204 can be thinned such that the overall height of the piezoelectric valve 800 meets a height threshold. The piezoelectric valve 800 can be diced (e.g., from a silicon-on-insulator wafer 1302) and packaged.

[0208] As described above, providing Figures 13A to 13J as an example. Multiple other examples can be different from Figures 4A to 4F the relevant description.

[0209] In this method, a piezoelectric valve can be formed using multiple semiconductor technologies such that the piezoelectric valve is biased into a normally closed structure. The actuation of the piezoelectric valve can be achieved through the use of a piezoelectric actuation layer of the piezoelectric valve. The piezoelectric valve can be implemented in a variety of use cases, such as a dispensing valve for precise drug delivery, a pressure relief valve in a speaker device (e.g., an earbud) to reduce the occlusion effect, a pressure control valve, and / or other types of valves configured for microfluidic control, etc. The normally closed structure of the piezoelectric valve enables the piezoelectric valve to operate as a normally closed valve in a power consumption-reducing manner.

[0210] As described in detail above, some embodiments described herein provide a piezoelectric valve. The piezoelectric valve includes a valve body including a fulcrum structure. The piezoelectric valve includes coupling a valve vane to the valve body on a first gap maintenance pad and a second gap maintenance pad of the valve vane. The first gap maintenance pad and the second gap maintenance pad are located on opposite sides of the fulcrum structure of the valve body. A thin film compressive stress in one or more layers of the valve body biases the valve vane with respect to the valve body into a normally closed structure.

[0211] As described in detail above, some embodiments described herein provide a method. The method includes forming an isolation layer over a substrate. The method includes forming a bottom electrode of a piezoelectric valve over the isolation layer. The method includes forming a piezoelectric drive layer of the piezoelectric valve over the bottom electrode. The method includes forming a top electrode of the piezoelectric valve over the piezoelectric drive layer. The method includes removing a plurality of portions of the isolation layer and a plurality of portions of the substrate after forming the top electrode to form a valve actuator of the piezoelectric valve. The method includes attaching a valve vane to the valve actuator.

[0212] As described in detail above, some embodiments described herein provide a piezoelectric valve. The piezoelectric valve includes a valve vane. The piezoelectric valve includes a valve body, the valve body including a first valve actuator coupled to the valve body at a first end of the valve body and a second valve actuator coupled to the valve body at a second end of the valve body relative to the first end, wherein a thin film compressive stress in one or more first layers of the first valve actuator and a thin film compressive stress in one or more second layers of the second valve actuator offset the valve vane with respect to the valve body.

[0213] As used herein, depending on the context, "meeting a threshold" may refer to a value greater than a threshold, greater than or equal to a threshold, less than a threshold, less than or equal to a threshold, equal to a threshold, not equal to a threshold, or the like.

[0214] The features of several embodiments are outlined above so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or obtain the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures can be made with various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure.

Claims

1. A piezoelectric valve, characterized in that: include: The valve body includes a fulcrum structure; and The valve blade is coupled to the valve body on a first gap maintaining pad and a second gap maintaining pad of the valve blade, wherein a plurality of film compressive stresses in one or more layers of the valve body bias the valve blade toward the valve body into a normally closed configuration, and Wherein, the first gap maintaining pad and the second gap maintaining pad are located on opposite sides of the fulcrum structure.

2. The piezoelectric valve according to claim 1, characterized in that: The one or more layers include a piezoelectric drive layer of a valve actuator contained within the valve body.

3. The piezoelectric valve according to claim 2, characterized in that: Wherein the piezoelectric drive layer is included between a bottom electrode of the valve actuator and a top electrode of the valve actuator.

4. The piezoelectric valve according to claim 1, characterized in that: wherein the first gap maintaining pad is located on a first end portion of the valve actuator of the valve body; and The second gap maintaining pad is located on a second end portion of the valve actuator of the valve body opposite to the first end portion.

5. The piezoelectric valve according to claim 4, characterized in that: wherein the valve blade includes a valve plug adjacent to the first gap maintaining pad; wherein the crack in the one or more semiconductor layers and the isolation layer is located between the valve plug and the first gap maintaining pad; and The plurality of film compressive stresses in the one or more layers bias the valve plug toward the valve body.

6. A piezoelectric valve, characterized in that: include: Valve blade; as well as Valve body, comprising: coupling a first valve actuator to the valve body at a first end of the valve body; as well as coupling a second valve actuator to the valve body at a second end of the valve body opposite the first end, A plurality of film compressive stresses in one or more first layers of the first valve actuator and a plurality of film compressive stresses in one or more second layers of the second valve actuator bias the valve blade toward the valve body.

7. The piezoelectric valve according to claim 6, characterized in that: wherein the valve blade comprises a valve plug; and The multiple film compressive stresses in the one or more first layers of the first valve actuator and the multiple film compressive stresses in the one or more second layers of the second valve actuator bias the valve plug toward the valve body.

8. The piezoelectric valve according to claim 6, characterized in that wherein the valve blade comprises a first gap maintaining pad and a second gap maintaining pad; wherein the first gap maintaining pad is coupled to the first valve driver; and The second gap maintaining pad is coupled to the second valve driver.

9. The piezoelectric valve according to claim 8, characterized in that: In the top view of the piezoelectric valve, the first gap maintaining pad and the second gap maintaining pad extend laterally outward from one or more sides of the valve blade.

10. The piezoelectric valve according to claim 6, characterized in that The first valve driver comprises: a first bottom electrode; a first piezoelectric drive layer on the first bottom electrode; and a first top electrode on the first piezoelectric drive layer; and The second valve driver comprises: a second bottom electrode; a second piezoelectric drive layer on the second bottom electrode; and A second top electrode is on the second piezoelectric drive layer.

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