Probe assembly structure
By designing a multi-layer structure containing probe components, the problem of limited processing volume of existing probe cards is solved, and efficient processing of semiconductor grain complexity testing is achieved.
Patent Information
- Application Number
- CN202421603777.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2023-07-14
- Filing Date
- 2024-07-08
- Publication Date
- 2025-06-17
- Estimated Expiration
- 2034-07-08
AI Technical Summary
When testing semiconductor grains, existing probe cards have limited processing capacity, making it difficult to meet the complex testing needs of high-density metal pads.
A structure including a probe assembly is designed, including a multi-layer structure, an upper guide plate, a lower guide plate, a dielectric partition plate and a probe array, which extends vertically through the openings of the upper guide plate, a lower guide plate and a dielectric partition plate. The lower guide plate comprises a downward protrusion and a base, and the downward protrusion has a larger transverse extension section for increased stability.
Through this structure, the test output capability of the probe card is improved, the processing volume of complexity tests of semiconductor grains is enhanced, and the efficiency of the test equipment is improved.
Smart Images
Figure CN222994543U_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present utility model relate to a testing technology, and particularly to an operation method of a testing device and a structure including a probe assembly. Background Art
[0002] After knowing the electrical layout of the test pad array in a semiconductor die, a probe card can be constructed and used in a testing device to be able to test the semiconductor die. High-density metal pads in the semiconductor die use a probe card with a fine pitch and a high pin count. Parallel testing can be used to cope with the complexity of semiconductor-on-chip (SoC) devices on a chip, and more than one device can be probed at a time, thereby improving the test output of the testing device. The throughput of the tester is usually a limiting factor in semiconductor manufacturing capabilities. Therefore, it is desirable to improve the probe card to increase the throughput of testing using the probe card. Summary of the Utility Model
[0003] The object of the present utility model is to provide a probe assembly structure to solve at least one of the above problems.
[0004] In some embodiments, there is provided a structure including a probe assembly, including: a multi-layer structure including probe contact pads; an upper guide plate including an upper hole array therethrough; a lower guide plate including a lower hole array therethrough; a dielectric separator located between the upper guide plate and the lower guide plate and including an opening; and a probe array attached to the probe contact pads, the probe array vertically extending through the upper hole array and the lower hole array and vertically extending through the opening of the dielectric separator, wherein the lower guide plate includes a downward protrusion and a base, the downward protrusion has a first laterally extending section having a first width, the base is above the downward protrusion and has a second width greater than the first width.
[0005] According to one embodiment of the present utility model, the second width is at least 5 times the first width, and the first laterally extending section of the downward protrusion has a first length that is at least 5 times the first width.
[0006] According to one embodiment of the present utility model, the first laterally extending section of the downward protrusion extends laterally along a first horizontal direction, and the downward protrusion includes a second laterally extending section that extends laterally along a second horizontal direction perpendicular to the first horizontal direction.
[0007] According to one embodiment of the present utility model, the first lateral extension section of the downward protrusion extends laterally along a first horizontal direction, and the lower guide plate includes an additional downward protrusion that extends laterally along the first horizontal direction and is laterally spaced apart from the downward protrusion by a spacing that is at least 5 times the first width.
[0008] According to one embodiment of the present utility model, it further includes: a dielectric polymer layer located on the bottom surface of the downward protrusion and having an array of openings through which the probe array vertically extends.
[0009] According to one embodiment of the present utility model, it further includes: a probe card attached to the multilayer structure through an interconnect structure.
[0010] According to one embodiment of the present utility model, the interconnect structure includes an array of solder balls or an interposer.
[0011] According to one embodiment of the present utility model, the multilayer structure further includes a redistribution structure and a multilayer dielectric matrix that surrounds and embeds the redistribution structure.
[0012] According to one embodiment of the present utility model, the probe contact pads are connected to the redistribution structure.
[0013] According to one embodiment of the present utility model, the dielectric partition further includes a guiding post that extends through the opening of the dielectric partition. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Embodiments of the present utility model can be better understood in accordance with the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with the standard practice in this industry, the various components (features) in the drawings are not necessarily drawn to scale. In fact, the dimensions of the various components may be arbitrarily enlarged or reduced for clear illustration.
[0015] Figure 1 Schematic diagram of a test device according to an embodiment of the present utility model.
[0016] Figure 2A Vertical cross-sectional schematic diagram of an exemplary probe assembly according to an embodiment of the present utility model.
[0017] Figure 2B Along Figure 2A Horizontal cross-sectional schematic diagram of the horizontal plane B - B' of the exemplary probe assembly.
[0018] Figure 2C Along Figure 2A Horizontal cross-sectional schematic diagram of the horizontal plane C - C' of the exemplary probe assembly.
[0019] Figure 2D is a schematic horizontal cross-sectional view along the horizontal plane D-D' of an exemplary probe assembly Figure 2A .
[0020] Figure 2E is a schematic horizontal cross-sectional view along the horizontal plane E-E' of an exemplary probe assembly Figure 2A .
[0021] Figure 3A is a plan view of a wafer after forming wafer side bonding pads and test pads according to an embodiment of the present utility model.
[0022] Figure 3B is a schematic vertical cross-sectional view of the wafer along the vertical plane B-B' Figure 3A .
[0023] Figure 4A is a plan view of an assembly of a wafer and semiconductor dies according to an embodiment of the present utility model.
[0024] Figure 4B is a schematic vertical cross-sectional view of the assembly along the vertical plane B-B' Figure 4A .
[0025] Figure 4C is a plan view of another configuration of an assembly of a wafer and semiconductor dies according to an embodiment of the present utility model.
[0026] Figure 5 is a schematic vertical cross-sectional view of a part of a test device during testing a semiconductor die using test pads on a wafer according to an embodiment of the present utility model Figure 1 .
[0027] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F , Figure 6G , Figure 6H is a bottom-up plan view of various configurations of a probe assembly according to an embodiment of the present utility model.
[0028] Figure 7 is a first flowchart of general processing steps for operating a test device according to an aspect of an embodiment of the present utility model.
[0029] Figure 8 is a second flowchart of general processing steps for operating a test device according to an aspect of an embodiment of the present utility model.
[0030] The reference numerals are as follows:
[0031] 10: Probe
[0032] 20: Upper guide plate
[0033] 21: Upper hole
[0034] 29: Upper guiding opening
[0035] 30: Dielectric separator
[0036] 31: Opening
[0037] 39: Guiding opening
[0038] 60: Fixture
[0039] 62,90: Guiding post
[0040] 80: Lower guide plate
[0041] 80B: Base
[0042] 80P: Downward protrusion
[0043] 81: Lower hole
[0044] 84: Dielectric polymer layer
[0045] 89: Lower guiding opening
[0046] 92: Fixing element
[0047] 100: Plate assembly
[0048] 200: Multilayer structure
[0049] 210: Multilayer dielectric matrix
[0050] 211: Groove area
[0051] 220: Probe contact pad
[0052] 250: Rewiring structure
[0053] 290: Interconnection structure
[0054] 300: Probe card
[0055] 500: Wafer
[0056] 510: Wafer-side bonding pad
[0057] 560: Rewiring interconnection structure
[0058] 580: Test pad
[0059] 600: Semiconductor die
[0060] 610: Die-side bonding pad
[0061] 630: Welding material part
[0062] 700: Wafer transporter unit
[0063] 710,720,730,810,820,830,840: Steps
[0064] 800: Tester electronic unit
[0065] 810: Cable
[0066] 900: Wafer detector
[0067] 910: Detector frame
[0068] 912,914: Tester head support structure
[0069] 920: Tester head
[0070] 930: Performance board
[0071] 940: Contact structure
[0072] 960: Wafer chuck
[0073] 980: Unit under test
[0074] UA: Unit area
[0075] h: Height
[0076] hd1: First horizontal direction
[0077] hd2: Second horizontal direction Detailed implementation mode
[0078] It should be understood that the following disclosure provides many different embodiments or examples for implementing different components of the provided subject matter. The following describes specific examples of each component and its arrangement to simplify the description of the disclosure. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, the dimensions of the components are not limited to the scope or values of an embodiment of the present disclosure, but may depend on the processing conditions and / or required properties of the components. In addition, in the subsequent description, embodiments including the first component being formed directly in contact with the second component above or on the second component, and embodiments may also include additional components being formed between the first and second components such that the first and second components may not be in direct contact. Unless otherwise clearly stated, elements having the same reference numerals are assumed to be the same or similar and are assumed to have the same material composition and the same function.
[0079] Furthermore, for the convenience of description, the attached
[0080] The relationship between one element or component and another element or components can be described using spatial relative terms, such as "under", "below", "lower", "above", "upper", and similar terms. In addition to the orientation shown in the drawings, spatial relative terms also cover different orientations during the use or operation of the device. The device can also be positioned otherwise (e.g., rotated 90 degrees or in other orientations), and the descriptions of the spatial relative terms used can be interpreted accordingly. Unless otherwise clearly stated, elements with the same reference signs represent the same elements and are assumed to have the same material composition and the same thickness range.
[0081] The test equipment can include a test head, a probe card attached to the test head, and a probe assembly attached to the probe card. The probe assembly can include probes that can be attached to probe contact pads in a multi-layer structure including a redistribution structure. The probes can be spatially and structurally stabilized by providing guide plates. The guide plates can include an upper guide plate close to the multi-layer structure and a lower guide plate away from the multi-layer structure. A dielectric spacer plate can be used to provide a vertical spacing between the upper guide plate and the lower guide plate. During the assembly of the upper guide plate, the lower guide plate, and the dielectric spacer plate, the probes can be inserted through an array of holes in the guide plates and through an opening in the dielectric spacer plate. An automated probe insertion process is typically used to automatically insert the probes through the guide plates and the dielectric spacer plate. The throughput of the automated probe insertion process is generally proportional to the thickness of the dielectric spacer plate. In other words, the thicker the dielectric spacer plate, the longer the time required for the automated probe insertion process to successfully insert the probe array through the assembly of the upper guide plate, the lower guide plate, and the dielectric spacer plate.
[0082] The minimum vertical distance between the upper guide plate and the lower guide plate can be used to provide sufficient structural stability in the probe assembly. The minimum vertical distance is generally in the range of 3 mm to 6 mm, such as about 4 mm. According to one aspect of the embodiments of the present invention, multiple dielectric spacer plates can be used instead of a single dielectric spacer plate. During the automated probe insertion process, one of the dielectric spacer plates can be positioned between the upper guide plate and the lower guide plate. After the automated probe insertion process, at least another dielectric spacer plate can be inserted from the side to provide sufficient vertical spacing between the upper guide plate and the lower guide plate. Since the thickness of the dielectric spacer plate through which the probes are inserted is less than the final vertical spacing between the upper guide plate and the lower guide plate, the time taken for the automated probe insertion process is less due to the reduction in the thickness of the dielectric spacer plate present during probe insertion. At the same time, the final vertical spacing between the upper guide plate and the lower guide plate can be maintained at the same level, and thus, the performance and structural stability of the probe assembly are not affected. Aspects of the embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0083] Please refer toFigure 1 , an embodiment testing device for one aspect of the present disclosure is provided. The embodiment testing device may include a tester electronic unit 800 (including at least one computer and peripheral devices), a wafer prober 900 communicating with the tester electronic unit 800 (e.g., via signal and cable 810), and an optional wafer transfer unit 700 configured to load and unload a unit under testing (UUT) 980 on the wafer prober 900. The wafer prober 900 may include a wafer chuck 960 (configured to hold the unit under test 980 above), a prober frame 910 (containing a stage drive unit configured to laterally drive the wafer chuck 960), a tester head 920 located above the wafer chuck 960, and tester head support structures 912, 914 (configured to structurally support and move the tester head 920).
[0084] A performance board 930 may be attached to the bottom of the tester head 920, and a probe card 300 may be attached to the bottom of the performance board 930 using a suitable array of contact structures 940 (e.g., a spring-type contact pin array). The probe card 300 may include a printed circuit board (PCB) containing a plastic substrate and a printed circuit above the plastic substrate. A stiffener (not shown) may be attached to the back side of the probe card 300 to reduce structural deformation of the probe card 300 caused by thermal stress and / or mechanical stress during use. The probe card 300 may also be referred to as a main board.
[0085] A probe assembly (10, 100, 200, 60) may be attached to the bottom of the probe card 300. The probe assembly (10, 100, 200, 60) includes a multi-layer structure 200, a board assembly 100, and an array of probes 10. The board assembly 100 includes an upper guide plate, a lower guide plate, and a plurality of dielectric partitions. The probe assembly (10, 100, 200, 60) may include various elements of the embodiments of the present invention. Specifically, the board assembly 100 may be assembled in a manner to accelerate the automatic probe insertion process according to an embodiment of the present invention. In addition, according to an embodiment of the present invention, the board assembly 100 may have structural features to accelerate the automatic probe insertion process.
[0086] Please refer to Figures 2A to 2E , showing, according to an embodiment of the present invention, the area around the probe assembly (10, 100, 200, 60), which can be incorporated into Figure 1In the embodiment test device. The multi-layer structure 200 may include an array of probe contact pads 220 having the same two-dimensional periodicity as the array of probes 10. The array of probes 10 may be attached to the array of probe contact pads 220 using methods known in the art. For example, the array of probes 10 may be attached to the array of probe contact pads 220 by solder material portions, metal-to-metal bonding, conductive paste portions, and / or epoxy resin.
[0087] The probes 10 are thin and sharp and may be made of a durable conductive material such as tungsten or gold. The probes 10 may be arranged in a pattern that matches the pattern of test pads on the wafer to be used subsequently. The probes 10 physically contact the test pads on the wafer and are conductive, such that electrical signals can be transmitted into or out of the test pads on the wafer for subsequent testing.
[0088] The total number of probes 10 in the array of probes 10 is typically in the range of 10 to 100,000, such as 100 to 10,000, but fewer and more probes 10 may also be used. The pitch of the probes 10 (i.e., the center-to-center distance between adjacent pairs of probes 10) may be the same as the pitch of the test access points (such as test pads) on the unit under test (UUT). For example, in the case where the unit under test includes components such as a wafer and semiconductor dies, and the test access points include test pads located between adjacent pairs of semiconductor dies, the pitch of the probes 10 may be the same as the pitch of the subset of test pads that will be used as access points.
[0089] The access points on the wafer may be electrically connected to a corresponding one of the semiconductor dies through an interconnect structure (such as a redistribution interconnect structure) in the wafer, and the semiconductor die electrically connected to the access points contacted by the array of probes 10 can be tested for functionality. In an exemplary display, the pitch of the probes 10 may be in the range from 10 micrometers to 100 micrometers, but smaller and larger pitches may also be used. Although embodiments in which the probes 10 are arranged in a 3×10 rectangular array are described, embodiments of array configurations in which the probes 10 are arranged in different sizes and / or non-rectangular arrays are explicitly contemplated herein.
[0090] The multi-layer structure 200 may include a multi-layer dielectric substrate 210 and a redistribution structure 250 embedded in the multi-layer dielectric substrate 210. The multi-layer dielectric substrate 210 may include a ceramic layer or an organic layer. In an embodiment where the multi-layer dielectric substrate 210 includes a ceramic layer, the multi-layer structure 200 may be referred to as a multi-layer ceramic structure. In an embodiment where the multi-layer dielectric substrate 210 includes an organic layer, the multi-layer structure 200 may be referred to as a multi-layer organic structure. A subset of the redistribution structure 250 may include an array of contact structures on a side facing the probe card 300. The array of contact structures may have a pitch greater than the pitch of the probes 10. The multi-layer structure 200 may be attached to the probe card 300 through an array of interconnect structures 290, which may include an array of solder balls or may include an interposer that includes an array of vertical interconnect structures.
[0091] In one embodiment, an array of probes 10 may be attached to an array of probe contact pads 220 in the recessed area 211, where the horizontal surface of the multi-layer structure 200 is recessed (i.e., recessed upward) with respect to the horizontal frame surface of the multi-layer structure 200 that laterally surrounds the recessed area 211, towards the probe card 300.
[0092] The board assembly 100 may include a vertical stack of an upper guide plate 20, a lower guide plate 80, and a dielectric separator 30 located between the upper guide plate 20 and the lower guide plate 80. The upper guide plate 20 may include an upper array of upper holes 21 through the upper guide plate 20, the lower guide plate 80 may include a lower array of lower holes 81 through the lower guide plate 80, and the dielectric separator 30 includes corresponding openings 31 through the dielectric separator 30. The upper guide plate 20 is closer to the multi-layer structure 200 than the lower guide plate 80. In one embodiment, the upper guide plate 20 may contact the bottom surface (e.g., the horizontal frame surface of the multi-layer structure 200). The lower guide plate 80 may be vertically spaced from the upper guide plate 20 by a vertical stack of a plurality of dielectric separators 30.
[0093] An array of probes 10 may be attached to the probe contact pads 220, may vertically extend through the array of upper holes 21 and the array of lower holes 81, and may vertically extend through the openings 31 through the vertical stack of a plurality of dielectric separators 30. The multi-layer structure 200 may include a redistribution structure 250 and a multi-layer dielectric substrate 210 that surrounds and embeds the redistribution structure 250. The probe contact pads 220 may be connected to a corresponding one of the redistribution structures 250.
[0094] In one embodiment, the dielectric separator 30 may include at least two guiding openings 39 therethrough, and the probe assembly (10, 100, 200, 60) includes at least two guiding posts 90 that extend vertically through the guiding openings 39 in the dielectric separator 30. In one embodiment, the upper guide plate 20 includes at least two upper guiding openings 29 through the upper guide plate 20, and the lower guide plate 80 includes at least two lower guiding openings 89 through the lower guide plate 80. In one embodiment, each of the at least two guiding posts 90 may extend vertically through a corresponding one of the upper guiding openings 29 and through a corresponding one of the lower guiding openings 89. In one embodiment, each of the at least two guiding posts 90 may extend vertically through a corresponding one of the upper guiding openings 29 and through a corresponding one of the lower guiding openings 89, and through a corresponding guiding opening 39 in a dielectric separator 30 selected from the plurality of dielectric separators 30.
[0095] In one embodiment, each of the at least two guiding posts 90 may include a corresponding fixing element at the top end (i.e., the end close to the multilayer structure 200). For example, a fixing element 92 (such as the thread of a bolt) may be used to mechanically fix the top end of each of the at least two guiding posts 90 to and / or within the multilayer structure 200. In this embodiment, the multilayer structure 200 may include at least two matching fixing elements configured to match the fixing elements 92 of the at least two guiding posts 90. For example, the multilayer structure 200 may include two or more threaded holes configured to accommodate the threads of the bolts and form a stable mechanical support for the threads of the bolts (which may form the corresponding guiding posts 90). In the illustrated example, the at least two guiding posts 90 may include at least two threaded bolts or at least two screws.
[0096] In one embodiment, the dielectric separator 30 may include an outer perimeter and an inner perimeter that is laterally surrounded and spaced apart from the outer perimeter. The dielectric separator 30 laterally surrounds each probe 10 selected from the array of probes 10. In one embodiment, the dielectric separator 30 may include at least one opening, and each perimeter of the opening is the inner perimeter of the dielectric separator 30. In one embodiment, at least one opening of the dielectric separator 30 may have a rectangular, rounded rectangular, L-shaped region, U-shaped region, a plurality of elongated strips parallel to each other, or a frame shape. Generally, at least one opening of the dielectric separator 30 may be shaped to enclose all regions of the array of probes 10 and depends on the overall arrangement of the array of probes 10. In one embodiment, the outer perimeter of the dielectric separator 30 may have a rectangular or rounded rectangular shape.
[0097] The thickness of the upper guide plate 20 can be in the range of 1 mm to 4 mm, for example, in the range of 1.5 mm to 2.5 mm, but smaller and larger thicknesses can also be used. The thickness of the lower guide plate 80 can be in the range of 1 mm to 4 mm, for example, in the range of 1.5 mm to 2.5 mm, but smaller and larger thicknesses can also be used. The thickness of the dielectric separator 30 can be in the range of 1 mm to 6 mm, for example, in the range of 3 mm to 5 mm, but smaller and larger total thicknesses can also be used. As described above, the thicknesses of the upper guide plate 20, the lower guide plate 80, and the dielectric separator 30 provide stability for the probe card and the array of probes 10, while simplifying and accelerating the automatic probe insertion process.
[0098] Generally, the probe assemblies (10, 100, 200, 60) of the embodiments of the present invention may include a multi-layer structure 200 (including probe contact pads 220), an upper guide plate 20 (including an array of through upper holes 21), a lower guide hole 80 (including an array of through lower holes 81), a dielectric separator 30 (including an opening 31) located between the upper guide plate 20 and the lower guide plate 80, and an array of probes 10 attached to the probe contact pads 220 (vertically passing through the array of upper holes 21, the array of lower holes 81, and the opening 31 of the dielectric separator 30). According to one aspect of the embodiments of the present invention, the lower guide hole 80 includes a downward protrusion 80P and a base 80B. The downward protrusion 80P has a first laterally extending section having a first width. The base 80B is above the downward protrusion 80P and has a second width greater than the first width. The first width can be in the range of 50 μm to 2 mm, for example, 100 μm to 1 mm, and / or 200 μm to 500 μm, but smaller and larger sizes can also be used. In one embodiment, the second width is at least 5 times the first width. The height h of the downward protrusion 80P can be the same as or significantly the same as the thickness of the semiconductor die subsequently attached to the wafer, and can be greater than 150 μm and / or 200 μm and / or greater than 300 μm and / or greater than 500 μm and / or greater than 700 μm and / or greater than 1 mm and / or greater than 2 mm and / or greater than 3 mm and / or greater than 5 mm.
[0099] In one embodiment, the downward protrusion 80P may be elongated in a horizontal direction perpendicular to the width direction of the downward protrusion 80P. In one embodiment, the downward protrusion 80P may be elongated in a first horizontal direction hd1 and may have a first width in a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. In one embodiment, the downward protrusion 80P may include a first laterally extending section that has a first length in the first horizontal direction hd1. The first length may be at least 5 times the first width. In one embodiment, the downward protrusion 80P of the lower guide plate 80 includes a first laterally extending section that is configured to be located between an adjacent pair of semiconductor dies such that the first laterally extending section is below a horizontal plane that includes the top surface of the semiconductor dies.
[0100] The base 80B of the lower guide plate 80 may be wider than the gap between an adjacent pair of semiconductor dies to be tested. During testing, the base 80B of the lower guide plate 80 may be configured to be above an adjacent pair of semiconductor dies. The lateral extent of the base 80B may be 5 times greater, 10 times greater, and / or 20 times greater, and / or 50 times greater, and / or 100 times greater than the first width of the downward protrusion 80P. Generally, the distance that the downward protrusion 80P of the lower guide plate 80 extends laterally in the first horizontal direction hd1 is greater than the width of the gap between an adjacent pair of semiconductor dies to be subsequently used during testing.
[0101] In one embodiment, a dielectric polymer layer 84 may be located on the bottom surface of the downward protrusion 80P. The dielectric polymer layer 84 may have an array of openings through which an array of probes 10 vertically extends. In one embodiment, the dielectric polymer layer 84 may have the same horizontal cross-sectional shape as the downward protrusion 80P of the lower guide plate 80. In one embodiment, the dielectric polymer layer 84 may have a lateral dimension that is less than the gap between an adjacent pair of semiconductor dies to be subsequently used during testing.
[0102] Generally, the downward protrusion 80P of the lower guide plate 80 may have a horizontal cross-sectional shape that does not overlap any semiconductor die covering the wafer during testing of the bonding assembly for the wafer and semiconductor dies. In one embodiment, the downward protrusion 80P of the lower guide plate 80 may be configured to fit a single gap between a first semiconductor die and a second semiconductor die that is an adjacent die to the first semiconductor die, or may be configured to fit multiple gaps that may or may not be interconnected to each other, and / or may laterally extend in the same horizontal direction above the bonding assembly. Further, although embodiments are described herein where the lower guide plate 80 includes a single downward protrusion 80P, embodiments where the lower guide plate 80 includes multiple downward protrusions 80P are expressly contemplated herein.
[0103] Optionally, the probe assemblies (10, 100, 200, 60) of the present disclosure may include a clamp 60 (with guide posts 62) that laterally surrounds the multi-layer structure 200, the upper guide plate 20, and the dielectric separator 30. If present, the clamp 60 is configured to be mounted on the bottom surface of the probe card 300. In one embodiment, the dielectric separator 30 may have a larger lateral extent than the upper guide plate 20 and the lower guide plate 80, and may have a recessed inner bottom surface that is configured to contact a laterally protruding peripheral portion of the top surface of the dielectric separator 30 that protrudes outward from the sidewall of the upper guide plate 20. The dielectric separator 30 may be fixed to the clamp 60 using fixing elements 92, which may include mechanical elements such as bolts, nuts, screws, clips, rivets, pins, etc. If present, the clamp 60 may be used to fix and position the board assembly during testing. For example, the clamp 60 may be used to stabilize the position of the board assembly 100 and provide consistent contact with the test device. In some embodiments, the clamp may be used to control the pressure applied by the array of probes 10 to the device under test to provide a consistent and repeatable test of the device under test.
[0104] Please refer to Figure 3A and Figure 3B , which shows a wafer 500 on which wafer-side bonding pads 510 and test pads 580 are formed. In one embodiment, the wafer 500 includes a substrate and an array of interposer layers formed on the substrate. The substrate can be any suitable substrate on which the array of interposer layers can be formed. In one embodiment, each interposer layer may include a redistribution interconnect structure 560 embedded in a redistribution dielectric layer. The wafer-side bonding pads 510 and test pads 580 may be formed, for example, by depositing and patterning at least one conductive material (such as copper) above the redistribution interconnect structure 560. In this embodiment, the wafer-side bonding pads 510 and test pads 580 may have the same material composition and the same thickness.
[0105] In one embodiment, a pattern including a set of wafer-side bonding pads 510 and a set of test pads 580 may be repeated in a periodic or non-periodic two-dimensional array above the wafer 500. The area of this pattern herein is referred to as the unit area UA. Each set of wafer-side bonding pads 510 may be used for subsequent bonding of semiconductor dies. In each unit area UA, a set of redistribution interconnect structures 560 may provide electrical connection between a set of wafer-side bonding pads 510 and a set of test pads 580.
[0106] Please refer to Figure 4A and Figure 4B, the assembly of the wafer 500 and the semiconductor die 600 can be formed by attaching the semiconductor die 600 to the wafer 500. The embodiments shown in FIGS. 4A and 4B correspond to the case where the interposer arrangement in the wafer 500 is a periodic two-dimensional array having a first periodicity along a first horizontal direction of the wafer 500 and a second periodicity along a second horizontal direction of the wafer 500. In this embodiment, the attached semiconductor dies 600 can be arranged as a periodic two-dimensional array. Generally, the arrangement of the semiconductor dies 600 above the wafer 500 may or may not have two-dimensional periodicity. Figure 4C An embodiment is shown in which the interposer in the wafer 500 and the semiconductor die 600 attached to the wafer 500 are not arranged as a periodic two-dimensional array.
[0107] Please refer jointly to Figures 4A to 4C , each semiconductor die 600 can include die-side bonding pads 610 that are arranged as a mirror image pattern of a pattern of a set of wafer-side bonding pads 510. An array of solder material portions 630 can be formed on the wafer-side bonding pads 510 or on the die-side bonding pads 610, and solder bonding can be performed to attach each semiconductor die 600 to the wafer 500.
[0108] Generally, an assembly of the wafer 500 and the semiconductor die 600 can be formed, where the semiconductor die 600 is attached to the wafer 500. The semiconductor die 600 can be attached to the wafer 500 by solder bonding using the solder material portions 630, or can be attached to the wafer 500 by metal-to-metal bonding, where the wafer-side bonding pads 510 are directly bonded to the die-side bonding pads 610. The wafer 500 includes test pads 580 located below the gaps between the semiconductor dies 600. Furthermore, the wafer 500 includes an interconnect structure, such as a redistribution interconnect structure 560, that provides an electrical conduction path between the test pads 580 and the semiconductor dies 600. Generally, a set of redistribution interconnect structures 560 can be located in a corresponding interposer and can provide an electrical conduction path between an upper set of wafer-side bonding pads 510 and an adjacent set of test pads 580.
[0109] In one embodiment, the wafer 500 includes a plurality of interposers. The interposer includes an interconnect structure that provides an electrical conduction path between a corresponding one of the test pads 580 and the semiconductor die 600. In one embodiment, the interconnect structure includes redistribution interconnect structures 560 buried in a redistribution dielectric layer located in the upper portion of the wafer 500. In one embodiment, the wafer 500 includes wafer-side bonding pads 510. The semiconductor die 600 includes die-side bonding pads 610 that are bonded to a corresponding subset of the wafer-side bonding pads 510. The wafer 500 includes test pads 580 located below the gaps between adjacent pairs of semiconductor dies 600.
[0110] In one embodiment, semiconductor die 600 includes die - side bonding pads 610, which are bonded to a corresponding subset of wafer - side bonding pads 510 via a corresponding set of solder material portions 630. In one embodiment, wafer - side bonding pads 510 may have the same material composition as test pads 580 and may have the same thickness as test pads 580. In one embodiment, wafer - side bonding pads 510 and test pads 580 may have corresponding upper portions that comprise and / or are mainly composed of copper. After bonding semiconductor die 600 to wafer 500, the redistribution interconnect structure 560 may provide an electrical conduction path between the devices in semiconductor die 600 and test pads 580. The components of wafer 500 and semiconductor die 600 may be used as Figure 1 the unit - under - test (UUT) 980 shown.
[0111] Figure 5 During testing of the components of wafer 500 and semiconductor die 600 as the unit - under - test (UUT) 980, Figure 1 a vertical cross - sectional schematic of a part of the test equipment.
[0112] As described above, lower guide plate 80 includes a downward protrusion 80P having a first laterally extending section. The first laterally extending section may have a first width that is less than the lateral separation distance between adjacent pairs of semiconductor die 600. For example, if the semiconductor devices in semiconductor die 600 are to be tested after semiconductor die 600 is attached to wafer 500, the first laterally extending section of the downward protrusion 80P of lower guide plate 80 may be located in the gap between two adjacent semiconductor die 600 (between a first and a second semiconductor die). When the plate assembly 100 is lowered, the first laterally extending section of the downward protrusion 80P of lower guide plate 80 may be positioned below the horizontal plane containing the top surface of semiconductor die 600 and remain in this position during testing of the functionality of semiconductor die 600.
[0113] Towards the wafer through the lowering plate assembly 100, an array of probes 10 (i.e., manipulation and positioning) can be controlled to contact a subset of test pads 580 located between a first semiconductor die and a second semiconductor die selected from semiconductor dies 600. In some embodiments, the step of controlling the array of probes 10 may include moving the array of probes 10 relative to a fixed wafer chuck 960, which is configured to hold the unit under test 980 fixed thereon. In other embodiments, the step of controlling the array of probes 10 may include moving the wafer chuck 960, which is configured to hold the unit under test 980 thereon relative to the fixed array of probes 10. The function of the first semiconductor die (i.e., semiconductor die 600) is to provide electrical signals to the first semiconductor die and to devices in the first semiconductor die through a subset of test pads 580, through a subset of interconnect structures (such as the redistribution interconnect structure 560) in the underlying interposer, through an array of wafer-side bonding pads 510, through an array of solder material portions 630, and through an array of die-side bonding pads 610 of the first semiconductor die. Generally, the function of the first semiconductor die can be tested by causing contact between the array of probes 10 and a subset of test pads 580 close to the first semiconductor die and by providing electrical signals to the devices in the first semiconductor die.
[0114] As described above, the lower guide plate 80 further includes a base 80B above the downward protrusion 80P and having a larger lateral extent than the downward protrusion 80P. Generally, during testing of the function of the first semiconductor die, the base 80B of the lower guide plate 80 can cover the first and second semiconductor dies (i.e., semiconductor dies 600), and can selectively cover additional semiconductor dies 600.
[0115] Although embodiments are described herein using an array of probes 10 including a 3x10 rectangular array, it should be noted that the selection of the 3x10 rectangular array is arbitrary, and the array of probes 10 can be arranged in any other array configuration.
[0116] Figures 6A to 6H For an embodiment according to the present invention, a bottom-up plan view of various configurations of the probe assembly (10, 100, 200, 60). For example, the array of probes 10 may include a rectangular array (as Figure 6A shown) having dimensions different from 3x10, a linear array including a single row of probes 10 (as Figure 6B shown), an L-shaped array including at least one row of probes 10 and at least one column of probes 10 adjacent at the ends (as Figure 6C and Figure 6D shown), a +-shaped array (referred to as a plus shape, cross shape) including at least one row of probes 10 and at least one column of probes 10 intersecting each other (as Figure 6Ea U-shaped array (as shown) that includes two rows of probe sets 10 that are parallel to each other and laterally spaced apart, and further includes at least one column of probes 10 that connect the two rows of probe sets 10 Figure 6F two or more rows of probes that are laterally spaced apart from each other (as shown Figure 6G ), or a frame array (as shown Figure 6H ). The various geometric features of the probe 10 and the downward protrusion 80P shown in Figures 6A to 6H are not limited or exhaustive in any way, and any configuration and shape of the downward protrusion 80P can be used, as long as during the test steps described with reference to Figure 5 , the downward protrusion 80P is adapted to fit into the corresponding gap between the corresponding adjacent pairs of semiconductor dies 600 below the horizontal plane that includes the top surface of the semiconductor die 600.
[0117] In one embodiment, the lower guide plate 80 includes at least one downward protrusion 80P, and the downward protrusion 80P includes a corresponding first laterally extending section that extends laterally along a first horizontal direction hd1 and has a corresponding first width along a second horizontal direction hd2. Each first width can be less than the gap between the adjacent pairs of semiconductor dies 600 and can be in the range of 50 μm to 2 mm, such as in the range of 100 μm to 1 mm and / or 200 μm to 500 μm, but smaller and larger sizes can also be used. This at least one downward protrusion 80P can include a single downward protrusion 80P as shown in Figures 6A to 6F and Figure 6H , or can include multiple downward protrusions 80P as shown in Figure 6G .
[0118] In one embodiment, the downward protrusion 80P may or may not include a second laterally extending section that extends laterally along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. For example, Figures 6C to 6F and Figure 6H show embodiments of the downward protrusion 80P that include a second laterally extending section. In this embodiment, during the testing of the function of the first semiconductor die (i.e., the semiconductor die 600), each second laterally extending section can be located between the first semiconductor die and the third semiconductor die (i.e., the semiconductor die 600).
[0119] In one embodiment, the first laterally extending section of the downward protrusion 80P extends laterally along the first horizontal direction hd1, and the lower guide plate 80 includes an additional downward protrusion 80P that extends laterally along the first horizontal direction hd1, as shown in Figure 6G . In this embodiment, during the testing of the function of the first semiconductor die (i.e., the semiconductor die 600), the additional downward protrusion 80P can be located between the first semiconductor die and the third semiconductor die (i.e., the semiconductor die 600).
[0120] Generally, an array of various types of probes 10 can be used as long as the pattern of the probes 10 in the array can fit into the gap region between adjacent pairs of semiconductor dies in the unit under test (UUT) of the above-described assembly including the wafer 500 and the semiconductor die 600.
[0121] Please refer to Figure 7 , Figure 7 FIG. 7 is a first flow chart of general processing steps for operating a test device according to an aspect of an embodiment of the present invention.
[0122] Please refer to step 710 and Figure 1 , Figures 2A to 2E and Figures 6A to 6G to provide a test device including a probe assembly (10, 100, 200, 60). The probe assembly (10, 100, 200, 60) includes: a multi-layer structure 200 (including probe contact pads 220), an upper guide plate 20 (including an array of upper holes 21 therethrough), a lower guide plate 80 (including an array of lower holes 81 therethrough), a dielectric separator 30 (located between the upper guide plate 20 and the lower guide plate 80 and including an opening 31), and an array of probes 10 attached to the probe contact pads 220 (vertically extending through the array of upper holes 21 and the array of lower holes 81 and vertically extending through the opening 31 of the dielectric separator 30).
[0123] Please refer to step 720 and Figure 3A , Figure 3B and Figures 4A to 4C to provide an assembly of a wafer 500 and semiconductor dies 600, wherein the semiconductor dies 600 are attached to the wafer 500. The wafer 500 includes test pads 580 below the gaps between the semiconductor dies 600 and the interconnect structure, and the interconnect structure provides an electrical conduction path between a corresponding one of the test pads 580 and the semiconductor dies 600.
[0124] Please refer to step 730 and Figure 5 to test the functionality of a first semiconductor die selected from the semiconductor dies 600 by causing contact between the array of probes 10 and a subset of the test pads 580 and by providing an electrical signal to a device in the first semiconductor die.
[0125] In one embodiment, the lower guide plate 80 includes a downward protrusion 80P having a first laterally extending section that, during testing of the functionality of the first semiconductor die, is positioned within a gap between the first semiconductor die and a second semiconductor die below the top surface of the first semiconductor die. In one embodiment, the lower guide plate 80 further includes a base that, during testing of the functionality of the first semiconductor die, covers the first semiconductor die and the second semiconductor die. In one embodiment, the downward protrusion 80P laterally extends a distance greater than the width of the gap in a second horizontal direction hd2.
[0126] In one embodiment, the test apparatus includes a dielectric polymer layer 84 positioned on the bottom surface of the downward protrusion 80P and having an array of openings, and an array of probes 10 vertically extending through the array of openings of the dielectric polymer layer 84. In one embodiment, the dielectric polymer layer 84 has a width less than the lateral dimension of the gap measured between the sidewalls of the first semiconductor die exposed to the gap and the sidewalls of an additional semiconductor die exposed to the gap.
[0127] In one embodiment, the first laterally extending section of the downward protrusion 80P laterally extends in a first horizontal direction hd1, and the downward protrusion 80P includes a second laterally extending section that laterally extends in a second horizontal direction hd2 perpendicular to the first horizontal direction hd1, and during testing of the functionality of the first semiconductor die, the second laterally extending section is positioned between the first semiconductor die and a third semiconductor die.
[0128] In one embodiment, the first laterally extending section of the downward protrusion 80P laterally extends in a first horizontal direction hd1; the lower guide plate 80 includes an additional downward protrusion 80P that laterally extends in the first horizontal direction hd1, and during testing of the functionality of the first semiconductor die, the additional downward protrusion 80P is positioned between the first semiconductor die and a third semiconductor die.
[0129] In one embodiment, the wafer 500 includes wafer-side bonding pads 510, and the semiconductor die 600 includes die-side bonding pads 610 bonded to a corresponding subset of the wafer-side bonding pads 510. In one embodiment, the wafer-side bonding pads 510 have the same material composition as the test pads 580 and have the same thickness as the test pads 580. In one embodiment, the wafer 500 includes a plurality of interposer layers, and the interconnect structure includes a redistribution interconnect structure 560 embedded in a redistribution dielectric layer located within the wafer 500.
[0130] Please refer to Figure 8 , Figure 8 which is a second flowchart of the general processing steps for operating a test apparatus according to one aspect of an embodiment of the present invention.
[0131] Please refer to step 810 and Figure 1 、 Figures 2A to 2E and Figures 6A to 6G to provide a test apparatus including a probe assembly (10, 100, 200, 60). The probe assembly (10, 100, 200, 60) includes: a multi-layer structure 200 (including probe contact pads 220), an upper guide plate 20, a lower guide plate 80, a dielectric separator 30 (located between the upper guide plate 20 and the lower guide plate 80 and including an opening 31), and an array of probes 10 attached to the probe contact pads 220 (vertically extending through the upper guide plate 20, the lower guide plate 80, and the dielectric separator 30).
[0132] Please refer to step 820 and Figure 3A 、 Figure 3B and Figures 4A to 4C to provide an assembly of a wafer 500 and semiconductor dies 600, wherein the semiconductor die 600 is attached to the wafer 500. The wafer 500 includes test pads 580 located below a gap between the semiconductor die 600 and an interconnect structure, and the interconnect structure provides an electrical conduction path between a corresponding one of the test pads 580 and the semiconductor die 600.
[0133] Please refer to step 830 and Figure 5 to enable the array of probes 10 to contact a subset of the test pads 580 located between a first semiconductor die and a second semiconductor die selected from the semiconductor dies 600.
[0134] Please refer to step 840 and Figure 5 to test the functionality of the first semiconductor die by providing an electrical signal to the first semiconductor die through a subset of the test pads 580 and a subset of the interconnect structure and to a device in the first semiconductor die.
[0135] In one embodiment, the lower guide plate 80 includes a downward protrusion 80P having a first laterally extending section that, during testing of the functionality of the first semiconductor die, is located in a gap between the first semiconductor die and the second semiconductor die below the top surface of the first semiconductor die. In one embodiment, the lower guide plate 80 further includes a base that, during testing of the functionality of the first semiconductor die, covers the first semiconductor die and the second semiconductor die.
[0136] In one embodiment, the wafer 500 includes wafer-side bonding pads 510, and the semiconductor die 600 includes die-side bonding pads 610 bonded to corresponding subsets of the wafer-side bonding pads 510 through corresponding subsets of solder material portions 630. In one embodiment, the wafer 500 includes a plurality of interposers, and the interconnect structure includes a redistribution interconnect structure 560 embedded in a redistribution dielectric layer located in the wafer 500 and including an organic polymer.
[0137] Please refer to Figures 1 to 8 , various embodiments of the present invention can be used to provide a test device, wherein a probe 10 for contacting a test pad 580 is located between adjacent pairs of semiconductor dies 600, and the probe 10 is laterally protected by an adjacent structure, which is a downward protrusion 80P of a lower guide plate 80. The test device herein can be used to test the functions of semiconductor dies 600 after the semiconductor dies 600 are attached to a wafer 500, and the wafer 500 can include, for example, an interposer layer that includes a redistribution interconnect structure 560 buried in a redistribution dielectric layer. The test device herein provides enhanced probe alignment for contacting and testing using test pads 580 disposed between adjacent pairs of semiconductor dies 600. If the downward protrusion 80P is used in the lower guide plate 80, the test pad 580 can have a smaller size. Generally, the height h of each downward protrusion 80P can be selected such that the base 80B of the lower guide plate 80 does not contact any semiconductor die 600 during testing. Therefore, during testing using the test device herein, the semiconductor dies 600 and the probes 10 in the unit under test 980 can be protected from physical damage.
[0138] Some embodiments of the present invention provide a method of operating a test device, including: providing a test device including a probe assembly, wherein the probe assembly includes: a multi-layer structure including probe contact pads; an upper guide plate including an upper hole array therethrough; a lower guide plate including a lower hole array therethrough; a dielectric separator located between the upper guide plate and the lower guide plate and including an opening; and a probe array attached to the probe contact pads, the probe array extending vertically through the upper hole array and the lower hole array and vertically through the opening of the dielectric separator; providing a wafer and a component of a plurality of semiconductor dies, wherein the plurality of semiconductor dies are attached to the wafer, and the wafer includes a plurality of test pads below a gap between the plurality of semiconductor dies and an interconnect structure, and the interconnect structure provides a conductive path between a corresponding one of the plurality of test pads and one of the plurality of semiconductor dies; and testing the function of a first semiconductor die among the plurality of semiconductor dies by causing contact between the probe array and a subset of the plurality of test pads and by providing an electrical signal to a device in the first semiconductor die.
[0139] In some other embodiments, the lower guide plate includes a downward protrusion having a section that extends laterally in a first horizontal direction, and during testing of the function of the first semiconductor die, the section is positioned in a gap between the first semiconductor die and a second semiconductor die below a horizontal plane including the top surface of the first semiconductor die.
[0140] In some other embodiments, the lower guide plate further includes a base that covers the first semiconductor die and the second semiconductor die during testing of the function of the first semiconductor die.
[0141] In some other embodiments, the distance that the downward protrusion extends laterally along the second horizontal direction is greater than the width of the gap.
[0142] In some other embodiments, the test device includes a dielectric polymer layer located on the bottom surface of the downward protrusion and having an array of openings through which the probe array extends vertically.
[0143] In some other embodiments, the dielectric polymer layer has a lateral dimension smaller than the gap, and the lateral dimension of the gap is measured between the sidewalls of the first semiconductor die exposed to the gap and the sidewalls of the additional semiconductor die exposed to the gap.
[0144] In some other embodiments, the downward protrusion includes a second laterally extending section that extends laterally along a second horizontal direction perpendicular to the first horizontal direction, and during testing of the functionality of the first semiconductor die, the second laterally extending section is positioned between the first semiconductor die and the third semiconductor die.
[0145] In some other embodiments, the lower guide plate includes an additional downward protrusion that extends laterally along the first horizontal direction, and during testing of the functionality of the first semiconductor die, the additional downward protrusion is positioned between the first semiconductor die and the third semiconductor die.
[0146] In some other embodiments, the wafer includes a plurality of wafer-side bonding pads, and the plurality of semiconductor dies include a plurality of die-side bonding pads bonded to a corresponding subset of the plurality of wafer-side bonding pads.
[0147] In some other embodiments, the plurality of wafer-side bonding pads have the same material composition as the plurality of test pads and have the same thickness as the plurality of test pads.
[0148] In some other embodiments, the wafer includes a plurality of interposer layers, and the interconnect structure includes a redistribution interconnect structure embedded in a redistribution dielectric layer located in the wafer.
[0149] Some embodiments of the present utility model provide an operation method for a test device, including: providing a test device including a probe assembly, where the probe assembly includes: a multi-layer structure including probe contact pads; an upper guide plate; a lower guide plate; a dielectric partition located between the upper guide plate and the lower guide plate and including an opening; and a probe array attached to the probe contact pads, the probe array vertically extending through the upper guide plate, the lower guide plate, and the dielectric partition; providing a wafer and a component of a plurality of semiconductor dies, where the plurality of semiconductor dies are attached to the wafer, and the wafer includes a plurality of test pads below a gap between the plurality of semiconductor dies and an interconnect structure, and the interconnect structure provides a conduction path between the plurality of test pads and a corresponding one of the plurality of semiconductor dies; manipulating the probe array to contact a subset of the plurality of test pads located between a first semiconductor die and a second semiconductor die selected from the plurality of semiconductor dies; and testing the function of the first semiconductor die by providing an electrical signal to the first semiconductor die through the subset of the plurality of test pads and a subset of the interconnect structure and into the first semiconductor die.
[0150] In some other embodiments, the lower guide plate includes a downward protrusion having a first laterally extending section, and during testing the function of the first semiconductor die, the first laterally extending section is located in a gap between the first semiconductor die and the second semiconductor die below a horizontal plane including the top surface of the first semiconductor die.
[0151] In some other embodiments, the lower guide plate further includes a base, and during testing the function of the first semiconductor die, the base covers the first semiconductor die and the second semiconductor die.
[0152] In some other embodiments, the wafer includes a plurality of wafer-side bonding pads, and the plurality of semiconductor dies include a plurality of die-side bonding pads bonded to corresponding subsets of the plurality of wafer-side bonding pads through corresponding sets of a plurality of bonding materials.
[0153] In some other embodiments, the wafer includes a plurality of interlayers, and the interconnect structure includes a redistribution interconnect structure buried in a redistribution dielectric layer, and the redistribution dielectric layer is located in the wafer and includes an organic polymer.
[0154] Some embodiments of the present utility model provide a structure including a probe assembly, including: a multi-layer structure including probe contact pads; an upper guide plate including an upper hole array therethrough; a lower guide plate including a lower hole array therethrough; a dielectric partition located between the upper guide plate and the lower guide plate and including an opening; and a probe array attached to the probe contact pads, the probe array vertically extending through the upper hole array and the lower hole array and vertically extending through the opening of the dielectric partition, where the lower guide plate includes a downward protrusion and a base, the downward protrusion has a first laterally extending section having a first width, the base is above the downward protrusion and has a second width greater than the first width.
[0155] In some other embodiments, the second width is at least five times the first width, and the first laterally extending section has a first length that is at least five times the first width.
[0156] In some other embodiments, the first laterally extending section of the downward protrusion extends laterally in a first horizontal direction, and the downward protrusion includes a second laterally extending section that extends laterally in a second horizontal direction perpendicular to the first horizontal direction.
[0157] In some other embodiments, the first laterally extending section of the downward protrusion extends laterally in a first horizontal direction, and the lower guide plate includes an additional downward protrusion that extends laterally in the first horizontal direction and is laterally spaced apart from the downward protrusion by a spacing that is at least five times the first width.
[0158] The foregoing text outlines the features of many embodiments, enabling those skilled in the art to better understand the embodiments of the present utility model from various aspects. Unless otherwise explicitly disclosed herein, each embodiment described using the term "comprising" also inherently discloses other embodiments that replace the term "comprising" with "consisting essentially of" or "consisting of". Whenever two or more elements are listed as alternatives in the same or different paragraphs, a Markush group including the list of two or more elements is also implicitly disclosed. Whenever the auxiliary verb "can" is used in the embodiments of the present utility model to describe the formation of an element or the performance of a processing step, embodiments that do not form such an element or perform such a processing step are also explicitly considered, provided that the resulting device or apparatus can provide equivalent results. In this way,
[0159] Whenever such an element formation or such a processing step is omitted, the auxiliary verb "can" applied to the performance of the element formation or the processing step should also be interpreted as "may" or "may or may not", capable of providing the same result or an equivalent result, and the equivalent result includes a slightly better result and a slightly worse result. Those skilled in the art should understand and can easily design or modify other processes and structures based on the embodiments of the present utility model to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the embodiments of the present utility model. Various changes, substitutions, or modifications can be made to the embodiments of the present utility model without departing from the spirit and scope of the embodiments of the present utility model.
Claims
1. A probe assembly structure, characterized in that: include: A multi-layer structure including a probe contact pad; an upper guide plate including an upper array of holes therethrough; a lower guide plate including a lower array of holes therethrough; a dielectric spacer located between the upper guide plate and the lower guide plate and including an opening; and A probe array is attached to the probe contact pad, the probe array extending vertically through the upper hole array and the lower hole array and the opening extending vertically through the dielectric spacer, wherein the lower guide plate includes a downward protrusion and a base, the downward protrusion has a first lateral extension section, the first lateral extension section has a first width, and the base is above the downward protrusion and has a second width greater than the first width.
2. The probe assembly structure according to claim 1, characterized in that: The second width is at least 5 times the first width, and wherein the first laterally extending section has a first length that is at least 5 times the first width.
3. The probe assembly structure according to claim 1, characterized in that: The first lateral extension section of the downward protrusion extends laterally along a first horizontal direction, and the downward protrusion includes a second lateral extension section, which extends laterally along a second horizontal direction perpendicular to the first horizontal direction.
4. The probe assembly structure according to claim 1, characterized in that: The first lateral extension section of the downward protrusion extends laterally along a first horizontal direction, and the lower guide plate includes an additional downward protrusion, which extends laterally along the first horizontal direction and is laterally spaced apart from the downward protrusion at a spacing that is at least 5 times the first width.
5. The probe assembly structure according to any one of claims 1 to 4, characterized in that: Also includes: A dielectric polymer layer is located on the bottom surface of the downward projection and has an array of openings through which the array of probes extends vertically.
6. The probe assembly structure according to any one of claims 1 to 4, characterized in that: Also includes: A probe card is attached to the multi-layer structure via an interconnect structure.
7. The probe assembly structure according to claim 6, characterized in that: The interconnect structure includes a solder ball array or an interposer.
8. The probe assembly structure according to any one of claims 1 to 4, characterized in that: The multi-layer structure also includes a redistribution structure and a multi-layer dielectric matrix. The multi-layer dielectric matrix surrounds and buries the redistribution structure.
9. The probe assembly structure according to claim 8, characterized in that: The probe contact pad is connected to the redistribution structure.
10. The probe assembly structure according to any one of claims 1 to 4, characterized in that: The dielectric spacer also includes a guide post extending through the opening of the dielectric spacer.