Slope current compensation circuit, driving chip, DCDC converter and vehicle

Abstract

The utility model provides a slope current compensation circuit, a driving chip, a DCDC converter and a vehicle, the slope current compensation circuit comprises an oscillator circuit, one end of the oscillator circuit is connected with a power supply, and the oscillator circuit is used for receiving voltage provided by the power supply and outputting a first reference current and an oscillation frequency signal corresponding to the first reference current; and the slope current generation circuit is connected with the other end of the oscillator circuit and is used for receiving the first reference current and the oscillation frequency signal and outputting compensation current. According to the utility model, the slope current generating circuit can be dynamically adjusted according to the working state of the oscillator circuit, so as to achieve the current compensation effect and ensure that the compensation amounts of the compensation current under different frequencies are similar, thereby expanding the selection range of the working frequency and improving the working efficiency. The influence of overcompensation during low-frequency work and insufficient compensation during high-frequency work on the circuit is reduced, and the working stability of the circuit is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of vehicles, and in particular to a ramp current compensation circuit, a driving chip, a DCDC converter and a vehicle. Background Art

[0002] In the related art, an oscillation frequency signal generated by an oscillator module is combined with a current generated by a fixed current generation module, and a ramp compensation current is generated by a ramp current generation module within each working cycle of the oscillation frequency signal. The magnitude of the ramp compensation current depends on the frequency of the oscillation frequency signal and the magnitude of the current bias. Since the magnitude of the current bias is fixed, the magnitude of the ramp compensation current is determined by the frequency of the oscillation frequency signal.

[0003] However, this solution has a significant drawback, that is, the compensation amount is directly related to the working frequency. However, current DCDC (DC-to-DC Converter) converters usually need to work stably within a relatively wide working frequency range. Therefore, this solution will limit the selection range of the working frequency, and cannot solve the influence of over-compensation at low frequencies and under-compensation at high frequencies on the circuit, thus affecting the stability of the circuit. Summary of the Utility Model

[0004] The utility model aims to solve at least one of the technical problems existing in the prior art.

[0005] To this end, one object of the utility model is to provide a ramp current compensation circuit, which enables the ramp current generation circuit to dynamically adjust according to the working state of the oscillator circuit, so as to achieve the current compensation effect, ensure that the compensation amounts of the compensation current at different frequencies are similar, thereby expanding the selection range of the working frequency, reducing the influence of over-compensation at low frequencies and under-compensation at high frequencies on the circuit, and improving the stability of the circuit operation.

[0006] To this end, the second object of the utility model is to provide a driving chip.

[0007] To this end, the third object of the utility model is to provide a DCDC (DC-to-DC Converter) converter.

[0008] To this end, the fourth object of the utility model is to provide a vehicle.

[0009] To achieve the above object, an embodiment of the first aspect of the present utility model provides a ramp current compensation circuit, comprising: an oscillator circuit, one end of the oscillator circuit is connected to a power supply for receiving the voltage provided by the power supply and outputting a first reference current and an oscillation frequency signal corresponding to the first reference current; a ramp current generation circuit, connected to the other end of the oscillator circuit for receiving the first reference current and the oscillation frequency signal and outputting a compensation current.

[0010] According to the ramp current compensation circuit of the present utility model, the oscillator circuit receives power supply by connecting to the power supply to ensure the normal operation of the circuit. In this process, the oscillator circuit generates a stable first reference current based on the voltage provided by the power supply and generates an oscillation frequency signal corresponding thereto. The ramp current generation circuit is connected to the other end of the oscillator circuit, so the ramp current generation circuit can receive the first reference current and the oscillation frequency signal from the oscillator circuit. The ramp current generation circuit will output a compensation current according to these two input signals, enabling the ramp current generation circuit to dynamically adjust according to the working state of the oscillator circuit to achieve the current compensation effect, ensuring that the compensation amount of the compensation current is similar at different frequencies, thereby expanding the selection range of the working frequency, reducing the influence of over-compensation during low-frequency operation and under-compensation during high-frequency operation on the circuit, and improving the stability of the circuit operation.

[0011] In addition, the ramp current compensation circuit according to the embodiment of the present utility model may further have the following additional technical features:

[0012] In some embodiments, the oscillator circuit includes: a reference current generation sub-circuit, a first end of the reference current generation sub-circuit is connected to the power supply, a second end of the reference current generation sub-circuit is connected to a first reference voltage terminal, and a third end of the reference current generation sub-circuit is grounded for receiving the voltage provided by the power supply and the first reference voltage provided by the first reference voltage terminal, and outputting the first reference current and a second reference current; a frequency signal generation sub-circuit, a first end of the frequency signal generation sub-circuit is connected to the power supply, and a second end of the frequency signal generation sub-circuit is connected to a fifth end of the reference current generation sub-circuit for receiving the second reference current and outputting the oscillation frequency signal.

[0013] In some embodiments, the reference current generating sub-circuit includes: a current generating sub-circuit, the first end of the current generating sub-circuit is connected to the first reference voltage terminal, the second end of the current generating sub-circuit is grounded, for receiving the first reference voltage and outputting a first current; a first current mirror circuit, the first end of the first current mirror circuit is connected to the power supply, the second end of the first current mirror circuit is connected to the third end of the current generating sub-circuit, for receiving the first current and outputting the first reference current and the second reference current.

[0014] In some embodiments, the current generating sub-circuit includes: a first operational amplifier, the positive input terminal of the first operational amplifier is connected to the first reference voltage terminal, the output terminal of the first operational amplifier is connected to the second end of the first current mirror circuit; a first resistor, one end of the first resistor is connected to the negative input terminal of the first operational amplifier, the other end of the first resistor is grounded, for outputting the first current; a first MOS transistor, the drain of the first MOS transistor is connected to the second end of the first current mirror circuit, the source of the first MOS transistor is connected to one end of the first resistor, the gate of the first MOS transistor is connected to the output terminal of the first operational amplifier, for turning on or off the current generating sub-circuit composed of the first operational amplifier and the first resistor.

[0015] In some embodiments, the first current mirror circuit includes: a second MOS transistor, the source of the second MOS transistor is connected to the power supply, the drain of the second MOS transistor is connected to the third end of the current generating sub-circuit; a third MOS transistor, the source of the third MOS transistor is connected to the power supply, the gate of the third MOS transistor is connected to the gate of the second MOS transistor, for receiving the first current and the first reference voltage and outputting the first reference current; a fourth MOS transistor, the source of the fourth MOS transistor is connected to the power supply, the gate of the fourth MOS transistor is connected to the drain of the second MOS transistor, for receiving the first current and the first reference voltage and outputting the second reference current.

[0016] In some embodiments, the frequency signal generation sub - circuit includes: a second current mirror circuit, the first end of the second current mirror circuit is connected to the fifth end of the first current mirror circuit, the second end of the second current mirror circuit is grounded, for receiving the second reference current and outputting a second current; a third current mirror circuit, the first end of the third current mirror circuit is connected to a power supply, the second end of the third current mirror circuit is connected to the fifth end of the second current mirror circuit, for receiving the voltage provided by the power supply and outputting a third current; a frequency output sub - circuit, the first end of the frequency output sub - circuit is connected to the third end of the third current mirror circuit, the third end of the frequency output sub - circuit is connected to the fourth end of the second current mirror circuit, for receiving the second current and the third current and outputting the oscillation frequency signal.

[0017] In some embodiments, the second current mirror circuit includes: a fifth MOS transistor, the drain of the fifth MOS transistor is connected to the fifth end of the first current mirror circuit, the source of the fifth MOS transistor is grounded; a sixth MOS transistor, the drain of the sixth MOS transistor is connected to the second end of the third current mirror circuit, the source of the sixth MOS transistor is grounded, the gate of the sixth MOS transistor is connected to the gate of the fifth MOS transistor; a seventh MOS transistor, the drain of the seventh MOS transistor is connected to the third end of the frequency output sub - circuit, the source of the seventh MOS transistor is grounded, the gate of the seventh MOS transistor is connected to the drain of the fifth MOS transistor.

[0018] In some embodiments, the third current mirror circuit includes: an eighth MOS transistor, the source of the eighth MOS transistor is connected to the power supply, the drain of the eighth MOS transistor is connected to the fifth end of the second current mirror circuit; a ninth MOS transistor, the source of the ninth MOS transistor is connected to the power supply, the drain of the ninth MOS transistor is connected to the first end of the frequency output sub - circuit, the gate of the ninth MOS transistor is connected to the gate of the eighth MOS transistor.

[0019] In some embodiments, the frequency output sub - circuit includes: a voltage switching sub - circuit, the first end of the voltage switching sub - circuit is connected to the third end of the third current mirror circuit, the third end of the voltage switching sub - circuit is connected to the fourth end of the second current mirror circuit; a trigger sub - circuit, the first end of the trigger sub - circuit is connected to the sixth end of the voltage switching sub - circuit, the second end of the trigger sub - circuit is connected to the fifth end of the voltage switching sub - circuit.

[0020] In some embodiments, the voltage switching sub-circuit includes: a MOS transistor sub-circuit, a first end of the MOS transistor sub-circuit is connected to a third end of the third current mirror circuit, and a third end of the MOS transistor sub-circuit is connected to a fourth end of the second current mirror circuit; a first capacitor, one end of the first capacitor is connected to a fourth end of the MOS transistor sub-circuit, and the other end of the first capacitor is connected to a third end of the second current mirror circuit; a comparator group, a first end of the comparator group is connected to a second reference voltage, a second end of the comparator group is connected to the fourth end of the MOS transistor sub-circuit, and a third end of the comparator group is connected to a third reference voltage, for controlling charging or discharging of the first capacitor.

[0021] In some embodiments, the comparator group includes: a first comparator, a positive input terminal of the first comparator is connected to the second reference voltage, and a negative input terminal of the first comparator is connected to a fifth end of the MOS transistor sub-circuit; a second comparator, a positive input terminal of the second comparator is connected to the negative input terminal of the first comparator, and a negative input terminal of the second comparator is connected to the third reference voltage.

[0022] In some embodiments, the MOS transistor sub-circuit includes: a tenth MOS transistor, a source of the tenth MOS transistor is connected to the third end of the third current mirror circuit, and a gate of the tenth MOS transistor is connected to the fourth end of the second current mirror circuit; an eleventh MOS transistor, a drain of the eleventh MOS transistor is connected to a drain of the tenth MOS transistor, a source of the eleventh MOS transistor is connected to the fourth end of the second current mirror circuit, and a gate of the eleventh MOS transistor is connected to a gate of the tenth MOS transistor.

[0023] In some embodiments, the trigger sub-circuit includes: an RS flip-flop, a first input terminal of the RS flip-flop is connected to an output terminal of the first comparator, a second input terminal of the RS flip-flop is connected to the output terminal of the first comparator, and a first output terminal of the RS flip-flop is connected to a second end of the MOS transistor sub-circuit; a steady-state flip-flop, one end of the steady-state flip-flop is connected to a second output terminal of the RS flip-flop, for outputting the oscillation frequency signal.

[0024] In some embodiments, the ramp current generating circuit includes: a ramp voltage generating sub-circuit, one end of the ramp voltage generating sub-circuit is connected to the other end of the oscillator circuit, for receiving the first reference current and the oscillation frequency signal and outputting a ramp voltage; a voltage-to-current conversion sub-circuit, one end of the voltage-to-current conversion sub-circuit is connected to the other end of the ramp voltage generating sub-circuit, for receiving the ramp voltage and outputting the compensation current.

[0025] In some embodiments, the ramp voltage generating sub-circuit includes: a twelfth MOS transistor, the drain of the twelfth MOS transistor is connected to the power supply, the source of the twelfth MOS transistor is grounded, and the gate of the twelfth MOS transistor is connected to the fourth terminal of the frequency signal generating sub-circuit; a second capacitor, one end of the second capacitor is connected to the drain of the twelfth MOS transistor, and the other end of the second capacitor is connected to the source of the twelfth MOS transistor or grounded.

[0026] In some embodiments, the voltage-to-current conversion sub-circuit includes: a thirteenth MOS transistor, the source of the thirteenth MOS transistor is grounded, for receiving the ramp voltage and outputting a fourth current; a fourth current mirror circuit, the first terminal of the fourth current mirror circuit is connected to the power supply, and the second terminal of the fourth current mirror circuit is connected to the drain of the thirteenth MOS transistor, for receiving the fourth current and outputting the compensation current.

[0027] In some embodiments, the fourth current mirror circuit includes: a fourteenth MOS transistor, the source of the fourteenth MOS transistor is connected to the power supply, and the drain of the fourteenth MOS transistor is connected to the drain of the thirteenth MOS transistor; a fifteenth MOS transistor, the source of the fifteenth MOS transistor is connected to the source of the fourteenth MOS transistor, and the gate of the fifteenth MOS transistor is connected to the gate of the fourteenth MOS transistor or the drain of the fourteenth MOS transistor, for outputting the compensation current.

[0028] In some embodiments, the voltage-to-current conversion sub-circuit further includes: a second operational amplifier, the positive input terminal of the second operational amplifier is connected to the drain of the twelfth MOS transistor, the negative input terminal of the second operational amplifier is connected to the source of the twelfth MOS transistor, and the output terminal of the second operational amplifier is connected to the gate of the thirteenth MOS transistor.

[0029] In some embodiments, the voltage-to-current conversion sub-circuit further includes: a second resistor, one end of the second resistor is connected to the negative input terminal of the second operational amplifier, and the other end of the second resistor is connected to the other end of the second capacitor, for outputting the fourth current.

[0030] To achieve the above object, an embodiment of the second aspect of the present invention provides a driving chip, including the ramp current compensation circuit described in the above-mentioned first aspect embodiment of the present invention.

[0031] According to the driving chip of the embodiment of the present utility model, the oscillator circuit receives power supply by connecting to the power source to ensure the normal operation of the circuit. In this process, the oscillator circuit generates a stable first reference current based on the voltage provided by the power source, and generates an oscillation frequency signal corresponding thereto based on the first reference current. The ramp current generation circuit is connected to the other end of the oscillator circuit, so the ramp current generation circuit can receive the first reference current and the oscillation frequency signal from the oscillator circuit. The ramp current generation circuit will output a compensation current according to these two input signals, so that the ramp current generation circuit can dynamically adjust according to the working state of the oscillator circuit to achieve the current compensation effect, ensure that the compensation amount of the compensation current is similar at different frequencies, thereby expanding the selection range of the working frequency, reducing the influence of over-compensation during low-frequency operation and under-compensation during high-frequency operation on the circuit, and improving the stability of the circuit operation.

[0032] To achieve the above object, an embodiment of the third aspect of the present utility model provides a DCDC converter, which includes the driving chip described in the embodiment of the second aspect of the present utility model, or the ramp current compensation circuit described in any embodiment of the first aspect of the present utility model.

[0033] According to the DCDC converter of the embodiment of the present utility model, the oscillator circuit receives power supply by connecting to the power source to ensure the normal operation of the circuit. In this process, the oscillator circuit generates a stable first reference current based on the voltage provided by the power source, and generates an oscillation frequency signal corresponding thereto based on the first reference current. The ramp current generation circuit is connected to the other end of the oscillator circuit, so the ramp current generation circuit can receive the first reference current and the oscillation frequency signal from the oscillator circuit. The ramp current generation circuit will output a compensation current according to these two input signals, so that the ramp current generation circuit can dynamically adjust according to the working state of the oscillator circuit to achieve the current compensation effect, ensure that the compensation amount of the compensation current is similar at different frequencies, thereby expanding the selection range of the working frequency, reducing the influence of over-compensation during low-frequency operation and under-compensation during high-frequency operation on the circuit, and improving the stability of the circuit operation.

[0034] To achieve the above object, an embodiment of the fourth aspect of the present utility model provides a vehicle, which includes the DCDC converter described in the embodiment of the third aspect of the present utility model.

[0035] According to the vehicle of the embodiment of the present utility model, the oscillator circuit receives power supply by connecting to a power source to ensure the normal operation of the circuit. During this process, the oscillator circuit will generate a stable first reference current based on the voltage provided by the power source, and generate an oscillation frequency signal corresponding to the first reference current. The ramp current generation circuit is connected to the other end of the oscillator circuit, so the ramp current generation circuit can receive the first reference current and the oscillation frequency signal from the oscillator circuit. The ramp current generation circuit will output a compensation current according to these two input signals, so that the ramp current generation circuit can dynamically adjust according to the working state of the oscillator circuit to achieve the current compensation effect, ensure that the compensation amount of the compensation current is similar at different frequencies, thereby expanding the selection range of the working frequency, reducing the influence of over-compensation during low-frequency operation and under-compensation during high-frequency operation on the circuit, and improving the stability of the circuit operation.

[0036] Additional aspects and advantages of the present utility model will be given in part in the following description, become apparent in part from the following description, or be understood through the practice of the present utility model. Brief Description of the Drawings

[0037] The above and / or additional aspects and advantages of the present utility model will become apparent and be easily understood from the description of the embodiments in conjunction with the following drawings, wherein:

[0038] Figure 1 is a schematic structural diagram of the generation of a ramp compensation current according to an embodiment of the related art;

[0039] Figure 2 is a schematic structural diagram of a ramp current compensation circuit according to an embodiment of the present utility model;

[0040] Figure 3 is a schematic structural diagram of a ramp current compensation circuit according to another embodiment of the present utility model;

[0041] Figure 4 is a circuit schematic diagram of an oscillator circuit according to an embodiment of the present utility model;

[0042] Figure 5 is a circuit schematic diagram of a ramp current generation circuit according to an embodiment of the present utility model;

[0043] Figure 6 is a schematic diagram of a compensation current according to an embodiment of the present utility model;

[0044] Figure 7 is a circuit schematic diagram of a ramp current generation circuit according to an embodiment of the present utility model;

[0045] Figure 8 is a schematic diagram of a compensation current according to another embodiment of the present utility model;

[0046] Figure 9 is a structural block diagram of a driving chip according to an embodiment of the present utility model;

[0047] Figure 10 is a structural block diagram of a DCDC converter according to an embodiment of the present utility model;

[0048] Figure 11 is a structural block diagram of a vehicle according to an embodiment of the present utility model.

[0049] Reference numerals:

[0050] Ramp current compensation circuit 100;

[0051] Oscillator circuit 1;

[0052] Reference current generation sub-circuit 11;

[0053] Current generation sub-circuit 111; First current mirror circuit 112;

[0054] Frequency signal generation sub-circuit 12;

[0055] Second current mirror circuit 121; Third current mirror circuit 122;

[0056] Trigger sub-circuit 1231;

[0057] MOS transistor sub-circuit 12301; Comparator group 12302;

[0058] RS flip-flop 12311;

[0059] Ramp current generation circuit 2;

[0060] Ramp voltage generation sub-circuit 21; Voltage-current conversion sub-circuit 22; Fourth current mirror circuit 221;

[0061] Driving chip 200;

[0062] DCDC converter 300;

[0063] Vehicle 400. Detailed implementation manners

[0064] The embodiments of the present utility model will be described in detail below. The embodiments described with reference to the drawings are exemplary. The embodiments of the present utility model will be described in detail below.

[0065] The PWM (Pulse Width Modulation) peak current mode DCDC converter is a widely used modulation method, which has the advantages of small output ripple voltage, excellent frequency characteristics, high linearity, and high conversion efficiency under heavy load conditions. However, when the duty cycle is greater than 50%, the rising slope of the inductor current will be less than its falling slope, which will cause any small perturbation current to be continuously amplified during the operation of the circuit, and then generate subharmonic oscillations, making the system unstable.

[0066] A ramp compensation current can be superimposed inside the integrated circuit to make the rising slope greater than the falling slope. In this way, even if there is a perturbation current, it will be continuously reduced over time, thus ensuring that the system can maintain a stable operating state.

[0067] In related technologies, such as Figure 1 As shown in the schematic diagram of the structure for generating the ramp compensation current, the magnitude of the ramp compensation current ISLOPE1 depends on the frequency of the oscillation frequency signal CLK and the fixed current IB1 generated by the fixed current generation module. Since the magnitude of the fixed current IB1 is fixed, the magnitude of the ramp compensation current ISLOPE1 is actually determined by the frequency of the oscillation frequency signal CLK. However, this scheme has a significant drawback, that is, the compensation amount is directly related to the operating frequency.

[0068] Specifically, when the operating frequency of the DCDC converter is low, the frequency of the oscillation frequency signal CLK generated by the oscillator is also low, which will result in a smaller ramp compensation current ISLOPE1 generated within the same time, possibly causing overcompensation, affecting the load-carrying capacity of the system, and making the system unable to effectively handle load changes.

[0069] On the contrary, when the operating frequency is high, the frequency of the oscillation frequency signal CLK increases, and the ramp compensation current ISLOPE1 generated within the same time will also increase, but it may not be sufficient to fully compensate the rising slope of the inductor current at high frequencies, resulting in undercompensation, which may trigger subharmonic oscillations and make the system unstable.

[0070] As Figure 2 shown, it is the schematic diagram of the structure of the ramp current compensation circuit according to the embodiment of the present invention. In the ramp current compensation circuit 100 proposed in the embodiment of the present invention, the first reference current IB2 related to the frequency generated by the oscillator circuit 1 replaces the fixed current IB1 generated by the fixed current generation module in the related technology implementation, and the first reference current IB2 and the oscillation frequency signal CLK generate the compensation current ISLOPE2 through the ramp current generation circuit 2.

[0071] Among them, the first reference current IB2 is characterized in that its current magnitude is positively correlated with the frequency of the oscillation frequency signal CLK. The compensation current ISLOPE2 is characterized in that its current magnitude is positively correlated with the first reference current IB2 and negatively correlated with the frequency of the oscillation frequency signal CLK.

[0072] Therefore, when other conditions are certain, the compensation amounts of the compensation current ISLOPE2 at different frequencies are similar, thereby expanding the selection range of the circuit operating frequency. Especially when operating at low frequencies, it can effectively avoid the influence of over-compensation on the circuit operating range; while when operating at high frequencies, it can also reduce the sub-harmonic oscillation caused by insufficient compensation and improve the stability of the circuit.

[0073] Next, refer to Figures 2 - 8 to describe the ramp current compensation circuit of the embodiment of the present invention.

[0074] Figure 2 is a schematic diagram of the ramp current compensation circuit according to the embodiment of the present invention. As Figure 2 shown, the ramp current compensation circuit 100 includes: an oscillator circuit 1 and a ramp current generation circuit 2.

[0075] Among them, as Figure 2 shown, one end of the oscillator circuit 1 is connected to the power supply, used to receive the voltage VDD provided by the power supply, and output the first reference current IB2 and the oscillation frequency signal CLK corresponding to the first reference current IB2; the ramp current generation circuit 2 is connected to the other end of the oscillator circuit, used to receive the first reference current IB2 and the oscillation frequency signal CLK, and output the compensation current ISLOPE2.

[0076] Specifically, as Figure 2 shown, one end of the oscillator circuit 1 is connected to the power supply, used to receive the voltage VDD provided by the stable power supply as an input. Then, according to the received voltage VDD, the oscillator circuit 1 starts to work and outputs the first reference current IB2 and the oscillation frequency signal CLK corresponding to the first reference current IB2.

[0077] The other end of the oscillator circuit 1 is connected to the ramp current generation circuit 2. After receiving the first reference current IB2 and the oscillation frequency signal CLK output from the oscillator circuit 1, the ramp current generation circuit 2 outputs the compensation current ISLOPE2.

[0078] Therefore, the ramp current compensation circuit 100 generates a first reference current IB2 and an oscillation frequency signal CLK through the oscillator circuit 1. The ramp current generation circuit 2 outputs a compensation current ISLOPE2 based on the first reference current IB2 and the oscillation frequency signal CLK, which can ensure that the compensation amount of the compensation current ISLOPE2 remains similar at different frequencies. Therefore, regardless of how the frequency of the oscillation frequency signal CLK changes, the ramp current generation circuit 2 can provide a similar compensation current ISLOPE2, thereby improving the stability of the entire circuit.

[0079] Thus, in the ramp current compensation circuit 100 of the embodiment of the present invention, the oscillator circuit 1 receives power supply by connecting to the power supply to ensure the normal operation of the circuit. In this process, the oscillator circuit 1 generates a stable first reference current IB2 based on the voltage VDD provided by the power supply, and generates an oscillation frequency signal CLK corresponding to the first reference current IB2. The ramp current generation circuit 2 is connected to the other end of the oscillator circuit 1, so the ramp current generation circuit 2 can receive the first reference current IB2 and the oscillation frequency signal CLK from the oscillator circuit 1. The ramp current generation circuit 2 will output a compensation current ISLOPE2 according to these two input signals, enabling the ramp current generation circuit 2 to dynamically adjust according to the working state of the oscillator circuit 1 to achieve the current compensation effect, ensuring that the compensation amount of the compensation current ISLOPE2 is similar at different frequencies, thereby expanding the selection range of the working frequency, reducing the influence of over-compensation during low-frequency operation and under-compensation during high-frequency operation on the circuit, and improving the stability of the circuit operation.

[0080] In an embodiment of the present invention, in combination with Figure 3 and Figure 4 as shown, the oscillator circuit 1 includes: a reference current generation sub-circuit 11 and a frequency signal generation sub-circuit 12. The first end of the reference current generation sub-circuit 11 is connected to the power supply, the second end of the reference current generation sub-circuit 11 is connected to the first reference voltage terminal, and the third end of the reference current generation sub-circuit 11 is grounded, for receiving the voltage VDD provided by the power supply and the first reference voltage VREF1 provided by the first reference voltage terminal, and outputting a first reference current IB2 and a second reference current IB_OSC; the first end of the frequency signal generation sub-circuit 12 is connected to the power supply, and the second end of the frequency signal generation sub-circuit 12 is connected to the fifth end of the reference current generation sub-circuit 11, for receiving the second reference current IB_OSC and outputting an oscillation frequency signal CLK.

[0081] In the embodiment, as Figure 4As shown in the figure, the oscillator circuit 1 mainly consists of a reference current generation sub-circuit 11 and a frequency signal generation sub-circuit 12. The first end of the reference current generation sub-circuit 11 is connected to the power supply, and the second end of the reference current generation sub-circuit 11 is connected to the first reference voltage terminal, which can be used to set the reference value of current generation. The third end of the reference current generation sub-circuit 11 is grounded, which can be used to receive the voltage VDD provided by the power supply and the first reference voltage VREF1, thereby generating two reference currents, namely the first reference current IB2 and the second reference current IB_OSC.

[0082] The frequency signal generation sub-circuit 12 can generate an oscillation frequency signal CLK according to the reference current. The first end of the frequency signal generation sub-circuit 12 is connected to the power supply, and the second end of the frequency signal generation sub-circuit 12 is connected to the fifth end of the reference current generation sub-circuit 11, which can receive the second reference current IB_OSC output from the fifth end of the reference current generation sub-circuit 11. Based on the second reference current IB_OSC, the oscillation frequency signal CLK is output.

[0083] In an embodiment of the present invention, as Figure 4 shown, the reference current generation sub-circuit 11 includes: a current generation sub-circuit 111 and a first current mirror sub-circuit 112. The first end of the current generation sub-circuit 111 is connected to the first reference voltage terminal, and the second end of the current generation sub-circuit 111 is grounded, which is used to receive the first reference voltage VREF1 and output the first current I1. The first end of the first current mirror sub-circuit 112 is connected to the power supply, and the second end of the first current mirror sub-circuit 112 is connected to the third end of the current generation sub-circuit 111, which is used to receive the first current I1 and output the first reference current IB2 and the second reference current IB_OSC.

[0084] In the embodiment, as Figure 4 shown, the current generation sub-circuit 111 and the first current mirror sub-circuit 112 form the reference current generation sub-circuit 11. The first end of the current generation sub-circuit 111 is connected to the first reference voltage terminal, and the second end of the current generation sub-circuit 111 is grounded. When the current generation sub-circuit 111 receives the first reference voltage VREF1, the current generation sub-circuit 111 will output the first current I1 according to the first reference voltage VREF1.

[0085] The first end of the first current mirror sub-circuit 112 is connected to the power supply, and the second end of the first current mirror sub-circuit 112 is connected to the third end of the current generation sub-circuit 111 to receive the first current I1 output by the current generation sub-circuit 111. Then, based on the first current I1, the first current mirror sub-circuit 112 outputs the first reference current IB2 and the second reference current IB_OSC.

[0086] In an embodiment of the present invention, as Figure 4As shown, the current generation sub-circuit 111 includes: a first operational amplifier AMP1, a first resistor R1, and a first MOS transistor NM1. The positive input terminal of the first operational amplifier AMP1 is connected to the first reference voltage terminal, and the output terminal of the first operational amplifier AMP1 is connected to the second terminal of the first current mirror circuit 112; one end of the first resistor R1 is connected to the negative input terminal of the first operational amplifier AMP1, and the other end of the first resistor R1 is grounded, for outputting a first current I1; the drain of the first MOS transistor NM1 is connected to the second terminal of the first current mirror circuit 112, the source of the first MOS transistor NM1 is connected to one end of the first resistor R1, and the gate of the first MOS transistor NM1 is connected to the output terminal of the first operational amplifier AMP1, for turning on or off the current generation sub-circuit 111 composed of the first operational amplifier AMP1 and the first resistor R1.

[0087] In the embodiment, as Figure 4 shown, the current generation sub-circuit 111 is mainly composed of a first operational amplifier AMP1, a first resistor R1, and a first MOS transistor NM1.

[0088] Specifically, the positive input terminal (i.e., the + terminal) of the first operational amplifier AMP1 is connected to the first reference voltage terminal, the output terminal of the first operational amplifier AMP1 is connected to the second terminal of the first current mirror circuit 112, one end of the first resistor R1 is connected to the negative input terminal (i.e., the - terminal) of the first operational amplifier AMP1, and the other end of the first resistor R1 is grounded. In this way, the first operational amplifier AMP1 can make the voltage generated on the first resistor R1 equal to the first reference voltage VREF1, that is, the first current I1 flowing through the first resistor R1 = VREF1 / R1, and the first current I1 generates a first reference current IB2 and a second reference current IB_OSC through the first current mirror circuit 112.

[0089] The first MOS transistor NM1 acts as a switch. The drain of the first MOS transistor NM1 is connected to the second terminal of the first current mirror circuit 112, the source is connected to one end of the first resistor R1, and the gate is connected to the output terminal of the first operational amplifier AMP1. In this way, when the first operational amplifier AMP1 outputs a suitable voltage, the first MOS transistor NM1 will turn on, allowing current to flow from the first operational amplifier AMP1 through the first resistor R1 through the first MOS transistor NM1 and then into the first current mirror circuit 112. Conversely, if the voltage output by the first operational amplifier AMP1 is not sufficient to turn on the first MOS transistor NM1, the current generation sub-circuit 111 will be turned off.

[0090] Therefore, by turning on or off the current generation sub-circuit 111 composed of the first operational amplifier AMP1 and the first resistor R1 through the first MOS transistor NM1, the controllability and stability of the current generation sub-circuit 111 are ensured.

[0091] In an embodiment of the present utility model, as Figure 4 shown, the first current mirror circuit 112 includes: a second MOS transistor PM1, a third MOS transistor PM2, and a fourth MOS transistor PM3. The source of the second MOS transistor PM1 is connected to the power supply, and the drain of the second MOS transistor PM1 is connected to the third terminal of the current generation sub-circuit 111; the source of the third MOS transistor PM2 is connected to the power supply, and the gate of the third MOS transistor PM2 is connected to the gate of the second MOS transistor PM1 for receiving the first current I1 and the first reference voltage VREF1 and outputting the first reference current IB2; the source of the fourth MOS transistor PM3 is connected to the power supply, and the gate of the fourth MOS transistor PM3 is connected to the drain of the second MOS transistor PM1 for receiving the first current I1 and the first reference voltage VREF1 and outputting the second reference current IB_OSC.

[0092] In the embodiment, as Figure 4 shown, the sources of the second MOS transistor PM1, the third MOS transistor PM2, and the fourth MOS transistor PM3 are all connected to the power supply, and the drain of the second MOS transistor PM1 is connected to the third terminal of the current generation sub-circuit 111, that is, the drain of the second MOS transistor PM1 is connected to the drain of the first MOS transistor NM1.

[0093] The gate of the third MOS transistor PM2 is connected to the gate of the second MOS transistor PM1, so that the first current I1 and the first reference voltage VREF1 can be received, and thus the first reference current IB2 is output.

[0094] The gate of the fourth MOS transistor PM3 is connected to the drain of the second MOS transistor PM1. This connection method enables the fourth MOS transistor PM3 to receive the first current I1 and the first reference voltage VREF1, and thus the second reference current IB_OSC is output.

[0095] For example, if the relationship of the aspect ratios of the second MOS transistor PM1, the third MOS transistor PM2, and the fourth MOS transistor PM3 is 1:k2:k3, where k2 and k3 are proportionality coefficients, and the widths of the second MOS transistor PM1, the third MOS transistor PM2, and the fourth MOS transistor PM3 are denoted as W, and the lengths of the second MOS transistor PM1, the third MOS transistor PM2, and the fourth MOS transistor PM3 are denoted as L, then W / L = 1:k2:k3.

[0096] After determining the aspect ratios (i.e., W / L) of the second MOS transistor PM1, the third MOS transistor PM2, and the fourth MOS transistor PM3, the first reference current IB2 and the second reference current IB_OSC can be calculated according to the aspect ratios, and their specific calculation formulas are as follows:

[0097]

[0098] With this design, the first current mirror circuit 112 can accurately replicate the first current I1 output by the current generating sub-circuit 111 and generate two first reference currents IB2 and second reference current IB_OSC with a specific proportional relationship.

[0099] In an embodiment of the present invention, as Figure 4 shown, the frequency signal generating sub-circuit 12 includes: a second current mirror circuit 121, a third current mirror circuit 122, and a frequency output sub-circuit (not shown in the figure). Among them, the first end of the second current mirror circuit 121 is connected to the fifth end of the first current mirror circuit 112, and the second end of the second current mirror circuit 121 is grounded for receiving the second reference current IB_OSC and outputting a second current I2; the first end of the third current mirror circuit 122 is connected to the power supply, and the second end of the third current mirror circuit 122 is connected to the fifth end of the second current mirror circuit 121 for receiving the voltage VDD provided by the power supply and outputting a third current I3; the first end of the frequency output sub-circuit is connected to the third end of the third current mirror circuit 122, and the third end of the frequency output sub-circuit is connected to the fourth end of the second current mirror circuit 121 for receiving the second current I2 and the third current I3 and outputting an oscillation frequency signal CLK.

[0100] In the embodiment, as Figure 4 shown, the frequency signal generating sub-circuit 12 is mainly composed of a second current mirror circuit 121, a third current mirror circuit 122, and a frequency output sub-circuit.

[0101] Specifically, the second current mirror circuit 121 is connected to the fifth end of the first current mirror circuit 112 through its first end, and the second end of the second current mirror circuit 121 is grounded for receiving the second reference current IB_OSC. When receiving the second reference current IB_OSC, the second current mirror circuit 121 will output a second current I2 proportional to the second reference current IB_OSC.

[0102] Next, the third current mirror circuit 122 is connected to the power supply through its first end, and the second end of the third current mirror circuit 122 is connected to the fifth end of the second current mirror circuit 121 and also receives the voltage VDD provided by the power supply, so that the third current mirror circuit 122 can output a third current I3 based on the voltage VDD provided by the power supply and the second reference current IB_OSC received from the second current mirror circuit 121.

[0103] Among them, the second current I2 output by the second current mirror circuit 121 is equal to the third current I3 output by the third current mirror circuit 122, that is, the ratio of the second current I2 and the third current I3 is the same. For example, if the ratio coefficient is k4, then the ratio relationship between the second reference current IB_OSC and the second current I2 and the third current I3 is 1:k4:k4.

[0104] Finally, the first end of the frequency output sub-circuit is connected to the third end of the third current mirror circuit 122, and the third end of the third current mirror circuit 122 is connected to the fourth end of the second current mirror circuit 121. In this way, the frequency output sub-circuit can receive the currents from the two current mirror circuits at the same time, that is, the second current I2 and the third current I3. Based on these two currents, the frequency output sub-circuit can generate an oscillation frequency signal CLK.

[0105] In an embodiment of the present invention, as Figure 4 shown, the second current mirror circuit 121 includes: a fifth MOS transistor NM2, a sixth MOS transistor NM3, and a seventh MOS transistor NM4. The drain of the fifth MOS transistor NM2 is connected to the fifth end of the first current mirror circuit 112, and the source of the fifth MOS transistor NM2 is grounded; the drain of the sixth MOS transistor NM3 is connected to the second end of the third current mirror circuit 122, the source of the sixth MOS transistor NM3 is grounded, and the gate of the sixth MOS transistor NM3 is connected to the gate of the fifth MOS transistor NM2; the drain of the seventh MOS transistor NM4 is connected to the third end of the frequency output sub-circuit, the source of the seventh MOS transistor NM4 is grounded, and the gate of the seventh MOS transistor NM4 is connected to the drain of the fifth MOS transistor NM2.

[0106] In the embodiment, as Figure 4 shown, the fifth MOS transistor NM2, the sixth MOS transistor NM3, and the seventh MOS transistor NM4 form the second current mirror circuit 121. The drain of the fifth MOS transistor NM2 is connected to the fifth end of the first current mirror circuit 112, and is used to receive the second reference current IB_OSC from the first current mirror circuit 112. At the same time, the source of the fifth MOS transistor NM2 is grounded to form a current path.

[0107] Next, the drain of the sixth MOS transistor NM3 is connected to the second terminal of the third current mirror circuit 122, but its source is also grounded. The gate of the sixth MOS transistor NM3 is connected to the gate of the fifth MOS transistor NM2. The drain of the seventh MOS transistor NM4 is connected to the third terminal of the frequency output sub-circuit, the source of the seventh MOS transistor NM4 is grounded, and the gate of the seventh MOS transistor NM is connected to the drain of the fifth MOS transistor NM2. In this way, through the ingenious connection of three MOS transistors (NM2, NM3, and NM4), the second current mirror circuit 121 copies the second reference current IB_OSC from the first current mirror circuit 112 to the frequency output sub-circuit according to a certain ratio, thereby generating the oscillation frequency signal CLK.

[0108] In an embodiment of the present invention, as Figure 4 shown, the third current mirror circuit 122 includes: an eighth MOS transistor PM4 and a ninth MOS transistor PM5. The source of the eighth MOS transistor PM4 is connected to the power supply, and the drain of the eighth MOS transistor PM4 is connected to the fifth terminal of the second current mirror circuit 121. The source of the ninth MOS transistor PM5 is connected to the power supply, the drain of the ninth MOS transistor PM5 is connected to the first terminal of the frequency output sub-circuit, and the gate of the ninth MOS transistor PM5 is connected to the gate of the eighth MOS transistor PM4.

[0109] In the embodiment, as Figure 4 shown, the third current mirror circuit 122 is composed of an eighth MOS transistor PM4 and a ninth MOS transistor PM5.

[0110] Specifically, the source of the eighth MOS transistor PM4 is connected to the power supply, the drain of the eighth MOS transistor PM4 is connected to the fifth terminal of the second current mirror circuit 121, the source of the ninth MOS transistor PM5 is also connected to the power supply, and the drain of the ninth MOS transistor PM5 is connected to the first terminal of the frequency output sub-circuit. Then, the drain current of the ninth MOS transistor PM5 will directly affect the working state of the frequency output sub-circuit.

[0111] In addition, the gate of the ninth MOS transistor PM5 is connected to the gate of the eighth MOS transistor PM4, so that the drain current of the ninth MOS transistor PM5 will be in a certain ratio to the drain current of the eighth MOS transistor PM4. This ratio depends, for example, on the size ratio of the two MOS transistors.

[0112] Therefore, through the eighth MOS transistor PM4 and the ninth MOS transistor PM5, the third current mirror circuit 122 copies the second reference current IB_OSC from the second current mirror circuit 121 to the frequency output sub-circuit according to a certain ratio, thereby further affecting the working state of the frequency output sub-circuit.

[0113] In an embodiment of the present invention, as Figure 4As shown, the frequency output sub-circuit (not shown in the figure) includes: a voltage switching sub-circuit (not shown in the figure) and a trigger sub-circuit 1231. The first end of the voltage switching sub-circuit is connected to the third end of the third current mirror circuit 122, and the third end of the voltage switching sub-circuit is connected to the fourth end of the second current mirror circuit 121; the first end of the trigger sub-circuit 1231 is connected to the sixth end of the voltage switching sub-circuit, and the second end of the trigger sub-circuit 1231 is connected to the fifth end of the voltage switching sub-circuit.

[0114] In an embodiment, as Figure 4 shown, the frequency output sub-circuit mainly consists of a voltage switching sub-circuit and a trigger sub-circuit 1231. Among them, the voltage switching sub-circuit can play a role in adjusting and switching voltages, and the trigger sub-circuit 1231 triggers corresponding actions according to the received information.

[0115] Specifically, the first end of the voltage switching sub-circuit is connected to the third end of the third current mirror circuit 122, and the voltage switching sub-circuit can switch the voltage or current inside it according to the third current I3 output by the received third current mirror circuit 122.

[0116] The third end of the voltage switching sub-circuit is connected to the fourth end of the second current mirror circuit 121, enabling the voltage switching sub-circuit to interact with the second current mirror circuit 121. For example, it may ensure the stability and reliability of the entire circuit by adjusting or stabilizing the second current I2 in the second current mirror circuit 121.

[0117] On the other hand, the first end of the trigger sub-circuit 1231 is connected to the sixth end of the voltage switching sub-circuit and can receive the voltage signal from the voltage switching sub-circuit, while the second end of the trigger sub-circuit 1231 is connected to the fifth end of the voltage switching sub-circuit. Through this connection method, for example, it can feedback or control the working state of the voltage switching sub-circuit, ensuring that the frequency output sub-circuit can achieve precise control and stable output of the oscillation frequency signal CLK through the coordinated work between the voltage switching sub-circuit and the trigger sub-circuit 1231, and at the same time ensuring the reliability and stability of the entire circuit.

[0118] In an embodiment of the present utility model, as Figure 4As shown in the figure, the voltage switching sub-circuit includes: a MOS transistor sub-circuit 12301, a first capacitor C1, and a comparator group 12302. The first end of the MOS transistor sub-circuit 12301 is connected to the third end of the third current mirror circuit 122, and the third end of the MOS transistor sub-circuit 12301 is connected to the fourth end of the second current mirror circuit 121. One end of the first capacitor C1 is connected to the fourth end of the MOS transistor sub-circuit 12301, and the other end of the first capacitor C1 is connected to the third end of the second current mirror circuit 121. The first end of the comparator group 12302 is connected to the second reference voltage, the second end of the comparator group 12302 is connected to the fourth end of the MOS transistor sub-circuit 12301, and the third end of the comparator group 12302 is connected to the third reference voltage, which is used to control the charging or discharging of the first capacitor C1.

[0119] In the embodiment, as Figure 4 shown, the voltage switching sub-circuit mainly consists of a MOS transistor sub-circuit 12301, a comparator group 12302, and a first capacitor C1.

[0120] Specifically, the first end of the MOS transistor sub-circuit 12301 is connected to the third end of the third current mirror circuit 122, so as to receive the current or voltage signal from the third current mirror circuit 122. The third end of the MOS transistor sub-circuit 12301 is connected to the fourth end of the second current mirror circuit 121. Therefore, the state change of the MOS transistor sub-circuit 12301 will directly affect the working state of the second current mirror circuit 121.

[0121] One end of the first capacitor C1 is connected to the fourth end of the MOS transistor sub-circuit 12301, and the other end is connected to the third end of the second current mirror circuit 121. In this way, according to the third current I3 of the third current mirror circuit 122, and the second current I2 of the second current mirror circuit 121, and according to the proportional relationship between the second reference current IB_OSC and the second current I2 and the third current I3, the charging and discharging speed of the first capacitor C1 can be controlled. Since the magnitudes of the second current I2 and the third current I3 are equal, the charging and discharging speeds of the first capacitor C1 can be made consistent, which helps to generate a stable oscillation frequency signal CLK.

[0122] One end of the comparator group 12302 is connected to the second reference voltage VREF2, its second end is connected to the fourth end of the MOS transistor sub-circuit 12301, and its third end is connected to the third reference voltage VREF3. By comparing the voltage at the fourth end of the MOS transistor sub-circuit 12301 with the relationship between these two reference voltages, and controlling the charging or discharging of the first capacitor C1 according to the comparison result, the stable operation and precise control of the circuit can be realized.

[0123] In an embodiment of the present invention, as Figure 4As shown, the comparator group 12302 includes: a first comparator CMP1 and a second comparator CMP2. The positive input terminal of the first comparator CMP1 is connected to the second reference voltage VREF2, and the negative input terminal of the first comparator CMP1 is connected to the fifth terminal of the MOS transistor circuit 12301. The positive input terminal of the second comparator CMP2 is connected to the negative input terminal of the first comparator CMP1, and the negative input terminal of the second comparator CMP2 is connected to the third reference voltage VREF3.

[0124] In an embodiment, as Figure 4 shown, the positive input terminal (i.e., the + terminal) of the first comparator CMP1 is connected to the second reference voltage VREF2, while the negative input terminal (i.e., the - terminal) of the first comparator CMP1 is connected to the fifth terminal of the MOS transistor circuit 12301. In this way, the first comparator CMP1 continuously monitors the difference between the voltage at the fifth terminal of the MOS transistor circuit 12301 and the second reference voltage VREF2.

[0125] The positive input terminal (i.e., the + terminal) of the second comparator CMP2 is directly connected to the negative input terminal (i.e., the - terminal) of the first comparator CMP1 and is also connected to the fifth terminal of the MOS transistor circuit 12301, while the negative input terminal (i.e., the - terminal) of the second comparator CMP2 is connected to the third reference voltage VREF3. This connection method enables the second comparator CMP2 to compare the difference between the voltage at the fifth terminal of the MOS transistor circuit 12301 and the third reference voltage VREF3.

[0126] In this way, the comparator group 12302 can accurately determine the current voltage state based on the comparison results of the voltage at the fifth terminal of the MOS transistor circuit 12301 with the two reference voltages, and accordingly control other parts of the voltage switching sub - circuit, such as the first capacitor C1, to perform corresponding charging or discharging operations on the first capacitor C1, thereby achieving accurate voltage switching and control.

[0127] In an embodiment of the present utility model, as Figure 4 shown, the MOS transistor circuit 12301 includes: a tenth MOS transistor PM6 and an eleventh MOS transistor NM5. The source of the tenth MOS transistor PM6 is connected to the third terminal of the third current mirror circuit 122, and the gate of the tenth MOS transistor PM6 is connected to the fourth terminal of the second current mirror circuit 121. The drain of the eleventh MOS transistor NM5 is connected to the drain of the tenth MOS transistor PM6, the source of the eleventh MOS transistor NM5 is connected to the fourth terminal of the second current mirror circuit 121, and the gate of the eleventh MOS transistor NM5 is connected to the gate of the tenth MOS transistor PM6.

[0128] In an embodiment, as Figure 4As shown, in the MOS transistor circuit 12301, the source of the tenth MOS transistor PM6 is connected to the third terminal of the third current mirror circuit 122, such that the third current mirror circuit 122 provides a current source for the tenth MOS transistor PM6. The gate of the tenth MOS transistor PM6 is connected to the fourth terminal of the second current mirror circuit 121, and the on-state of the tenth MOS transistor PM6 can be controlled according to the output voltage of the second current mirror circuit 121.

[0129] The drain of the eleventh MOS transistor NM5 is connected to the drain of the tenth MOS transistor PM6, forming a series structure of two MOS transistors, such that current can flow from the tenth MOS transistor PM6 to the eleventh MOS transistor NM5. Since the source of the eleventh MOS transistor NM5 is also connected to the fourth terminal of the second current mirror circuit 121, in this way, the voltage reference points of the gate of the tenth MOS transistor PM6 and the source of the eleventh MOS transistor NM5 are the same, and the gate of the eleventh MOS transistor NM5 is connected to the gate of the tenth MOS transistor PM6, such that the gate voltages of the two MOS transistors are equal. Therefore, these two MOS transistors will have the same on characteristics, that is, these two MOS transistors will turn on or off simultaneously, and precise control of the current can also be achieved.

[0130] In an embodiment of the present invention, as Figure 4 shown, the trigger sub-circuit 1231 includes: an RS flip-flop 12311 and a steady-state flip-flop. The first input terminal S of the RS flip-flop 12311 is connected to the output terminal of the first comparator CMP1, the second input terminal R of the RS flip-flop 12311 is connected to the output terminal of the second comparator CMP2, and the first output terminal Q of the RS flip-flop 12311 is connected to the second terminal of the MOS transistor circuit 12301; one end of the steady-state flip-flop is connected to the second output terminal of the RS flip-flop 12311 for outputting an oscillation frequency signal.

[0131] In the embodiment, as Figure 4 shown, the trigger sub-circuit 1231 is composed of an RS flip-flop 12311 and a steady-state flip-flop, wherein the steady-state flip-flop includes, for example, a monostable flip-flop.

[0132] Specifically, the first input terminal S of the RS trigger 12311 is connected to the output terminal of the first comparator CMP1, and the second input terminal R of the RS trigger 12311 is connected to the output terminal of the second comparator CMP2. In this way, when the voltage of the first capacitor C1 is detected by the first comparator CMP1 and the second comparator CMP2, the two comparators will compare the voltage of the first capacitor C1 with the reference voltage and output corresponding signals. These signals are transmitted to the RS trigger 12311. Since the first output terminal Q of the RS trigger 12311 is connected to the second end of the MOS tube circuit 12301, when the RS trigger 12311 receives the signal, it can control the charging and discharging state of the first capacitor C1. Then, the second output terminal of the RS trigger 12311 A control signal, such as CT, will be output, so that the charging and discharging state of the first capacitor C1 is switched according to the control signal CT, and the first output terminal Q of the RS trigger 12311 will simultaneously generate an original oscillation frequency signal, such as CLK1.

[0133] On the other hand, in order to obtain a frequency signal with the same frequency and a shorter high level time, the second output terminal of the RS trigger 12311 Connect a steady-state trigger, then the second output terminal of the RS trigger 12311 The output original oscillation frequency signal CLK1 will be transmitted to the steady-state trigger for shaping. The steady-state trigger converts the original oscillation frequency signal CLK1 into a high-level pulse with a specified width, thereby generating an oscillation frequency signal CLK with the same frequency as the original oscillation frequency signal CLK1 but a shorter high-level time.

[0134] Among them, the frequency f of the oscillation frequency signal CLK CLK It can be obtained according to the following calculation formula:

[0135]

[0136] According to calculation formula (3), when other conditions are constant, adjusting the value of the first resistor R1 can simultaneously change the first reference current IB2 and the frequency f of the oscillation frequency signal CLK. CLK .

[0137] In one embodiment of the present invention, Figure 3 and Figure 5As shown in the figure, the ramp current generation circuit 2 includes: a ramp voltage generation sub-circuit 21 and a voltage-current conversion sub-circuit 22. One end of the ramp voltage generation sub-circuit 21 is connected to the other end of the oscillator circuit 1, and is used to receive the first reference current IB2 and the oscillation frequency signal CLK, and output a ramp voltage VSLOPE; one end of the voltage-current conversion sub-circuit 22 is connected to the other end of the ramp voltage generation sub-circuit 21, and is used to receive the ramp voltage VSLOPE and output a compensation current ISLOPE2.

[0138] In an embodiment, as Figure 5 shown, the voltage generation circuit mainly consists of two sub-circuits, namely, a ramp voltage generation sub-circuit 21 and a voltage-current conversion sub-circuit 22. Among them, one end of the ramp voltage generation sub-circuit 21 is connected to the other end of the oscillator circuit 1, so that the ramp voltage generation sub-circuit 21 can receive the first reference current IB and the oscillation frequency signal CLK output by the oscillator circuit 1. Based on the first reference current IB and the oscillation frequency signal CLK, the ramp voltage generation sub-circuit 21 can output a ramp voltage VSLOPE.

[0139] On the other hand, the other end of the ramp voltage generation sub-circuit 21 is connected to one end of the voltage-current conversion sub-circuit 22, so that the voltage-current conversion sub-circuit 22 can receive the ramp voltage VSLOPE output from the ramp voltage generation sub-circuit 21, thereby converting the ramp voltage VSLOPE into a current signal to obtain a compensation current ISLOPE2.

[0140] In an embodiment of the present utility model, as Figure 5 shown, the ramp voltage generation sub-circuit 21 includes: a twelfth MOS transistor NM6' and a second capacitor C2. The drain of the twelfth MOS transistor NM6' is connected to the power supply, the source of the twelfth MOS transistor NM6' is grounded, and the gate of the twelfth MOS transistor NM6' is connected to the fourth terminal of the frequency signal generation sub-circuit 12; one end of the second capacitor C2 is connected to the drain of the twelfth MOS transistor NM6', and the other end of the second capacitor C2 is connected to the source of the twelfth MOS transistor or grounded.

[0141] In an embodiment, as Figure 5 shown, the twelfth MOS transistor NM6' and the second capacitor C2 form the ramp voltage generation sub-circuit 21. Among them, the drain of the twelfth MOS transistor NM6' is connected to the power supply, the source of the twelfth MOS transistor NM6' is grounded, and the gate of the twelfth MOS transistor NM6' is connected to the fourth terminal of the frequency signal generation sub-circuit 12. In this way, when the twelfth MOS transistor NM6' is turned on, the power supply will form a path between the twelfth MOS transistor NM6' and the ground, so that current can pass through.

[0142] On the other hand, one end of the second capacitor C2 is connected to the drain of the twelfth MOS transistor NM6' (i.e., the power supply), and the other end can be selectively connected to the source of the twelfth MOS transistor NM6' or directly grounded. When the twelfth MOS transistor NM6' is turned on, the second capacitor C2 starts to charge and store charge; when the twelfth MOS transistor NM6' is turned off, the second capacitor C2 discharges through the charge it stores, thereby forming a ramp voltage VSLOPE across its two ends, and the slope of this ramp voltage VSLOPE depends on the frequency f of the frequency signal CLK CLK and the capacitance value of the second capacitor C2.

[0143] Therefore, by controlling the frequency f of the frequency signal CLK CLK and the capacitance value of the second capacitor C2, the slope of the ramp voltage VSLOPE can be precisely adjusted, thereby achieving precise voltage control.

[0144] Specifically, when the first reference current IB2 continuously charges the second capacitor C2, the voltage of the second capacitor C2 gradually rises. Then, when the oscillation frequency signal CLK is at a high level, the gate of the twelfth MOS transistor NM6' will receive the oscillation frequency signal CLK, causing the twelfth MOS transistor NM6' to turn on. After the twelfth MOS transistor NM6' is turned on, the charge on the second capacitor C2 will discharge to the ground through the source of the twelfth MOS transistor NM6', causing the voltage across the two ends of the second capacitor C2 to rapidly drop. As the oscillation frequency signal CLK changes periodically, the twelfth MOS transistor NM6' will turn on or off periodically, thereby generating a periodic ramp voltage VSLOPE on the second capacitor C2.

[0145] The magnitude of the ramp voltage VSLOPE can be calculated by the calculation formula (4), that is:

[0146]

[0147] The calculation formula (4) is related to the duty cycle of the oscillation frequency signal CLK. The duty cycle is denoted as D for example. Among them, the duty cycle D represents the ratio of the time of the high level in the oscillation frequency signal to the entire periodic time. When other conditions are certain, the magnitude of the ramp voltage VSLOPE only depends on the duty cycle D.

[0148] Specifically, the larger the duty cycle D, the longer the conduction time of the twelfth MOS transistor NM6', and the longer the discharge time of the second capacitor C2, so the amplitude of the ramp voltage VSLOPE is smaller; conversely, the smaller the duty cycle D, the shorter the conduction time of the twelfth MOS transistor NM6', and the shorter the discharge time of the second capacitor C2, so the amplitude of the ramp voltage VSLOPE is larger.

[0149] In an embodiment of the present invention, asFigure 5 As shown, the voltage-to-current conversion sub-circuit 22 includes: the thirteenth MOS transistor NM7 and the fourth current mirror circuit 221. The source of the thirteenth MOS transistor NM7 is grounded and is used to receive the ramp voltage VSLOPE and output the fourth current I4. The first end of the fourth current mirror circuit 221 is connected to the power supply, and the second end of the fourth current mirror circuit 221 is connected to the drain of the thirteenth MOS transistor NM7 and is used to receive the fourth current I4 and output the compensation current ISLOPE2.

[0150] In the embodiment, as Figure 5 shown, the voltage-to-current conversion sub-circuit 22 is composed of the thirteenth MOS transistor NM7 and the fourth current mirror circuit 221. Among them, the source of the thirteenth MOS transistor NM7 is directly grounded to receive the ramp voltage VSLOPE, so as to output the fourth current I4. When the ramp voltage VSLOPE changes, the fourth current I4 output by the drain of the thirteenth MOS transistor NM7 also changes accordingly, and this change is linear, that is, the increase or decrease of the ramp voltage VSLOPE will cause the increase or decrease of the fourth voltage I4, realizing the conversion from voltage to current.

[0151] Next, one end of the fourth current mirror circuit 221 is connected to the power supply, and the power supply serves as the source of the current. The second end of the fourth current mirror circuit 221 is connected to the drain of the thirteenth MOS transistor NM7 to receive the fourth current I4 output by the thirteenth MOS transistor NM7. The fourth current mirror circuit 221 copies and outputs the fourth current I4 as the compensation current ISLOPE2 through the internal current mirror effect. The compensation current ISLOPE2 is proportional to the magnitude of the fourth current I4, and the proportional relationship between the output current and the input current can be changed by adjusting the structural parameters of the fourth current mirror circuit 221.

[0152] Among them, the following relationship can be obtained for the fourth current I4 output by the thirteenth MOS transistor NM7 according to the saturation region current formula:

[0153]

[0154] Among them, k5 is the process parameter constant of the thirteenth MOS transistor NM7 and is a known quantity; V TH7 is the turn-on threshold of the thirteenth MOS transistor NM7. It is known from the calculation formula (5) that the larger the duty cycle D, the larger the fourth current I4.

[0155] In summary, the voltage-to-current conversion sub-circuit 22 converts the ramp voltage VSLOPE into the fourth current I4 through the thirteenth MOS transistor NM7, and then uses the fourth current mirror circuit 221 to copy and output the fourth current I4 as the compensation current ISLOPE2, realizing the accurate conversion from voltage to current.

[0156] In an embodiment of the present utility model, the fourth current mirror circuit 221 includes: a fourteenth MOS transistor PM7 and a fifteenth MOS transistor PM8. The source of the fourteenth MOS transistor PM7 is connected to the power supply, and the drain of the fourteenth MOS transistor PM7 is connected to the drain of the thirteenth MOS transistor NM7. The source of the fifteenth MOS transistor PM8 is connected to the source of the fourteenth MOS transistor PM7, and the gate of the fifteenth MOS transistor PM8 is connected to the gate of the fourteenth MOS transistor PM7 or the drain of the fourteenth MOS transistor PM7, for outputting a compensation current ISLOPE2.

[0157] In the embodiment, as Figure 5 shown, the fourth current mirror circuit 221 is composed of a fourteenth MOS transistor PM7 and a fifteenth MOS transistor PM8. Among them, the drain of the fourteenth MOS transistor PM7 is connected to the drain of the thirteenth MOS transistor NM7, and the source of the fourteenth MOS transistor PM7 is connected to the power supply, so as to ensure the stable working voltage of the fourteenth MOS transistor PM7.

[0158] Next, the source of the fifteenth MOS transistor PM8 is connected to the source of the fourteenth MOS transistor PM7, so that the source voltages of the two MOS transistors are kept the same. There are two possible connection methods for the gate of the fifteenth MOS transistor PM8. One is to connect it to the gate of the fourteenth MOS transistor PM7, so that the gate-source voltage of the fifteenth MOS transistor PM8 will be the same as that of the fourteenth MOS transistor PM7, thus ensuring that the two MOS transistors work under the same bias conditions; the other is to connect it to the drain of the fourteenth MOS transistor PM7.

[0159] The drain of the fifteenth MOS transistor PM8 is used to output the compensation current ISLOPE2. Since the voltages of the gate and source of the fifteenth MOS transistor PM8 and the fourteenth MOS transistor PM7 are the same, the drain current of the fifteenth MOS transistor PM8 will be in a certain proportion to the drain current of the fourteenth MOS transistor PM7, so as to output the compensation current ISLOPE2.

[0160] Specifically, the fourth current I4 is converted into the compensation current ISLOPE2 through the fourth current mirror circuit 221. For example, the relationship between the aspect ratios (i.e., W / L) of the fourteenth MOS transistor PM7 and the fifteenth MOS transistor PM8 is 1:k6, that is, W / L = 1:k6, then the compensation current ISLOPE2 = k6 × I4. That is, the calculation formula (6) of the compensation current ISLOPE2 is as follows:

[0161]

[0162] It can be seen from the calculation formula (6) that the relationship between the compensation current ISLOPE2 and the duty cycle D is a quadratic function. The schematic diagram of the compensation current ISLOPE2 and the oscillation frequency signal CLK can be referred to Figure 6 asFigure 6 As shown, the compensation current ISLOPE2 is a quadratic function from the first duty cycle D1 to the second duty cycle D2 within the oscillation frequency signal CLK period tCLK.

[0163] Adopting such a circuit design ensures that at a low duty cycle, the current slope of the ramp current ISLOPE2 is relatively small, while at a high duty cycle, the current slope of the compensation current ISLOPE2 is relatively large.

[0164] For example, when the duty cycle is less than 50%, the relatively small compensation current ISLOPE2 is sufficient to maintain the normal operating state of the circuit and has a relatively small impact on the circuit, which helps to reduce unnecessary power consumption and potential instability.

[0165] On the contrary, when the duty cycle is greater than 50%, the circuit may face the risk of sub-harmonic oscillation. At this time, a larger compensation current ISLOPE2 is required to ensure the stability of the circuit. By adjusting the slope of the ramp current ISLOPE2, this circuit achieves precise control of the compensation current ISLOPE2 at different duty cycles, thereby ensuring the stable operation of the DCDC converter at a high duty cycle while minimizing the impact on the circuit at a low duty cycle.

[0166] In an embodiment of the present utility model, as Figure 7 shown, the voltage-current conversion sub-circuit 22 further includes: a second operational amplifier AMP2. The positive input terminal of the second operational amplifier AMP2 is connected to the drain of the twelfth MOS transistor NM6', the negative input terminal of the second operational amplifier AMP2 is connected to the source of the twelfth MOS transistor NM6', and the output terminal of the second operational amplifier AMP2 is connected to the gate of the thirteenth MOS transistor.

[0167] In the embodiment, as Figure 7 shown, the positive input terminal (i.e., the + terminal) of the second operational amplifier AMP2 is connected to the drain of the twelfth MOS transistor NM6', and the negative input terminal (i.e., the - terminal) of the second operational amplifier AMP2 is connected to the source of the twelfth MOS transistor NM6'. In this way, the second operational amplifier AMP2 can receive and amplify the voltage difference between the drain and source of the twelfth MOS transistor NM6'. When this voltage difference changes, the second operational amplifier AMP2 adjusts the voltage at its output terminal to maintain the equality of the voltages at the two input terminals.

[0168] The output terminal of the second operational amplifier AMP2 is directly connected to the gate of the thirteenth MOS transistor NM8, and a voltage equal to the ramp voltage VSLOPE can be generated on the second resistor R2.

[0169] In an embodiment of the present utility model, as Figure 7As shown, the voltage-current conversion sub-circuit 22 further includes: a second resistor R2, one end of the second resistor R2 is connected to the negative input terminal of the second operational amplifier AMP2, and the other end of the second resistor R2 is connected to the other end of the second capacitor C2, for outputting a fourth current.

[0170] In the embodiment, as Figure 7 shown, one end of the second resistor R2 is connected to the negative input terminal of the second operational amplifier AMP2, and the other end of the second resistor R2 is connected to the other end of the second capacitor C2. In this way, the second operational amplifier AMP2 will generate a voltage equal to the ramp voltage VSLOPE on the second resistor R2 and output a fourth current I4, that is, the fourth current I4 flowing through the second resistor R2 can be converted into a compensation current ISLOPE2 through the fourth current mirror circuit 221 composed of the fourteenth MOS transistor PM9 and the fifteenth MOS transistor PM10.

[0171] Specifically, in Figure 7 the shown circuit schematic diagram, the calculation formula (7) of the fourth current I4 is as follows:

[0172]

[0173] For example, when the width-to-length ratio of the fourteenth MOS transistor PM7 and the fifteenth MOS transistor PM8 is 1:k7, the calculation formula (8) of the compensation current ISLOPE2 is as follows:

[0174]

[0175] It can be seen from the calculation formula (8) that when other conditions are certain, the compensation current ISLOPE2 and the duty cycle D are in a linear relationship. The schematic diagram of the compensation current ISLOPE2 and the oscillation frequency signal CLK is as Figure 8 shown. It can be seen that the compensation current ISLOPE2 from the third duty cycle D3 to the fourth duty cycle D4 within the oscillation frequency signal period tCLK is a linear function, and the structure of this circuit is stable and the output result is independent of the process constants of the transistors.

[0176] According to the ramp current compensation circuit 100 of the present utility model, the oscillator circuit 1 receives power supply by connecting to the power source to ensure the normal operation of the circuit. In this process, the oscillator circuit 1 generates a stable first reference current IB2 based on the voltage VDD provided by the power source, and generates an oscillation frequency signal CLK corresponding to the first reference current IB2. The ramp current generation circuit 2 is connected to the other end of the oscillator circuit 1. Then, the ramp current generation circuit 2 can receive the first reference current IB2 and the oscillation frequency signal CLK from the oscillator circuit 1. The ramp current generation circuit 2 will output a compensation current ISLOPE2 according to these two input signals, so that the ramp current generation circuit 2 can dynamically adjust according to the working state of the oscillator circuit 1 to achieve the current compensation effect, ensure that the compensation amount of the compensation current ISLOPE2 is similar at different frequencies, thereby expanding the selection range of the working frequency, reducing the influence of over-compensation during low-frequency operation and under-compensation during high-frequency operation on the circuit, and improving the stability of the circuit operation.

[0177] The following describes the drive chip of the present utility model.

[0178] Reference Figure 9 to the structural block diagram of the drive chip shown. As Figure 9 shown, the drive chip 200 includes the ramp current compensation circuit 100 described in any one of the above embodiments of the present utility model.

[0179] According to the drive chip 200 of the embodiment of the present utility model, the oscillator circuit 1 receives power supply by connecting to the power source to ensure the normal operation of the circuit. In this process, the oscillator circuit 1 generates a stable first reference current IB2 based on the voltage VDD provided by the power source, and generates an oscillation frequency signal CLK corresponding to the first reference current IB2. The ramp current generation circuit 2 is connected to the other end of the oscillator circuit 1. Then, the ramp current generation circuit 2 can receive the first reference current IB2 and the oscillation frequency signal CLK from the oscillator circuit 1. The ramp current generation circuit 2 will output a compensation current ISLOPE2 according to these two input signals, so that the ramp current generation circuit 2 can dynamically adjust according to the working state of the oscillator circuit 1 to achieve the current compensation effect, ensure that the compensation amount of the compensation current ISLOPE2 is similar at different frequencies, thereby expanding the selection range of the working frequency, reducing the influence of over-compensation during low-frequency operation and under-compensation during high-frequency operation on the circuit, and improving the stability of the circuit operation.

[0180] The following describes the DCDC converter of the present utility model.

[0181] Reference Figure 10 to the structural block diagram of the DCDC converter shown. As Figure 10As shown, the DCDC converter 300 includes the drive chip 200 described in the embodiments of the present invention.

[0182] For the DCDC converter 300 according to the embodiments of the present invention, the oscillator circuit 1 receives power supply by connecting to the power source to ensure the normal operation of the circuit. In this process, the oscillator circuit 1 will generate a stable first reference current IB2 based on the voltage VDD provided by the power source, and generate an oscillation frequency signal CLK corresponding to the first reference current IB2. The ramp current generation circuit 2 is connected to the other end of the oscillator circuit 1, so the ramp current generation circuit 2 can receive the first reference current IB2 and the oscillation frequency signal CLK from the oscillator circuit 1. The ramp current generation circuit 2 will output a compensation current ISLOPE2 according to these two input signals, so that the ramp current generation circuit 2 can dynamically adjust according to the working state of the oscillator circuit 1 to achieve the current compensation effect, ensure that the compensation amount of the compensation current ISLOPE2 is similar at different frequencies, thereby expanding the selection range of the working frequency, reducing the influence of over-compensation during low-frequency operation and under-compensation during high-frequency operation on the circuit, and improving the stability of the circuit operation.

[0183] The vehicle of the present invention will be described below.

[0184] Reference Figure 11 to the structural block diagram of the vehicle shown. As Figure 11 shown, the vehicle 400 includes the DCDC converter 300 described in the above embodiments of the present invention.

[0185] For the vehicle 400 according to the embodiments of the present invention, the oscillator circuit 1 receives power supply by connecting to the power source to ensure the normal operation of the circuit. In this process, the oscillator circuit 1 will generate a stable first reference current IB2 based on the voltage VDD provided by the power source, and generate an oscillation frequency signal CLK corresponding to the first reference current IB2. The ramp current generation circuit 2 is connected to the other end of the oscillator circuit 1, so the ramp current generation circuit 2 can receive the first reference current IB2 and the oscillation frequency signal CLK from the oscillator circuit 1. The ramp current generation circuit 2 will output a compensation current ISLOPE2 according to these two input signals, so that the ramp current generation circuit 2 can dynamically adjust according to the working state of the oscillator circuit 1 to achieve the current compensation effect, ensure that the compensation amount of the compensation current ISLOPE2 is similar at different frequencies, thereby expanding the selection range of the working frequency, reducing the influence of over-compensation during low-frequency operation and under-compensation during high-frequency operation on the circuit, and improving the stability of the circuit operation.

[0186] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "schematic embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present utility model. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example.

[0187] Although the embodiments of the present utility model have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present utility model, and the scope of the present utility model is defined by the claims and their equivalents.

Claims

1. A slope current compensation circuit, characterized in that: include: an oscillator circuit, one end of which is connected to a power supply, and is used to receive a voltage provided by the power supply, and output a first reference current and an oscillation frequency signal corresponding to the first reference current; The ramp current generating circuit is connected to the other end of the oscillator circuit, and is used for receiving the first reference current and the oscillation frequency signal, and outputting a compensation current.

2. The slope current compensation circuit according to claim 1, characterized in that: The oscillator circuit comprises: a reference current generating subcircuit, wherein a first end of the reference current generating subcircuit is connected to the power supply, a second end of the reference current generating subcircuit is connected to the first reference voltage end, and a third end of the reference current generating subcircuit is grounded, and is used to receive a voltage provided by the power supply and a first reference voltage provided by the first reference voltage end, and output the first reference current and a second reference current; A frequency signal generating subcircuit, wherein the first end of the frequency signal generating subcircuit is connected to the power supply, and the second end of the frequency signal generating subcircuit is connected to the fifth end of the reference current generating subcircuit, for receiving the second reference current and outputting the oscillation frequency signal.

3. The slope current compensation circuit according to claim 2, characterized in that: The reference current generating subcircuit comprises: a current generating sub-circuit, wherein a first end of the current generating sub-circuit is connected to the first reference voltage end, a second end of the current generating sub-circuit is grounded, and is used to receive the first reference voltage and output a first current; A first current mirror circuit, wherein a first end of the first current mirror circuit is connected to the power supply, and a second end of the first current mirror circuit is connected to a third end of the current generating subcircuit, and is used for receiving the first current and outputting the first reference current and the second reference current.

4. The slope current compensation circuit according to claim 3, characterized in that: The current generating subcircuit comprises: A first operational amplifier, wherein a positive input terminal of the first operational amplifier is connected to the first reference voltage terminal, and an output terminal of the first operational amplifier is connected to a second terminal of the first current mirror circuit; a first resistor, one end of which is connected to the negative input terminal of the first operational amplifier, and the other end of which is grounded, for outputting the first current; A first MOS transistor, wherein the drain of the first MOS transistor is connected to the second end of the first current mirror circuit, the source of the first MOS transistor is connected to one end of the first resistor, and the gate of the first MOS transistor is connected to the output end of the first operational amplifier, and is used to turn on or off the current generating sub-circuit composed of the first operational amplifier and the first resistor.

5. The slope current compensation circuit according to claim 3, characterized in that: The first current mirror circuit comprises: a second MOS transistor, wherein a source of the second MOS transistor is connected to the power supply, and a drain of the second MOS transistor is connected to the third end of the current generating sub-circuit; a third MOS transistor, wherein a source of the third MOS transistor is connected to the power supply, a gate of the third MOS transistor is connected to the gate of the second MOS transistor, and is used to receive the first current and the first reference voltage and output the first reference current; A fourth MOS tube, wherein the source of the fourth MOS tube is connected to the power supply, the gate of the fourth MOS tube is connected to the drain of the second MOS tube, and is used for receiving the first current and the first reference voltage, and outputting the second reference current.

6. The slope current compensation circuit according to claim 3, characterized in that: The frequency signal generating subcircuit comprises: a second current mirror circuit, wherein a first end of the second current mirror circuit is connected to a fifth end of the first current mirror circuit, a second end of the second current mirror circuit is grounded, and is configured to receive the second reference current and output a second current; a third current mirror circuit, wherein a first end of the third current mirror circuit is connected to a power supply, a second end of the third current mirror circuit is connected to a fifth end of the second current mirror circuit, and is configured to receive a voltage provided by the power supply and output a third current; A frequency output subcircuit, wherein the first end of the frequency output subcircuit is connected to the third end of the third current mirror circuit, and the third end of the frequency output subcircuit is connected to the fourth end of the second current mirror circuit, for receiving the second current and the third current and outputting the oscillation frequency signal.

7. The slope current compensation circuit according to claim 6, characterized in that: The second current mirror circuit comprises: a fifth MOS transistor, wherein a drain of the fifth MOS transistor is connected to a fifth end of the first current mirror circuit, and a source of the fifth MOS transistor is grounded; a sixth MOS tube, wherein a drain of the sixth MOS tube is connected to the second end of the third current mirror circuit, a source of the sixth MOS tube is grounded, and a gate of the sixth MOS tube is connected to the gate of the fifth MOS tube; A seventh MOS tube, wherein the drain of the seventh MOS tube is connected to the third end of the frequency output sub-circuit, the source of the seventh MOS tube is grounded, and the gate of the seventh MOS tube is connected to the drain of the fifth MOS tube.

8. The slope current compensation circuit according to claim 6, characterized in that: The third current mirror circuit comprises: an eighth MOS transistor, wherein a source of the eighth MOS transistor is connected to the power supply, and a drain of the eighth MOS transistor is connected to the fifth end of the second current mirror circuit; A ninth MOS tube, wherein a source of the ninth MOS tube is connected to the power supply, a drain of the ninth MOS tube is connected to the first end of the frequency output sub-circuit, and a gate of the ninth MOS tube is connected to the gate of the eighth MOS tube.

9. The slope current compensation circuit according to claim 6, characterized in that: The frequency output subcircuit comprises: a voltage switching subcircuit, wherein a first end of the voltage switching subcircuit is connected to a third end of the third current mirror circuit, and a third end of the voltage switching subcircuit is connected to a fourth end of the second current mirror circuit; A trigger subcircuit, wherein the first end of the trigger subcircuit is connected to the sixth end of the voltage switching subcircuit, and the second end of the trigger subcircuit is connected to the fifth end of the voltage switching subcircuit.

10. The slope current compensation circuit according to claim 9, characterized in that: The voltage switching subcircuit comprises: A MOS tube circuit, wherein a first end of the MOS tube circuit is connected to a third end of the third current mirror circuit, and a third end of the MOS tube circuit is connected to a fourth end of the second current mirror circuit; A first capacitor, one end of the first capacitor is connected to the fourth end of the MOS tube circuit, and the other end of the first capacitor is connected to the third end of the second current mirror circuit; A comparator group, wherein the first end of the comparator group is connected to a second reference voltage, the second end of the comparator group is connected to a fourth end of the MOS tube circuit, and the third end of the comparator group is connected to a third reference voltage, for controlling the charging or discharging of the first capacitor.

11. The slope current compensation circuit according to claim 10, characterized in that: The comparator group comprises: A first comparator, wherein a positive input terminal of the first comparator is connected to the second reference voltage, and a negative input terminal of the first comparator is connected to the fifth terminal of the MOS tube circuit; A second comparator, wherein the positive input terminal of the second comparator is connected to the negative input terminal of the first comparator, and the negative input terminal of the second comparator is connected to a third reference voltage.

12. The slope current compensation circuit according to claim 10, characterized in that: The MOS tube circuit comprises: a tenth MOS transistor, wherein a source of the tenth MOS transistor is connected to the third end of the third current mirror circuit, and a gate of the tenth MOS transistor is connected to the fourth end of the second current mirror circuit; An eleventh MOS tube, wherein the drain of the eleventh MOS tube is connected to the drain of the tenth MOS tube, the source of the eleventh MOS tube is connected to the fourth end of the second current mirror circuit, and the gate of the eleventh MOS tube is connected to the gate of the tenth MOS tube.

13. The slope current compensation circuit according to claim 11, characterized in that: The trigger subcircuit comprises: An RS trigger, wherein a first input end of the RS trigger is connected to an output end of the first comparator, a second input end of the RS trigger is connected to an output end of the first comparator, and a first output end of the RS trigger is connected to a second end of the MOS tube circuit; A steady-state trigger, one end of which is connected to the second output end of the RS trigger, for outputting the oscillation frequency signal.

14. The slope current compensation circuit according to claim 6, characterized in that: The ramp current generating circuit comprises: a ramp voltage generating sub-circuit, one end of which is connected to the other end of the oscillator circuit, and is used for receiving the first reference current and the oscillation frequency signal, and outputting a ramp voltage; A voltage-to-current conversion subcircuit, one end of which is connected to the other end of the ramp voltage generating subcircuit, is used to receive the ramp voltage and output the compensation current.

15. The slope current compensation circuit according to claim 14, characterized in that: The ramp voltage generating subcircuit comprises: a twelfth MOS transistor, wherein a drain of the twelfth MOS transistor is connected to the power supply, a source of the twelfth MOS transistor is grounded, and a gate of the twelfth MOS transistor is connected to the fourth end of the frequency signal generating sub-circuit; A second capacitor, one end of the second capacitor is connected to the drain of the twelfth MOS transistor, and the other end of the second capacitor is connected to the source of the twelfth MOS transistor or is grounded.

16. The slope current compensation circuit according to claim 15, characterized in that: The voltage-to-current conversion subcircuit comprises: A thirteenth MOS tube, the source of which is grounded, and is used to receive the ramp voltage and output a fourth current; A fourth current mirror circuit, wherein a first end of the fourth current mirror circuit is connected to the power supply, and a second end of the fourth current mirror circuit is connected to the drain of the thirteenth MOS tube, and is used for receiving the fourth current and outputting the compensation current.

17. The slope current compensation circuit according to claim 16, characterized in that: The fourth current mirror circuit comprises: a fourteenth MOS tube, wherein the source of the fourteenth MOS tube is connected to the power supply, and the drain of the fourteenth MOS tube is connected to the drain of the thirteenth MOS tube; A fifteenth MOS tube, wherein the source of the fifteenth MOS tube is connected to the source of the fourteenth MOS tube, and the gate of the fifteenth MOS tube is connected to the gate of the fourteenth MOS tube or the drain of the fourteenth MOS tube, is used to output the compensation current.

18. The slope current compensation circuit according to claim 16, characterized in that: The voltage-to-current conversion subcircuit also includes: A second operational amplifier, wherein the positive input terminal of the second operational amplifier is connected to the drain of the twelfth MOS tube, the negative input terminal of the second operational amplifier is connected to the source of the twelfth MOS tube, and the output terminal of the second operational amplifier is connected to the gate of the thirteenth MOS tube.

19. The slope current compensation circuit according to claim 18, characterized in that: The voltage-to-current conversion subcircuit also includes: A second resistor, one end of the second resistor is connected to the negative input end of the second operational amplifier, and the other end of the second resistor is connected to the other end of the second capacitor, for outputting the fourth current.

20. A driver chip, characterized in that: include: A slope current compensation circuit as described in any one of claims 1 to 19.

21. A DCDC converter, characterized in that: include: The driver chip as claimed in claim 20, or the slope current compensation circuit as claimed in any one of claims 1 to 19.

22. A vehicle, characterized in that: include: The DCDC converter as claimed in claim 21.

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