Printed circuit board (PCB) for testing integrated circuit and integrated circuit testing device
By setting the test base and peripheral devices on the PCB board, the problem of distortion of the test results is solved, and more accurate and efficient integrated circuit testing is achieved.
Patent Information
- Application Number
- CN202520824873.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-28
- Publication Date
- 2025-06-17
- Estimated Expiration
- 2035-04-28
AI Technical Summary
When testing Tianmu chips, using the PCB layout design of the chip test base can easily lead to distortion of the test results, mainly due to the large package of the test base, the PCB board size becomes larger and the wiring is too long.
A PCB board for integrated circuit testing is designed. By setting a first test seat on the first surface of the PCB board, a peripheral device connected to the Tianmu chip is arranged on the second surface, and the area where the peripheral device is located is arranged opposite to the area where the first test seat is located is located, so as to reduce the volume and trace length of the PCB board.
It effectively prevents distortion of test results due to excessive packaging of the test seat, reduces the volume and trace length of the PCB board, and improves the accuracy of the test.
Smart Images
Figure CN222996768U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of integrated circuit testing, in particular to a PCB board for integrated circuit testing and an integrated circuit testing device. Background Art
[0002] Tianmu chip integrated circuit includes analog and digital functional blocks and integrates an Arm Cortex-M0+ core. The Tianmu chip integrated circuit is combined with a microcontroller and can control MOS transistors connected to a three-phase bridge or an H bridge, and is specially designed for automotive applications with high-power inductive loads.
[0003] In order to efficiently test the Tianmu chip, a chip test socket is usually used to realize the connection between the Tianmu chip and a PCB (Printed Circuit Board). However, in the PCB layout design using a related chip test socket, there is a great drawback when testing the Tianmu chip, which is likely to cause the test results to be distorted. Summary of the Utility Model
[0004] The utility model aims to at least solve one of the technical problems in the related technologies to some extent. For this purpose, an object of the utility model is to provide a PCB board for integrated circuit testing, which can effectively prevent the test results from being distorted when testing the Tianmu chip using a first test socket.
[0005] A second object of the utility model is to provide an integrated circuit testing device.
[0006] To achieve the above object, an embodiment of the first aspect of the utility model provides a PCB board for integrated circuit testing. The integrated circuit includes a Tianmu chip and peripheral devices connected to the Tianmu chip. The device includes: a first test socket for connecting the Tianmu chip; a PCB board body, a first surface of the PCB board body is used to set the first test socket, a second surface of the PCB board body is used to set the peripheral devices, and the first test socket and the peripheral devices are connected through traces provided on the first surface and the second surface, wherein the area where the peripheral devices are located and the area where the first test socket is located are oppositely arranged.
[0007] According to the PCB board for integrated circuit testing of the embodiment of the utility model, the first test socket is arranged on the first surface of the PCB board body, the peripheral devices connected to the Tianmu chip are arranged on the second surface of the PCB board body, and the area where the peripheral devices are located and the area where the first test socket is located are oppositely arranged, which can greatly reduce the problems of the increase in the volume of the PCB board and the excessive length of the PCB traces caused by the too large package of the first test socket, and effectively prevent the test results from being distorted.
[0008] In addition, the PCB board for integrated circuit testing proposed according to the above embodiments of the present utility model may further have the following additional technical features:
[0009] In some examples, a first wiring layer is provided on the first surface of the PCB board body, a first ground plane reference layer is provided between the first wiring layer and the PCB board body, a second wiring layer is provided on the second surface of the PCB board body, and a second ground plane reference layer is provided between the second wiring layer and the PCB board body. Among them, the traces are arranged on the first wiring layer and the second wiring layer, and the distance between the traces is greater than 3 times the line width.
[0010] In some examples, the distance between the first wiring layer and the first ground plane reference layer and the distance between the second wiring layer and the second ground plane reference layer are 4 mil.
[0011] In some examples, a plurality of vias are formed on the first surface and the second surface of the PCB board body, and each signal trace on the first wiring layer is connected to the corresponding signal trace on the second wiring layer through the vias.
[0012] In some examples, the via is a via after hole disk expansion processing and windowing processing, and a first return ground hole is formed at a position on one side of the PCB board body corresponding to the via.
[0013] In some examples, the peripheral devices at least include a current sense amplifier, a clock oscillator, an analog-to-digital converter ADC, a motor control pulse width modulation PWM module, a transceiver, at least one input / output unit, a resistor, and a capacitor; the traces at least include a current sense amplifier signal trace, a clock signal trace, an ADC signal trace, and a PWM signal trace.
[0014] In some examples, the current sense amplifier signal trace, the clock signal trace, the ADC signal trace, and the PWM signal trace all adopt a pseudo-differential form of routing. Ground copper strip isolation zones are provided on both sides of the current sense amplifier signal trace and the clock signal trace, and a plurality of second return ground holes are evenly formed at positions on the PCB board body corresponding to the current sense amplifier signal trace and the clock signal trace.
[0015] In some examples, at least one first positioning hole is formed at the position of the PCB board body where the first test socket is located for installing the first test socket; at least one second positioning hole is also formed within the area of the first test socket on the PCB board body for installing a second test socket for connecting a second chip, where the area occupied by the second test socket is smaller than the area occupied by the first test socket.
[0016] In some examples, contact pins in the first test socket area on the first surface of the PCB board body are soldered with a stencil layer, and vias are provided in the via pin area of the PCB board body corresponding to the Tianmu chip.
[0017] To achieve the above object, a second aspect embodiment of the present invention provides an integrated circuit testing device, including: a first test socket and a PCB board for integrated circuit testing as proposed in the first aspect embodiment of the present invention, wherein a groove is provided in the bottom cover of the first test socket corresponding to the position of the peripheral devices on the second surface of the PCB board.
[0018] Additional aspects and advantages of the present invention will be given in part in the following description, become apparent in part from the following description, or be understood through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 is a schematic diagram of the PCB board for integrated circuit testing in an embodiment of the present invention;
[0020] Figure 2 is a schematic diagram of the first surface of the PCB board with the first test socket installed in an embodiment of the present invention;
[0021] Figure 3 is a schematic diagram of the second surface of the PCB board when installing peripheral devices in an embodiment of the present invention;
[0022] Figure 4 is a schematic diagram of partial traces on the first surface of the PCB board body in an embodiment of the present invention Figure 1 ;
[0023] Figure 5 is a schematic diagram of partial traces on the second surface of the PCB board body in an embodiment of the present invention Figure 1 ;
[0024] Figure 6 is a schematic diagram of partial traces on the first surface of the PCB board body in an embodiment of the present invention Figure 2 ;
[0025] Figure 7 is a schematic diagram of partial traces on the second surface of the PCB board body in an embodiment of the present invention Figure 2 ;
[0026] Figure 8 is a schematic diagram of partial traces on the first surface of the PCB board body in an embodiment of the present invention Figure 3 ;
[0027] Figure 9 is a schematic diagram of the holes provided on the second surface of the PCB board body in an embodiment of the present invention;
[0028] Figure 10 It is a schematic diagram of the holes opened on the first surface of the PCB board body in the embodiment of the present utility model;
[0029] Figure 11 It is a schematic diagram of the solder mask layer provided on the PCB board body in the embodiment of the present utility model;
[0030] Figure 12 It is a schematic diagram of the through holes opened on the PCB board body in the embodiment of the present utility model;
[0031] Figure 13 It is a schematic diagram of the integrated circuit testing device in the embodiment of the present utility model.
[0032] Description of the reference numerals in the drawings:
[0033] 100, PCB board body; 200, first test socket; 300, Tianmu chip; 400, peripheral devices; 101, first wiring layer; 102, first ground plane reference layer; 103, second wiring layer; 104, second ground plane reference layer; 105, via hole; 106, first return ground hole; 107, second return ground hole; 108, first positioning hole; 109, second positioning hole; 110, through hole; 1000, integrated circuit testing device. Detailed implementation manners
[0034] The embodiments of the present utility model will be described in detail below. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals indicate the same or similar elements or elements with the same or similar functions from beginning to end. The embodiments described below with reference to the drawings are exemplary and are intended to explain the present utility model, but should not be construed as a limitation to the present utility model.
[0035] Before specifically describing the embodiments of the present application, for the convenience of understanding, the commonly used technical terms will be introduced first:
[0036] PCB (Printed Circuit Board, printed circuit board), also known as printed circuit board, is an important electronic component, a support for electronic components, and a carrier for the electrical connection of electronic components.
[0037] IC (Integrated Circuit, integrated circuit) chip test socket is a connector socket connecting the chip and the PCB board. Its main function is to meet the connection requirements between the chip pin terminals and the PCB test main board. The biggest advantage is that the chip can be replaced at any time during the chip testing process without damaging the chip and the PCB, thus realizing fast and efficient testing.
[0038] It should be noted that the test socket for Tianmu chips is often much larger than the chips themselves, and there are also height restrictions around it, which will cause the peripheral devices of Tianmu chips to be placed farther than normal, and the interconnection traces to become longer, resulting in problems outside the chips themselves and causing the test results to be distorted.
[0039] To solve the above problems, the embodiments of the present invention provide a PCB board for integrated circuit testing and an integrated circuit testing device. The PCB board for integrated circuit testing and the integrated circuit testing device according to the embodiments of the present invention will be described in detail below with reference to the accompanying drawings of the specification and specific implementation manners.
[0040] In the embodiments of the present invention, the integrated circuit may include a Tianmu chip 300 and peripheral devices 400 connected to the Tianmu chip 300.
[0041] Figure 1 is a schematic diagram of the PCB board for integrated circuit testing in the embodiments of the present invention. As Figure 1 shown, the PCB board for integrated circuit testing includes:
[0042] A PCB board body 100, the first surface of the PCB board body 100 is used to set a first test socket 200 connected to the Tianmu chip 300, the second surface of the PCB board body 100 is used to set peripheral devices 400, and the first test socket 200 and the peripheral devices 400 are connected through traces provided on the first surface and the second surface of the PCB board body 100. Among them, the area where the peripheral devices 400 are located is disposed opposite to the area where the first test socket 200 is located.
[0043] In the embodiments of the present invention, to prevent the test results from being distorted, the first test socket 200 is set on the first surface of the PCB board body 100, the peripheral devices 400 connected to the Tianmu chip 300 are set on the second surface of the PCB board body 100, and the area where the peripheral devices 400 are located is disposed opposite to the area where the first test socket 200 is located, which can greatly reduce the problems of the increased volume of the PCB board and the too long PCB traces caused by the too large package of the first test socket 200.
[0044] Specifically, the PCB board body 100 has a first surface and a second surface. The first surface can be denoted as the front surface of the PCB board body 100, and the second surface can be denoted as the back surface of the PCB board body 100. A first test socket 200 connected to the Tianmu chip 300 is set on the first surface of the PCB board body 100, see Figure 2 . Peripheral devices 400 of the Tianmu chip 300 are provided on the second surface of the PCB board body 100, see Figure 3。The area where the peripheral device 400 is located is disposed opposite to the area where the first test socket 200 is located. The first test socket 200 and the peripheral device 400 are connected by traces provided on the first surface and the second surface of the PCB board body 100.
[0045] In the embodiment of the present utility model, for the PCB board used in integrated circuit testing, the first test socket 200 is disposed on the first surface of the PCB board body 100, and the peripheral device 400 connected to the Tianmu chip 300 is disposed on the second surface of the PCB board body 100, and the area where the peripheral device 400 is located is disposed opposite to the area where the first test socket 200 is located, so as to solve the problems that the test socket of the Tianmu chip is much larger than the chip itself and is limited by the height around the test socket of the Tianmu chip, resulting in the need for the peripheral devices of the Tianmu chip to be placed farther than when used normally, the interconnection traces become longer, and problems other than the Tianmu chip itself are caused.
[0046] In a specific embodiment, as Figure 1 shown, the first surface of the PCB board body 100 is provided with a first wiring layer 101, a first ground plane reference layer 102 is provided between the first wiring layer 101 and the PCB board body 100, the second surface of the PCB board body 100 is provided with a second wiring layer 103, a second ground plane reference layer 104 is provided between the second wiring layer 103 and the PCB board body 100, wherein, the traces are disposed on the first wiring layer 101 and the second wiring layer 103, and the distance between the traces is greater than 3 times the line width.
[0047] In the embodiment of the present utility model, four layers of conductive materials are arranged in sequence on both sides of the PCB board body 100.
[0048] Specifically, the first surface of the PCB board body 100 is provided with a first wiring layer 101, and a first ground plane reference layer 102 is provided between the first wiring layer 101 and the PCB board body 100. The second surface of the PCB board body 100 is provided with a second wiring layer 103, and a second ground plane reference layer 104 is provided between the second wiring layer 103 and the PCB board body 100. That is, the first surface is the front of the PCB board body 100 and is the first wiring layer, and the second surface is the back of the PCB board body 100 and is the second wiring layer.
[0049] In the embodiment of the present utility model, the traces for connecting the first test socket 200 and the peripheral device 400 are disposed on the first wiring layer 101 and the second wiring layer 103 of the PCB board body 100, see Figures 4 - 8 。
[0050] To reduce the mutual interference between the traces, all signal traces are separated as far as possible. In the embodiment of the present utility model, the traces for connecting the first test socket 200 and the peripheral device 400 are greater than 3 times the line width.
[0051] In a specific embodiment, the distance between the first wiring layer 101 and the first ground plane reference layer 102 and the distance between the second wiring layer 103 and the second ground plane reference layer 104 are 4 mils.
[0052] Specifically, both the first ground plane reference layer 102 and the second ground plane reference layer 104 are ground plane layers, and the distances between the first wiring layer 101 and the first ground plane reference layer 102 and between the second wiring layer 103 and the second ground plane reference layer 104 are very close, only 4 mils (milli-inches). In this way, the PCB traces on the first wiring layer 101 and the second wiring layer 103 can have a reliable ground plane reference, reducing signal interference.
[0053] In a specific embodiment, as Figure 5 and 8 shown, a plurality of vias 105 are formed on the first surface and the second surface of the PCB board body 100, and the respective signal traces on the first surface are connected to the corresponding signal traces on the second surface through the vias 105.
[0054] Since the first test socket 200 of the Tianmu chip 300 is provided on the first surface of the PCB board body 100 and the peripheral devices 400 of the Tianmu chip 300 are provided on the second surface of the PCB board body 100, vias 105 are formed on the first surface and the second surface of the PCB board body 100 according to the trace trajectory, so that all the signal traces on the first surface are connected to the traces on the second surface through the vias 105, realizing the connection between the first test socket 200 and the peripheral devices 400 of the Tianmu chip 300.
[0055] In a specific embodiment, the via 105 is a via 105 after hole disk expansion processing and windowing processing, and a first return ground hole 106 is formed at a position on one side of the PCB board body 100 corresponding to the via 105. Refer to Figure 5 .
[0056] When manually testing signals, it is often necessary to place test points on each signal to be tested. The test points themselves will increase the size of the PCB board and affect the signal quality. In the embodiment of the present utility model, the vias 105 formed on the first surface and the second surface of the PCB board body 100 are processed, such as expanding the hole disks of these vias and performing windowing processing on the vias 105 on the first surface and the second surface of the PCB board body 100. This can not only facilitate manual testing but also save space, that is, it will not additionally increase the size of the PCB board.
[0057] The embodiment of the present utility model performs hole disk expansion processing and windowing processing on the vias 105 formed on the first surface and the second surface of the PCB board body 100, which saves more space than the traditional placement of test points and does not affect the signal quality.
[0058] In a specific embodiment, a first return ground via 106 is provided near each via 105 (within a preset range) of all signal traces.
[0059] For better effect, a first return ground via 106 is provided near each via 105 (within a preset distance range) to further reduce the influence of PCB traces.
[0060] In a specific embodiment, the peripheral device 400 includes at least a current sensing amplifier, a clock oscillator, an analog-to-digital converter ADC, a motor control pulse width modulation PWM module, a transceiver, at least one input / output unit, resistors, and capacitors; the traces include at least a current sensing amplifier signal trace, a clock signal trace, an ADC signal trace, and a PWM signal trace.
[0061] Specifically, the peripheral device 400 connected to the Tianmu chip 300 may include: a current sensing amplifier, a clock oscillator, an analog-to-digital converter ADC, a motor control pulse width modulation PWM module, a transceiver, at least one input / output unit, several resistors, and several capacitors.
[0062] A current sensing amplifier signal trace, a clock signal trace, a group of ADC signal traces, and a group of PWM signal traces are provided between the first test socket 200 and the above-mentioned peripheral device 400, see Figure 5 . The current sensing amplifier signal trace, the clock signal trace, a group of ADC signal traces, and a group of PWM signal traces are provided on the first surface and the second surface of the PCB board body 100, and all signal traces on the first surface are connected to the corresponding signal traces on the second surface through vias.
[0063] In a specific embodiment, the current sensing amplifier signal trace, the clock signal trace, the ADC signal trace, and the PWM signal trace all adopt a pseudo-differential form of routing. A ground copper strip isolation zone is provided for the current sensing amplifier signal trace and the clock signal trace. A plurality of second return ground vias 107 are evenly provided on one side of the current sensing amplifier signal trace and the clock signal trace, see Figure 5 . Among them, all holes provided on the PCB board body 100 in the embodiment of the present invention, see Figure 9 and Figure 10 .
[0064] Specifically, the current sensing amplifier signal trace, the clock signal trace, the ADC signal trace, and the PWM signal trace all adopt a pseudo-differential form to improve the anti-interference ability of each signal and ensure the integrity of signal transmission.
[0065] A ground copper strip isolation zone is provided on one side of the current sensing amplifier signal trace and the clock signal trace to avoid interfering with other signals. A plurality of second return ground holes 107 are evenly opened on one side of the current sensing amplifier signal trace and the clock signal trace to facilitate the return of the current sensing amplifier signal and the clock signal.
[0066] In the embodiment of the present utility model, the distances between the current sensing amplifier signal trace, the clock signal trace, a group of ADC signal traces and a group of PWM signal traces and the ground plane are very close. A first return ground hole 106 is drilled near each via of the signal trace, and the distance from other signals is greater than three times the line width. Among them, a ground copper strip isolation zone is also provided beside the amplifier signal trace and the clock signal trace, and a second return ground hole 107 is provided to facilitate signal return and avoid interfering with other signals, further reducing the test result distortion that the PCB board may cause due to the use of the first test socket (Tianmu chip test socket).
[0067] In a specific embodiment, the PCB board body 100 is provided with at least one first positioning hole 108 at the position of the first test socket for installing the first test socket; the PCB board body 100 is also provided with at least one second positioning hole 109 within the area of the first test socket for installing the second test socket for connecting the second chip, wherein the area occupied by the second test socket is smaller than the area occupied by the first test socket.
[0068] When conducting comprehensive chip testing, for higher efficiency and more comprehensive testing, parallel testing is often required. At this time, a large number of first test sockets are often needed, and the price of the first test socket itself is relatively expensive.
[0069] To reduce the total procurement quantity of the first test sockets and reduce costs and increase efficiency. The PCB board in the embodiment of the present utility model is provided with two different mounting holes for IC chip test sockets in the area of the first test socket. The Tianmu chip has 48 PINs (pins). The area occupied by the first test socket (the test socket for installing and connecting the Tianmu chip) is larger than the area occupied by the second test socket (the test socket for other chips with the same 48 PIN package). The PCB board in the embodiment of the present utility model can also fixedly install other IC chip test sockets with the same 48 PIN package in the area of the first test socket.
[0070] Specifically, positioning holes for two test sockets are respectively provided on the first surface of the PCB board to facilitate the use of compatible IC test sockets for installing other chips. Second positioning holes 109 are opened at the four corners of the smaller device silk screen frame in the inner circle for fixing other test sockets (the second test socket), and first positioning holes 108 are opened at the four corners of the outer device silk screen frame for fixing the Tianmu chip test socket.
[0071] In the embodiment of the present utility model, two different IC chip test sockets can be installed in the area of the Tianmu chip test socket on the PCB board. When the number of Tianmu chip test sockets is insufficient for large-scale parallel testing, other IC chip test sockets can be installed for testing, thereby reducing the total procurement quantity of IC chip test sockets and reducing costs and increasing efficiency.
[0072] In the embodiment of the present utility model, auxiliary positioning holes are also provided beside the first positioning hole 108 and the second positioning hole 109.
[0073] In a specific embodiment, a steel mesh layer is welded to the contact pins in the first test socket area on the first surface of the PCB board body 100, and a through hole 110 is provided in the through hole pin area of the PCB board body 100 corresponding to the Tianmu chip.
[0074] In the embodiment of the present utility model, the PCB board also has a compatible design for convenient soldering for long-term testing without the need to frequently replace the first test socket (Tianmu chip test socket).
[0075] Specifically, steel mesh layers are provided on the contact pins (PINs) on the first surface of the PCB board body 100 where the first test socket is placed. Refer to Figure 11 , which can be used for direct soldering with a pick-and-place machine during PCB board production. Steel mesh layers are provided on the contact PINs in the first test socket area of the first surface, and when performing some long-term test items that do not require frequent chip replacement, the Tianmu chip can be directly attached to this PCB board during the SMT (Surface Mount Technology) stage without occupying the Tianmu chip test socket for a long time, reducing the demand for chip test sockets and thus reducing costs.
[0076] Since the bottom of the Tianmu chip is provided with THMERL PIN (through hole pins) and needs to be soldered on the first surface of the PCB board, and the THMERL PIN at the bottom of the Tianmu chip has a large area and fast heat dissipation, which is prone to poor soldering. For this reason, special design is made for the THMERL PIN. Specifically, a relatively large through hole 110 is opened in the middle of the PCB board body 100 corresponding to the THMERL PIN of the Tianmu chip, and after soldering, tin can be filled into the soldering area of the THMERL PIN through this through hole 110 to ensure full soldering between the THMERL PIN of the Tianmu chip and the PCB board.
[0077] Refer to Figure 12 , the THMERL PIN at the bottom of the Tianmu chip adopts a special design with a relatively large through hole 110, and tin can be filled into the THMERL PIN when there is a need for manual soldering or when replacing the soldering chip to ensure reliability. It should be noted that Figure 12The labels marked as 1, 12, 13, 24, 25, 36, 37, and 48 correspond to the 48 pins of the Tianmu chip.
[0078] In the PCB board of the embodiment of the present utility model, for the test items of the IC chip test socket that do not require frequent replacement of the Tianmu chip, a design that can be surface-mounted during the production stage is carried out, so that the Tianmu chip test socket does not need to be occupied for a long time, further reducing the demand for the Tianmu chip test socket, thereby reducing costs; and for manual soldering or chip replacement, a special design is carried out for the THMERL PIN of the Tianmu chip, and a relatively large through hole is provided in the center of the THMERL PIN for filling solder into the THMERL PIN after soldering to ensure welding reliability.
[0079] The PCB board in the embodiment of the present utility model optimizes the ground return of the signal, reduces the interference between signals, thereby solving the problem of test result distortion caused by using the first test socket; at the same time, the PCB board in the embodiment of the present utility model also solves the problem of high cost caused by the large demand for IC test sockets during parallel testing through a compatible test socket package design and a design that can be SMT soldered and is convenient for manual soldering; and at the same time, a special via design is also adopted to replace the test point design to solve the problems of large test point space and affecting the signal quality on the board.
[0080] The PCB board for integrated circuit testing of the present utility model solves the problems that the PCB layout design will cause the size to become larger and the PCB trace to be too long, resulting in test result distortion when using an IC chip test socket for chip testing, the problem of requiring a large number of relatively expensive IC chip test sockets for large-scale parallel testing, and the problem that placing test points for each signal will cause the PCB size to become larger and affect the signal quality.
[0081] The PCB board for integrated circuit testing of the present utility model can shorten the PCB trace, take optimization measures to avoid the PCB layout design that causes test result distortion due to PCB layout design, and at the same time can achieve the purpose of reducing the PCB size, reducing the demand for the corresponding IC chip test socket, and reducing costs; finally, it can ensure that each signal of the Tianmu chip can be manually tested without additionally increasing the PCB size and affecting the signal quality.
[0082] The present utility model provides an integrated circuit testing device.
[0083] Figure 13 It is a schematic diagram of the integrated circuit testing device in the embodiment of the present utility model. As Figure 13As shown in the figure, the integrated circuit testing device 1000 may include: a first test socket 200 and a PCB board for integrated circuit testing as described above. Among them, the first test socket 200 is used to connect the Tianmu chip 300, and a groove is provided at the bottom cover of the first test socket 200 corresponding to the position of the peripheral device 400 on the second surface of the PCB board.
[0084] Since the first test socket for connecting the Tianmu chip is very large in volume, in the present utility model, all the peripheral devices 400 are directly placed on the second surface of the PCB board body 100, and the corresponding area of the base of the customized first test socket installed on the second surface is hollowed out, which not only greatly reduces the distance between the peripheral devices of the Tianmu chip and the chip, reduces the distortion of test results that may be caused by too long wiring between the peripheral devices and the chip, but also ensures the stability of the installation of the first test socket.
[0085] The integrated circuit testing device in the embodiment of the present utility model solves the problems that the PCB layout design will cause the size to become larger when using an IC chip test socket for chip testing, the PCB wiring is too long and the test results are distorted, solves the problem that a large number of relatively expensive IC chip test sockets are required for large-scale parallel testing, and the problem that placing test points for each signal will cause the PCB size to become larger and affect the signal quality.
[0086] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present utility model. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.
[0087] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by terms such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present utility model.
[0088] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of the present utility model, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise specifically defined.
[0089] In the present utility model, unless otherwise clearly stipulated and defined, terms such as "installed", "connected", "joined", "fixed", etc. shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two components or the interaction relationship between two components, unless otherwise clearly defined. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.
[0090] In the present utility model, unless otherwise clearly stipulated and defined, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "underneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.
[0091] Although the embodiments of the present utility model have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present utility model. Those of ordinary skill in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present utility model.
Claims
1. A PCB board for integrated circuit testing, characterized in that: The integrated circuit includes a Tianmu chip and peripheral devices connected to the Tianmu chip, and the PCB board includes: A PCB board body, wherein the first surface of the PCB board body is used to set a first test socket connected to the Tianmu chip, and the second surface of the PCB board body is used to set the peripheral device, the first test socket and the peripheral device are connected through traces set on the first surface and the second surface of the PCB board body, wherein the area where the peripheral device is located is arranged opposite to the area where the first test socket is located.
2. The PCB board for integrated circuit testing according to claim 1, characterized in that: A first wiring layer is provided on the first surface of the PCB board body, a first ground plane reference layer is provided between the first wiring layer and the PCB board body, a second wiring layer is provided on the second surface of the PCB board body, a second ground plane reference layer is provided between the second wiring layer and the PCB board body, wherein the traces are arranged in the first wiring layer and the second wiring layer, and the spacing between the traces is greater than 3 times the line width.
3. The PCB board for integrated circuit testing according to claim 2, characterized in that: The spacing between the first wiring layer and the first ground plane reference layer and the spacing between the second wiring layer and the second ground plane reference layer are 4 mil.
4. The PCB board for integrated circuit testing according to claim 2, characterized in that: A plurality of via holes are provided on the first surface and the second surface of the PCB body, and each signal trace on the first surface is connected to a corresponding signal trace on the second surface through the via holes.
5. The PCB board for integrated circuit testing according to claim 4, characterized in that: The via hole is a via hole that has been processed by hole plate enlargement and window opening, and the PCB board body is provided with a first return hole at a position corresponding to one side of the via hole.
6. The PCB board for integrated circuit testing according to claim 1, characterized in that: The peripheral devices at least include a current sensing amplifier, a clock crystal oscillator, an analog-to-digital converter ADC, a motor control pulse width modulation PWM module, a transceiver, at least one input / output unit, a resistor and a capacitor; The routing at least includes a current sensing amplifier signal routing, a clock signal routing, an ADC signal routing, and a PWM signal routing.
7. The PCB board for integrated circuit testing according to claim 6, characterized in that: The current sensing amplifier signal routing, the clock signal routing, the ADC signal routing and the PWM signal routing are all routed in a pseudo-differential form, and ground copper isolation belts are arranged on both sides of the current sensing amplifier signal routing and the clock signal routing, and a plurality of second return ground holes are evenly opened on the PCB board body corresponding to the positions of the current sensing amplifier signal routing and the clock signal routing.
8. The PCB board for integrated circuit testing according to claim 6, characterized in that: The PCB board body is provided with at least one first positioning hole at the position of the first test socket for installing the first test socket; the PCB board body is also provided with at least one second positioning hole in the area of the first test socket for installing a second test socket connected to a second chip, wherein the area occupied by the second test socket is smaller than the area occupied by the first test socket.
9. The PCB board for integrated circuit testing according to claim 1, characterized in that: The contact pins in the first test socket area on the first surface of the PCB body are welded with a steel mesh layer, and the PCB body is provided with through holes in the through hole pin area corresponding to the Tianmu chip.
10. An integrated circuit testing device, characterized in that: include: A first test socket and a PCB board for integrated circuit testing as claimed in any one of claims 1 to 9, wherein a groove is formed on the bottom cover of the first test socket corresponding to the position of the peripheral device on the second surface of the PCB board.