Double-sided packaging structure and electronic equipment

Abstract

The utility model provides a double-sided packaging structure and electronic equipment, and relates to the technical field of semiconductor packaging. The double-sided packaging structure comprises a substrate, a first surface of the substrate is provided with a first electronic component and a first plastic packaging layer, and the first plastic packaging layer wraps the first electronic component; the second surface is provided with a first photoresist layer, the first photoresist layer is provided with a first groove and a second groove, the second surface exposed by the first groove is provided with a second electronic component, the second groove is internally provided with a seed layer, and one side, deviating from the signal welding pad, of the seed layer is provided with a signal pin; the first photoresist layer and the second surface exposed by the first groove are provided with a second plastic package layer, the second plastic package layer wraps the signal pin and the second electronic component, and the signal pin is exposed out of the second plastic package layer. According to the double-sided packaging structure, when the seed layer and the signal pins are prepared, the grooves used can be obtained by exposing and developing the photoresist, slotting processing is not involved, and substrate damage caused by too deep slotting can be avoided.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technologies, and more particularly, to a dual-sided packaging structure and an electronic device. Background Art

[0002] With the development of packaging technologies and the increasingly urgent demands for product miniaturization and functional diversification, products with single-sided packaging can no longer meet the growing needs, and thus the dual-sided packaging process has emerged. The dual-sided packaging increases the available area of the product by mounting devices on both the front and back sides of the substrate, so as to accommodate more chips and achieve more functions.

[0003] The dual-sided packaging process usually requires forming signal pins for signal pads on the back side of the substrate to be led out. In the prior art, one method for forming signal pins is as follows: First, a chip is mounted on the back side of the substrate, and the chip and the signal pads are encapsulated; then, a groove is formed in the encapsulant to expose the signal pads, and signal pins electrically connected to the signal pads are formed in the groove. However, when forming the groove by the above method, the substrate is likely to be damaged due to over-deep grooving. Summary of the Utility Model

[0004] An object of this application is to provide a dual-sided packaging structure and an electronic device, which can avoid damaging the substrate when forming signal pins, in view of the deficiencies in the above prior art.

[0005] To achieve the above object, the technical solutions adopted in the embodiments of this application are as follows:

[0006] On the one hand, an embodiment of this application provides a dual-sided packaging structure, including: a substrate having opposite first and second surfaces, a first electronic component and a first encapsulant layer being provided on the first surface, the first electronic component being electrically connected to the substrate, and the first encapsulant layer wrapping the first electronic component; a first photoresist layer being provided on the second surface, a first groove and a second groove being provided on the first photoresist layer, the first groove exposing a part of the second surface, the second groove exposing signal pads on the second surface, a second electronic component being provided on the second surface exposed by the first groove, the second electronic component being electrically connected to the substrate, a seed layer being provided in the second groove, the seed layer covering the signal pads and the side walls of the second groove, a signal pin being provided on a side of the seed layer facing away from the signal pads, the signal pin being electrically connected to the signal pads through the seed layer, a second encapsulant layer being provided on the first photoresist layer and the second surface exposed by the first groove, the second encapsulant layer wrapping the signal pins and the second electronic component, and the signal pins being exposed from the second encapsulant layer.

[0007] Optionally, the signal pin includes a first conductive layer and a second conductive layer, the first conductive layer being in contact with the seed layer, the second conductive layer being provided on a side of the first conductive layer facing away from the seed layer, the second encapsulant layer wrapping the first conductive layer, and the second conductive layer being exposed from the second encapsulant layer.

[0008] Optionally, the melting point of the second conductive layer is lower than that of the first conductive layer.

[0009] Optionally, the signal pin further includes a conductive isolation layer. One side of the conductive isolation layer is attached to the first conductive layer, and the other side is attached to the second conductive layer. The conductive isolation layer is used to prevent the first conductive layer and the second conductive layer from diffusing into each other.

[0010] Optionally, the thickness of the conductive isolation layer is less than the thicknesses of the first conductive layer and the second conductive layer, respectively.

[0011] Optionally, the material of the first conductive layer is copper, the material of the second conductive layer is tin, and the material of the conductive isolation layer is nickel.

[0012] Optionally, the first conductive layer is cylindrical and the second conductive layer is spherical.

[0013] Optionally, the surface of the second encapsulation layer facing away from the substrate is flush with the surface of the second electronic component facing away from the substrate.

[0014] Optionally, the surface of the conductive isolation layer facing away from the substrate is flush with the surface of the second electronic component facing away from the substrate.

[0015] On the other hand, an embodiment of the present application provides an electronic device, including the dual-sided encapsulation structure as described in any one of the above.

[0016] The beneficial effects of the present application include:

[0017] The present application provides a double-sided encapsulation structure, including: a substrate having opposite first and second surfaces. A first electronic component and a first encapsulation layer are provided on the first surface. The first electronic component is electrically connected to the substrate, and the first encapsulation layer wraps the first electronic component. A first photoresist layer is provided on the second surface. A first groove and a second groove are provided on the first photoresist layer. The first groove exposes part of the second surface, and the second groove exposes a signal pad on the second surface. A second electronic component is provided on the second surface exposed by the first groove. The second electronic component is electrically connected to the substrate. A seed layer is provided in the second groove. The seed layer covers the signal pad and the side wall of the second groove. A signal pin is provided on a side of the seed layer facing away from the signal pad. The signal pin is electrically connected to the signal pad through the seed layer. A second encapsulation layer is provided on the first photoresist layer and the second surface exposed by the first groove. The second encapsulation layer wraps the signal pin and the second electronic component, and the signal pin is exposed from the second encapsulation layer. When preparing this double-sided encapsulation structure, the seed layer and the signal pin can be formed by using the first photoresist layer and the second photoresist layer respectively first, and then the second photoresist layer and part of the first photoresist layer are removed, the second electronic component is installed, and the signal pin and the second electronic component are encapsulated. When preparing the seed layer and the signal pin, the grooves used are obtained by exposing and developing the photoresist, without involving grooving processing. Therefore, substrate damage caused by over-deep grooving can be avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and thus should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0019] Figure 1 It is a schematic structural diagram of the double-sided encapsulation structure provided by the embodiment of the present application;

[0020] Figure 2 It is one of the schematic diagrams of the preparation process of the double-sided encapsulation structure provided by the embodiment of the present application;

[0021] Figure 3 It is a schematic structural diagram of the substrate in the double-sided encapsulation structure provided by the embodiment of the present application;

[0022] Figure 4 It is another schematic diagram of the preparation process of the double-sided encapsulation structure provided by the embodiment of the present application;

[0023] Figure 5 It is a third schematic diagram of the preparation process of the double-sided encapsulation structure provided by the embodiment of the present application;

[0024] Figure 6Schematic diagram IV of the preparation process of the double-sided packaging structure provided by the embodiment of the present application;

[0025] Figure 7 Schematic diagram V of the preparation process of the double-sided packaging structure provided by the embodiment of the present application;

[0026] Figure 8 Schematic diagram VI of the preparation process of the double-sided packaging structure provided by the embodiment of the present application.

[0027] Icons: 10 - Double-sided packaging structure; 11 - Substrate; 111 - First surface; 112 - Second surface; 113 - First pad; 114 - Signal pad; 12 - First electronic component; 13 - First encapsulation layer; 14 - First photoresist layer; 141 - First groove; 142 - Second groove; 15 - Second electronic component; 16 - Seed layer; 17 - Signal pin; 171 - First conductive layer; 172 - Second conductive layer; 173 - Conductive isolation layer; 18 - Second encapsulation layer; 19 - Second photoresist layer; 191 - Third groove. Detailed implementation manners

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Usually, the components of the embodiments of the present application described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0029] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application claimed, but merely represents selected embodiments of the present application. It should be noted that, without conflict, the various features in the embodiments of the present application can be combined with each other, and the combined embodiments are still within the protection scope of the present application.

[0030] It should be noted that: Similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0031] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of this application is customarily placed during use. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application. In addition, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0032] In addition, terms such as "horizontal" and "vertical" do not mean that the components are required to be absolutely horizontal or hanging vertically, but can be slightly inclined. For example, "horizontal" only means that its direction is more horizontal relative to "vertical", and does not mean that the structure must be completely horizontal, but can be slightly inclined.

[0033] In the description of the present application, it should also be noted that unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "couple" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0034] On the one hand of the embodiments of the present application, please refer to Figure 1 , a double-sided encapsulation structure 10 is provided, including: a substrate 11, and the substrate 11 has opposite first surface 111 and second surface 112. The substrate 11 can be a printed circuit board (PCB). One of the first surface 111 and the second surface 112 of the substrate 11 can be the front surface of the substrate 11, and the other can be the back surface of the substrate 11.

[0035] The first surface 111 of the substrate 11 is provided with a first electronic component 12 and a first encapsulation layer 13. The first electronic component 12 is electrically connected to the substrate 11, and the first encapsulation layer 13 wraps the first electronic component 12.

[0036] The number of the first electronic components 12 can be one, two, or more. The first electronic components 12 can include chips of wire bonding package type, chips of flip chip package type, and / or passive devices. The passive devices can be capacitors, resistors, or inductors. Exemplarily, a first surface 111 of the substrate 11 is provided with a first pad 113 and a second pad. The first pad 113 is used for connecting to a bonding wire of a chip of wire bonding package type, and the second pad is used for connecting to a bump on the surface of a chip of flip chip package type.

[0037] The first encapsulation layer 13 needs to wrap the side surfaces of the first electronic components 12. In one embodiment, the first encapsulation layer 13 can wrap the side surfaces of the first electronic components 12 and the surfaces of the first electronic components 12 facing away from the substrate 11. In another embodiment, the first encapsulation layer 13 can also wrap the side surfaces of the first electronic components 12 and expose the surfaces of the first electronic components 12 facing away from the substrate 11.

[0038] A second surface 112 of the substrate 11 is provided with a first photoresist layer 14. A first groove 141 and a second groove 142 are provided on the first photoresist layer 14. The first groove 141 exposes a part of the second surface 112, and the second groove 142 exposes a signal pad 114 on the second surface 112. A second electronic component 15 is provided on the second surface 112 exposed by the first groove 141. The second electronic component 15 is electrically connected to the substrate 11. A seed layer 16 is provided in the second groove 142. The seed layer 16 covers the signal pad 114 and the side walls of the second groove 142. A signal pin 17 is provided on a side of the seed layer 16 facing away from the signal pad 114. The signal pin 17 is electrically connected to the signal pad 114 through the seed layer 16. A second encapsulation layer 18 is provided on the first photoresist layer 14 and the second surface 112 exposed by the first groove 141. The second encapsulation layer 18 wraps the signal pin 17 and the second electronic component 15, and the signal pin 17 is exposed from the second encapsulation layer 18.

[0039] The first photoresist layer 14 is formed of photoresist. The first groove 141 and the second groove 142 thereon can be formed by exposing and developing the photoresist, or can be formed by other means.

[0040] The second electronic component 15 is provided on the second surface 112 exposed by the first groove 141. The number of the second electronic components 15 can be one, two, or more. The second electronic components 15 can include chips of wire bonding package type, chips of flip chip package type, and / or passive devices. The passive devices can be capacitors, resistors, or inductors. Exemplarily, a third pad is provided on the second surface 112 of the substrate 11. The third pad is used for connecting to a bump on the surface of a chip of flip chip package type.

[0041] The second surface 112 of the substrate 11 is also provided with signal pads 114, and the signal pads 114 can realize the input and / or output of signals. The position of the second groove 142 on the first photoresist layer 14 corresponds to the position of the signal pads 114 to expose the signal pads 114. A seed layer 16 and a signal pin 17 are sequentially arranged on the signal pads 114, and the seed layer 16 plays a connecting role to enable a stable electrical connection between the signal pads 114 and the signal pins 17.

[0042] The second encapsulation layer 18 needs to wrap the side surfaces of the second electronic component 15 and the signal pins 17, but the tops of the signal pins 17 need to be exposed from the second encapsulation layer 18 to realize the extraction of the signal pads 114. As for the surface of the second electronic component 15 facing away from the substrate 11, it can be wrapped by the second encapsulation layer 18 or exposed from the second encapsulation layer 18.

[0043] When preparing the above double-sided encapsulation structure 10, first, a first photoresist can be coated on the second surface 112 of the substrate 11, and through exposure and development operations, a first photoresist layer 14 with a second groove 142 is obtained to expose the signal pads 114 on the substrate 11. Then, a seed layer 16 is formed in the second groove 142, and the seed layer 16 is used to connect the signal pads 114 and the signal pins 17. After the seed layer 16 is prepared, please refer to Figure 2 , a second photoresist can be coated on the side of the seed layer 16 facing away from the substrate 11, and through exposure and development operations, a second photoresist layer 19 with a third groove 191 is obtained. The position of the third groove 191 corresponds to the position of the signal pads 114. Then, the signal pins 17 are directly formed in the third groove 191. After the signal pins 17 are formed, the second photoresist layer 19 is removed, and part of the seed layer 16 and the first photoresist layer 14 are removed to partially expose the second surface 112 of the substrate 11. The second electronic component 15 is installed on the exposed second surface 112. Finally, the signal pins 17 and the second electronic component 15 are encapsulated.

[0044] During the preparation process of the above double-sided encapsulation structure 10, the seed layer 16 and the signal pins 17 are first formed by using the first photoresist layer 14 and the second photoresist layer 19 respectively, and then the second photoresist layer 19 and part of the first photoresist layer 14 are removed, the second electronic component 15 is installed, and the signal pins 17 and the second electronic component 15 are encapsulated. When preparing the seed layer 16 and the signal pins 17, the grooves used are obtained by exposing and developing the photoresist, without involving grooving processing. Therefore, damage to the substrate 11 caused by over-deep grooving can be avoided.

[0045] Optionally, the signal pin 17 includes a first conductive layer 171 and a second conductive layer 172. The first conductive layer 171 is attached to the seed layer 16. The second conductive layer 172 is disposed on a side of the first conductive layer 171 facing away from the seed layer 16. The second encapsulation layer 18 wraps the first conductive layer 171, and the second conductive layer 172 is exposed from the second encapsulation layer 18.

[0046] The first conductive layer 171 is located within the second encapsulation layer 18, while the second conductive layer 172 protrudes from the second encapsulation layer 18. The provision of the first conductive layer 171 and the second conductive layer 172 can improve the reliability of the connection between the signal pin 17 and the signal pad 114.

[0047] It should be noted that the surface of the first conductive layer 171 facing away from the seed layer 16 can be flush with the surface of the second encapsulation layer 18 facing away from the substrate 11, can be located within the second encapsulation layer 18, or can be located outside the second encapsulation layer 18. The second conductive layer 172 can be completely located outside the second encapsulation layer 18, or can be partially located within the second encapsulation layer 18 and partially located outside the second encapsulation layer 18.

[0048] Optionally, the melting point of the second conductive layer 172 is lower than that of the first conductive layer 171.

[0049] With such a setting, when the signal pin 17 is welded to other devices, the second conductive layer 172 can be in a molten state while the first conductive layer 171 is in a solid state, thereby moderately maintaining the shape and hardness of the signal pin 17 and ensuring the welding reliability of the signal pin 17.

[0050] Optionally, the first conductive layer 171 is cylindrical and the second conductive layer 172 is spherical.

[0051] The cylindrical first conductive layer 171 is easy to process and maintain its shape and hardness. The spherical second conductive layer 172 can facilitate welding. For example, the first conductive layer 171 is prepared by an electroplating process, making the controllability of the height and width of the first conductive layer 171 stronger to adapt to chips with different heights and connection sites at different distances at the bottom of the substrate 11. The second conductive layer 172 is prepared by an electroplating process, and then the second conductive layer 172 is melted by a reflow soldering process, so that the second conductive layer 172 is spherical.

[0052] Optionally, the signal pin 17 further includes a conductive isolation layer 173. One side of the conductive isolation layer 173 is attached to the first conductive layer 171 and the other side is attached to the second conductive layer 172. The conductive isolation layer 173 is used to prevent the first conductive layer 171 and the second conductive layer 172 from diffusing into each other.

[0053] When the first conductive layer 171 and the second conductive layer 172 are made of different materials, diffusion is likely to occur at their joint surface, and then a brittle alloy is formed, making the signal pin 17 prone to cracking at the joint surface of the first conductive layer 171 and the second conductive layer 172. By providing the conductive isolation layer 173, mutual diffusion between the first conductive layer 171 and the second conductive layer 172 can be prevented without affecting the conductivity of the signal pin 17, thereby improving the reliability of the signal pin 17.

[0054] It can be understood that the conductive isolation layer 173 should not diffuse with the first conductive layer 171 and the second conductive layer 172 at the joint surface, or the alloy formed after diffusion is not easily cracked. Exemplarily, the material of the first conductive layer 171 is copper, the material of the second conductive layer 172 is tin, and the material of the conductive isolation layer 173 is nickel.

[0055] Optionally, the thickness of the conductive isolation layer 173 is respectively less than the thicknesses of the first conductive layer 171 and the second conductive layer 172.

[0056] The conductive isolation layer 173 is only used to isolate the first conductive layer 171 and the second conductive layer 172. Therefore, its thickness does not need to be too large, so as not to occupy the setting space of the first conductive layer 171 and also easily increase the cost.

[0057] Optionally, the surface of the conductive isolation layer 173 facing away from the substrate 11 is flush with the surface of the second electronic component 15 facing away from the substrate 11, so that the second conductive layer 172 is completely located outside the second encapsulation layer 18, facilitating the processing of the second conductive layer 172 and also being beneficial to improving the welding reliability between the signal pin 17 and other devices.

[0058] Optionally, the surface of the second encapsulation layer 18 facing away from the substrate 11 is flush with the surface of the second electronic component 15 facing away from the substrate 11.

[0059] The second encapsulation layer 18 exposes the surface of the second electronic component 15 facing away from the substrate 11, which is beneficial to the heat dissipation of the second electronic component 15.

[0060] A preparation method of the above double-sided packaging structure 10 is as follows:

[0061] S1: Refer to Figure 3 , provide the substrate 11, the substrate 11 has opposite first surface 111 and second surface 112, and the second surface 112 has a signal pad 114.

[0062] S2: Refer to Figure 4 , install the first electronic component 12 on the first surface 111 of the substrate 11, and encapsulate the first electronic component 12 to form the first encapsulation layer 13 that wraps the first electronic component 12.

[0063] S3: Refer toFigure 2 On the second surface 112 of the substrate 11, a first photoresist is coated, and an exposure and development operation is performed on the first photoresist to form a first photoresist layer 14 having a second groove 142.

[0064] S4: A titanium layer and a copper layer are sequentially sputtered on the first photoresist layer 14 to form a seed layer 16.

[0065] S5: A second photoresist is coated on the seed layer 16, and an exposure and development operation is performed on the second photoresist to form a second photoresist layer 19 having a third groove 191.

[0066] S6: A first conductive layer 171 is electroplated in the third groove 191.

[0067] S7: Refer to Figure 5 , remove the second photoresist layer 19, part of the first photoresist layer 14, and part of the seed layer 16.

[0068] S8: Refer to Figure 6 , install a second electronic component 15 on the second surface 112 of the substrate 11, and encapsulate the second electronic component 15 to form a second encapsulation layer 18 that wraps the second electronic component 15 and the first conductive layer 171.

[0069] S9: Refer to Figure 7 , grind the surface of the second encapsulation layer 18 facing away from the substrate 11 to make this surface flush with the surface of the second electronic component 15 facing away from the substrate 11.

[0070] S10: Refer to Figure 8 and Figure 1 , remove part of the first conductive layer 171, and electroplate a conductive isolation layer 173 on the side of the first conductive layer 171 facing away from the substrate 11.

[0071] S11: Electroplate a second conductive layer 172 on the side of the conductive isolation layer facing away from the substrate 11.

[0072] S12: Perform reflow soldering on the second conductive layer 172 to make it spherical.

[0073] This embodiment also provides an electronic device, including the double-sided encapsulation structure 10 as described in any one of the above.

[0074] This electronic device includes the same structure and beneficial effects as the double-sided encapsulation structure 10 in the foregoing embodiment. The structure and beneficial effects of the double-sided encapsulation structure 10 have been described in detail in the foregoing embodiment and will not be elaborated herein.

[0075] The above are only the preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A double-sided packaging structure, characterized in that: include: A substrate, the substrate having a first surface and a second surface opposite to each other, the first surface being provided with a first electronic component and a first plastic packaging layer, the first electronic component being electrically connected to the substrate, and the first plastic packaging layer wrapping the first electronic component; The second surface is provided with a first photoresist layer, and the first photoresist layer is provided with a first groove and a second groove, the first groove exposes a portion of the second surface, and the second groove exposes the signal pad on the second surface, a second electronic component is provided on the second surface exposed by the first groove, and the second electronic component is electrically connected to the substrate, a seed layer is provided in the second groove, the seed layer covers the signal pad and the side wall of the second groove, a signal pin is provided on the side of the seed layer away from the signal pad, and the signal pin is electrically connected to the signal pad through the seed layer, and a second plastic sealing layer is provided on the first photoresist layer and the second surface exposed by the first groove, the second plastic sealing layer wraps the signal pin and the second electronic component, and the signal pin is exposed from the second plastic sealing layer.

2. The double-sided packaging structure according to claim 1, characterized in that: The signal pin includes a first conductive layer and a second conductive layer, the first conductive layer is in contact with the seed layer, the second conductive layer is arranged on a side of the first conductive layer away from the seed layer, the second plastic packaging layer wraps the first conductive layer, and the second conductive layer is exposed from the second plastic packaging layer.

3. The double-sided packaging structure according to claim 2, characterized in that: The second conductive layer has a melting point lower than that of the first conductive layer.

4. The double-sided packaging structure according to claim 2, characterized in that: The signal pin further includes a conductive isolation layer, one side of the conductive isolation layer is in contact with the first conductive layer, and the other side of the conductive isolation layer is in contact with the second conductive layer. The conductive isolation layer is used to prevent the first conductive layer and the second conductive layer from diffusing into each other.

5. The double-sided packaging structure according to claim 4, characterized in that: The thickness of the conductive isolation layer is smaller than that of the first conductive layer and the second conductive layer.

6. The double-sided packaging structure according to claim 4, characterized in that: The material of the first conductive layer is copper, the material of the second conductive layer is tin, and the material of the conductive isolation layer is nickel.

7. The double-sided packaging structure according to claim 2, characterized in that: The first conductive layer is cylindrical, and the second conductive layer is spherical.

8. The double-sided packaging structure according to claim 1, characterized in that: A surface of the second plastic packaging layer facing away from the substrate is flush with a surface of the second electronic component facing away from the substrate.

9. The double-sided packaging structure according to claim 4, characterized in that: A surface of the conductive isolation layer facing away from the substrate is flush with a surface of the second electronic component facing away from the substrate.

10. An electronic device, characterized in that: It comprises the double-sided packaging structure as claimed in any one of claims 1 to 9.

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