Image acquisition board card and image acquisition device
By using FPGA chips for signal acquisition and image compression in the image acquisition products using the FPGA chip's hardware encoder for system-on-chip chip, the problem of signal transmission delay and distortion in the prior art is solved, and high-quality image acquisition and display are achieved.
Patent Information
- Application Number
- CN202421670119.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-15
- Publication Date
- 2025-06-20
- Estimated Expiration
- 2034-07-15
AI Technical Summary
Existing image acquisition products have large signal transmission delays and distortions during signal acquisition and compression, which affects the final display effect.
The signal acquisition process is realized through the FPGA chip, and the image compression is performed using the hardware encoder in the system-on-chip chip to ensure small signal transmission delay and lossless compression.
The entire process from acquisition to playback is achieved with very small delay and no signal distortion, which improves the quality of image acquisition and display.
Smart Images
Figure CN223007601U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of image acquisition, and particularly to an image acquisition board and an image acquisition device. Background Art
[0002] Currently, existing image acquisition products generally use Field Programmable Gate Array (FPGA) chips provided by foreign manufacturers to collect and compress image signals. There are certain signal transmission delays and distortions during the processing, which have an adverse effect on the final display effect. Utility Model Content
[0003] In view of this, the purpose of this application is to provide an image acquisition board and an image acquisition device. The signal acquisition process is realized through an FPGA chip, and the image compression is realized by using the hardware encoder in the system-on-chip. It can ensure a small signal transmission delay, achieve lossless compression, and make the delay of the entire process from acquisition to playback very small, and ensure that the signal is distortion-free. The specific solutions are as follows:
[0004] On the one hand, this application provides an image acquisition board, including:
[0005] A first connector, a decoder, an FPGA chip, a system-on-chip, and a second connector connected in sequence; the system-on-chip includes an encoder;
[0006] The first connector is used to receive a first image signal, the decoder is used to decode the first image signal to obtain a second image signal, the FPGA chip is used to collect the second image signal, the encoder is used to compress and process the second image signal to obtain a third image signal, and the second connector is used to output the third image signal.
[0007] In a possible implementation, the decoder and the FPGA chip are connected through a target interface; the target interface is an Ethernet interface, a fiber optic interface, a PCIE interface, or a USB interface.
[0008] In a possible implementation, the image acquisition board further includes:
[0009] A third connector connected to the system-on-chip.
[0010] In a possible implementation, the third connector and the system-on-chip are connected through a display interface; the display interface is an HDMI interface, a DP interface, or a VGA interface.
[0011] In a possible implementation, the decoder is an Advanced Digital Video Transport (AVT) decoder.
[0012] In a possible implementation, the first connector is connected to the AVT decoder through a Serial Digital Interface.
[0013] In a possible implementation, the FPGA chip is connected to the System on Chip (SoC) through a target interface; the target interface is an Ethernet interface, a fiber optic interface, a PCIe interface, or a USB interface.
[0014] In a possible implementation, the second connector is connected to the System on Chip (SoC) through a target interface; the target interface is an Ethernet interface, a fiber optic interface, a PCIe interface, or a USB interface.
[0015] In another aspect, an embodiment of the present application further provides an image acquisition device, including:
[0016] The image acquisition board;
[0017] A camera connected to the first connector, configured to acquire the first image signal.
[0018] In a possible implementation, the camera is a multi-channel AVT camera.
[0019] An embodiment of the present application provides an image acquisition board and an image acquisition device. The image acquisition board includes a first connector, a decoder, an FPGA chip, a System on Chip (SoC), and a second connector connected in sequence; the System on Chip (SoC) includes an encoder; the first connector is configured to receive a first image signal, the decoder is configured to decode the first image signal to obtain a second image signal, the FPGA chip is configured to acquire the second image signal, the encoder is configured to perform compression processing on the second image signal to obtain a third image signal, and the second connector is configured to output the third image signal. In this way, the signal acquisition process is implemented through the FPGA chip, and the image compression is implemented using the hardware encoder in the System on Chip (SoC), which can ensure a small signal transmission delay, achieve lossless compression, and make the delay of the entire process from acquisition to playback very small, and ensure that the signal is distortion-free. Description of the Drawings
[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0021] Figure 1Shows a schematic diagram of an image acquisition board provided by an embodiment of the present application;
[0022] Figure 2 Shows a schematic diagram of an image acquisition device provided by an embodiment of the present application. Detailed implementation manners
[0023] To make the above objects, features, and advantages of the present application more obvious and understandable, the following will describe the detailed implementation manners of the present application with reference to the accompanying drawings.
[0024] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar generalizations without departing from the connotation of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.
[0025] For ease of understanding, the following will describe in detail an image acquisition board and an image acquisition device provided by an embodiment of the present application with reference to the accompanying drawings.
[0026] Refer to Figure 1 As shown, it is a schematic diagram of an image acquisition board provided by an embodiment of the present application. The image acquisition board may include a first connector 101, a decoder 102, an FPGA chip 103, a system-on-chip (SOC) 104, and a second connector 105 that are connected in sequence.
[0027] Specifically, the first connector 101 is connected to the decoder 102, the decoder 102 is connected to the FPGA chip 103, the FPGA chip 103 is connected to the SOC chip 104, and the SOC chip 104 is connected to the second connector 105. The first connector 101 can be used to receive a first image signal from the outside. The first image signal can be a signal obtained by collecting an image or a video. The decoder 102 can be used to decode the first image signal to obtain a second image signal. The signal formats of the first image signal and the second image signal change, but the data content carried by the signals remains unchanged. The signal format of the second image signal conforms to the signal format of the FPGA chip 103, for example, it can be a parallel format.
[0028] The FPGA chip 103 can be used to collect the second image signal, that is, to receive the signal transmitted by the decoder 102. When collecting signals, the FPGA chip 103 can achieve multi-channel parallel collection, with a fast collection rate and small delay. The system-on-chip can include an encoder. As a hardware encoder, it can be used to compress the second image signal to obtain the third image signal. Among them, the compression process can be performed according to the video compression format of H.264 or H.265 to realize the compression process of the image or video. The second connector 105 can be connected to other external electronic components and can be used to output the third image signal.
[0029] In this way, by using the FPGA chip 103 to implement the signal collection process and the hardware encoder in the system-on-chip to implement image compression, it is possible to ensure a small signal transmission delay, achieve lossless compression, and make the delay of the entire process from collection to playback very small, and ensure that the signal is distortion-free.
[0030] In a possible implementation manner, the decoder 102 and the FPGA chip 103 can be connected through a target interface; the target interface is an Ethernet interface, an optical fiber interface, a Peripheral Component Interconnect Express (PCIE) interface, or a Universal Serial Bus (USB) interface.
[0031] Specifically, the target interface can be used as a high-speed channel. That is, signals are transmitted between the decoder 102 and the FPGA chip 103 through the high-speed channel, which can improve the collection rate and transmission rate, thereby achieving low delay. In addition, the type of the communication protocol of the target interface is not specifically limited here. The high-speed channel can be connected to any other electronic device. For example, signals can be transmitted to a switch through a high-speed channel such as a 10 Gigabit Ethernet.
[0032] In a possible implementation manner, the FPGA chip 103 and the system-on-chip 104 are connected through a target interface; the target interface is an Ethernet interface, an optical fiber interface, a PCIE interface, or a USB interface. That is, the SOC chip 104 can provide an external high-speed channel for signal transmission. Signals can be transmitted between the FPGA chip 103 and the SOC chip 104 through the high-speed channel, which can improve the collection rate and transmission rate, thereby achieving low delay.
[0033] In a possible implementation, the second connector 105 is connected to the system-on-chip 104 through a target interface; the target interface is an Ethernet interface, a fiber optic interface, a PCIE interface, or a USB interface, that is, signals can be transmitted between the second connector 105 and the SOC chip 104 through a high-speed channel, which can improve the acquisition rate and transmission rate, thereby achieving low latency.
[0034] In a possible implementation, the image acquisition board may further include a third connector 106 connected to the system-on-chip, and the third connector 106 can be used to connect to external electronic components to output signals.
[0035] In a possible implementation, the third connector 106 is connected to the system-on-chip through a display interface; the display interface is an HDMI interface, a DP interface, or a VGA interface, thereby realizing image display. Specifically, the third image signal can be transmitted to an external display device through the display interface and the third connector 106, for example, it can be transmitted to a display screen, thereby realizing the display and playback of images or videos.
[0036] In a possible implementation, the decoder 102 can be an Advanced Video Transport (AVT) decoder 102, and the AVT decoder 102 can convert a Serial Digital Interface (SDI) signal into a signal of other formats.
[0037] In a possible implementation, the first connector 101 is connected to the AVT decoder 102 through a serial digital interface, so that the first image signal in SDI format can be smoothly transmitted.
[0038] The embodiment of the present application provides an image acquisition board. The image acquisition board includes a first connector, a decoder, an FPGA chip, a system-on-chip, and a second connector connected in sequence; the system-on-chip includes an encoder; the first connector is used to receive a first image signal, the decoder is used to decode the first image signal to obtain a second image signal, the FPGA chip is used to acquire the second image signal, the encoder is used to compress the second image signal to obtain a third image signal, and the second connector is used to output the third image signal. In this way, the signal acquisition process is realized through the FPGA chip, and the image compression is realized by using the hardware encoder in the system-on-chip, which can ensure a small signal transmission delay, realize lossless compression, and realize that the delay of the entire process from acquisition to playback is very small, and ensure that the signal is distortion-free.
[0039] Based on the above image acquisition board, the embodiment of the present application further provides an image acquisition device, refer to Figure 2As shown in the figure, it is a schematic diagram of an image acquisition device provided by an embodiment of the present application. The device may include an image acquisition board, and a camera 107 connected to a first connector 101. The camera 107 can be used for shooting to acquire a first image signal.
[0040] In a possible implementation, the camera 107 can be a multi-channel AVT camera, so as to achieve multi-channel signal transmission, improve signal transmission efficiency, and then the FPGA chip 103 can collect the signals transmitted by the multi-channel AVT camera.
[0041] An embodiment of the present application provides an image acquisition device. The image acquisition device includes an image acquisition board, and a camera connected to a first connector. The camera can be used to acquire a first image signal. The image acquisition board includes a first connector, a decoder, an FPGA chip, a system-on-chip, and a second connector connected in sequence; the system-on-chip includes an encoder; the first connector is used to receive the first image signal, the decoder is used to decode the first image signal to obtain a second image signal, the FPGA chip is used to collect the second image signal, the encoder is used to compress the second image signal to obtain a third image signal, and the second connector is used to output the third image signal. By using the FPGA chip to implement the signal acquisition process and using the hardware encoder in the system-on-chip to implement image compression, it is possible to ensure a small signal transmission delay, achieve lossless compression, and make the delay of the entire process from acquisition to playback very small, and ensure that the signal is distortion-free.
[0042] Each embodiment in this specification is described in a progressive manner. The same or similar parts among the embodiments can be referred to each other, and the key points of each embodiment are the differences from other embodiments. In particular, for the embodiment of the image acquisition device, since it is basically similar to the embodiment of the image acquisition board, the description is relatively simple, and the relevant parts can be referred to the partial description of the embodiment of the image acquisition board.
[0043] The above are only the preferred embodiments of the present application. Although the present application has been disclosed above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make many possible changes and modifications to the technical solution of the present application, or modify it into an equivalent embodiment with equivalent changes, without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of the protection of the technical solution of the present application.
Claims
1. An image acquisition board, characterized in that: include: A first connector, a decoder, an FPGA chip, a system-on-chip chip, and a second connector connected in sequence; The system-on-chip chip includes an encoder; The first connector is used to receive a first image signal, the decoder is used to decode the first image signal to obtain a second image signal, the FPGA chip is used to collect the second image signal, the encoder is used to compress the second image signal to obtain a third image signal, and the second connector is used to output the third image signal.
2. The image acquisition board according to claim 1, characterized in that: The decoder is connected to the FPGA chip via a target interface; the target interface is an Ethernet interface, an optical fiber interface, a PCIE interface or a USB interface.
3. The image acquisition board according to claim 1, characterized in that: The image acquisition board also includes: A third connector connected to the system-on-chip chip.
4. The image acquisition board according to claim 3, characterized in that: The third connector is connected to the system-on-chip chip via a display interface; the display interface is an HDMI interface, a DP interface or a VGA interface.
5. The image acquisition board according to claim 1, characterized in that: The decoder is an Advanced Video Transport (AVT) decoder.
6. The image acquisition board according to claim 5, characterized in that: The first connector is connected to the AVT decoder via a serial digital interface.
7. The image acquisition board according to claim 1, characterized in that: The FPGA chip is connected to the system-on-chip chip via a target interface; the target interface is an Ethernet interface, a fiber optic interface, a PCIE interface or a USB interface.
8. The image acquisition board according to claim 1, characterized in that: The second connector is connected to the system-on-chip chip via a target interface; the target interface is an Ethernet interface, a fiber optic interface, a PCIE interface or a USB interface.
9. An image acquisition device, characterized in that: include: The image acquisition board as described in any one of claims 1 to 8; The camera connected to the first connector is used to collect the first image signal.
10. The image acquisition device according to claim 9, characterized in that: The camera is a multi-channel AVT camera.