Power semiconductor device

Abstract

The utility model relates to a power semiconductor device, in particular to a power semiconductor device, an upper P-type cover layer and a lower P-type cover layer are designed, the high doping concentration of the first P-type cover layer at the lower layer ensures that the threshold voltage of the device can reach a higher value, and the opportunity that an enhanced device is mistakenly opened is reduced; the doping concentration of the upper second P-type cover layer decreases progressively from bottom to top in the vertical direction and decreases progressively from the middle to the left edge and the right edge in the horizontal direction, the doping concentration of the surface corner position is low, when the grid electrode is pressed in the forward direction, the depletion region of the surface corner is deep, the formed peak electric field is low, the design reduces the leakage current of the grid electrode, and the reliability of the grid electrode is improved. And the breakdown voltage and the reliability of the gate are improved.

Description

Technical Field

[0001] The utility model relates to power semiconductor devices, especially power gallium nitride devices. Background Art

[0002] Compared with silicon materials, gallium nitride materials have a larger band gap, higher electron mobility, saturation electron velocity and breakdown electric field. Gallium nitride high electron mobility transistors are common power devices and are widely used in high-frequency application fields such as radio frequency and microwave.

[0003] A conventional gallium nitride high electron mobility transistor structure is as Figure 1 shown. The device shown is provided with a buffer layer above the substrate layer, a channel layer above the buffer layer, a barrier layer above the channel layer, a conventional P-type cap layer 104 above the barrier layer, and a gate metal layer 107 above the conventional P-type cap layer 104. A heterojunction is formed between the channel layer and the barrier layer, and a two-dimensional electron gas (2DEG) is formed on the surface of the channel layer below the heterojunction. A main function of the conventional P-type cap layer 104 is to form a Schottky contact with the upper gate metal layer 107 to reduce the gate current when the gate is forward biased. Another main function of the conventional P-type cap layer 104 is to deplete the two-dimensional electron gas located below the conventional P-type cap layer 104 to form an enhancement-mode device. In order to reduce the chance of the enhancement-mode device being accidentally turned on, the threshold voltage needs to reach a sufficiently high value. In order to achieve a higher threshold voltage, the conventional P-type cap layer 104 generally requires a higher doping concentration to enhance the ability to deplete the two-dimensional electron gas below it. However, the depletion region in the conventional P-type cap layer 104 with a higher doping concentration is shallower when the gate is forward biased, and a peak electric field will be formed at the corner position 110 on the surface of the conventional P-type cap layer 104, resulting in a higher gate leakage current and a lower breakdown voltage of the device, affecting the performance and reliability of the device. Summary of the Utility Model

[0004] To solve the above-mentioned problems, the present utility model provides a power semiconductor device. The device includes a substrate layer at the bottom, a buffer layer above the substrate layer, a channel layer above the buffer layer, a barrier layer above the channel layer, and a first P-type capping layer above the barrier layer. Above the first P-type capping layer, there are also a diffusion barrier layer at the edge part and a second P-type capping layer at the middle part. The second P-type capping layer includes a second P-type middle capping layer above the first P-type capping layer and second P-type side capping layers extending to both sides to cover the diffusion barrier layer. Above the second P-type capping layer, there are a gate metal layer, a source metal layer on one side of the gate metal layer, and a drain metal layer on the other side. The second P-type capping layer forms a Schottky contact with the gate metal layer. The channel layer and the barrier layer form a heterojunction, and a two-dimensional electron gas is formed on the surface of the channel layer below the heterojunction. The doping concentration range of the first P-type capping layer is 1x10 16 –1x10 21 cm -3 , and the second P-type capping layer is formed by the diffusion of the doping material of the first P-type capping layer. The doping concentration decreases from bottom to top in the vertical direction and decreases from the middle to both side edges in the horizontal direction.

[0005] Further, by increasing the width of the diffusion barrier layer, an undoped region is formed above the diffusion barrier layer and outside the second P-type side capping layers.

[0006] Further, by adjusting the width of the diffusion barrier layer on one side of the source metal layer and the width of the diffusion barrier layer on the other side of the drain metal layer, the peak electric field formed at the first surface corner position and the second surface corner position when the gate is forward biased is adjusted.

[0007] Further, the width of the diffusion barrier layer on one side of the source metal layer is greater than the width of the diffusion barrier layer on the other side of the drain metal layer.

[0008] The P-type capping layer of the present utility model has two layers. The high doping concentration of the lower first P-type capping layer ensures that the threshold voltage of the device can reach a relatively high value, reducing the chance of the enhancement-type device being accidentally turned on. The doping concentration of the upper second P-type capping layer decreases from bottom to top in the vertical direction and decreases from the middle to the left and right edges in the horizontal direction. Therefore, the doping concentration at the surface corner positions of the upper second P-type capping layer is relatively low. When the gate is forward biased, the depletion region at the surface corners of the upper second P-type capping layer is deeper, and the formed peak electric field will be lower. This design reduces the gate leakage current and improves the gate breakdown voltage and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a schematic cross-sectional view of an existing high electron mobility transistor structure.

[0010] Figures 2 - 3 This is a schematic cross-sectional view of the device structure according to an embodiment of the present invention.

[0011] Figures 4 - 6 This is a schematic cross-sectional view of the device structure according to another embodiment of the present invention.

[0012] Figures 7 - 13 This is a schematic cross-sectional view of the manufacturing method of the device structure according to another embodiment of the present invention. Detailed implementation manners

[0013] The present invention will be described in detail below with reference to the accompanying drawings and embodiments. It should be noted that the corresponding position words such as "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", and "vertical" described in this document are relative positions corresponding to the reference drawings. The specific implementation does not limit the fixed direction. The devices in the drawings are not necessarily drawn to scale. The straight lines shown at the boundaries of the doped regions and trenches in the drawings, and the sharp corners formed by the boundaries, are generally not straight lines and precise angles in actual applications.

[0014] Refer to Figure 2 This is a schematic cross-sectional view of the device structure according to the first embodiment of the present invention, and the structure includes:

[0015] A substrate layer 200 located at the bottom;

[0016] A buffer layer 201 located above the substrate layer 200;

[0017] A channel layer 202 located above the buffer layer 201;

[0018] A barrier layer 203 located above the channel layer 202;

[0019] A first P-type capping layer 204 located above the barrier layer 203;

[0020] A diffusion barrier layer 205 and a second P-type capping layer 206 located above the first P-type capping layer 204;

[0021] The second P-type capping layer 206 includes a second P-type capping layer middle part 206a only located above the first P-type capping layer 204 and second P-type capping layer side parts 206b located above the diffusion barrier layer 205, and the second P-type capping layer 206 formed by combining the second P-type capping layer middle part 206a and the second P-type capping layer side parts 206b;

[0022] A gate metal layer 107 located above the second P-type capping layer 206;

[0023] A source metal layer 208 located to the left of the gate metal layer 107 and a drain metal layer 209 located to the right of the gate metal layer 107;

[0024] In the above structure, the channel layer 202 and the barrier layer 203 form a heterojunction, and a two-dimensional electron gas (2DEG) is formed on the surface of the channel layer 202 below the heterojunction, forming a current channel between the source metal layer 208 and the drain metal layer 209 when the device is turned on.

[0025] In the above structure, the first P-type capping layer 204 depletes the two-dimensional electron gas on the surface of the channel layer 202 below it when the device is turned off, forming an enhancement-mode device.

[0026] In the above structure, the second P-type capping layer 206 forms a Schottky contact with the gate metal layer 107 above it, reducing the gate current when the gate is forward-biased.

[0027] In the above structure, the doping material of the first P-type capping layer 204 includes magnesium (Mg) or other suitable P-type doping elements, and the doping concentration ranges from 1x10 16 –1x10 21 cm -3 . The second P-type capping layer 206 is an unintentionally doped layer, and its doping material is formed by the diffusion of the doping material of the first P-type capping layer 204. Therefore, the doping concentration of the second P-type capping layer 206 is lower than that of the first P-type capping layer 204.

[0028] In the above structure, the diffusion barrier layer 205 blocks the direct upward diffusion of the doping material of the first P-type capping layer 204 in the vertical direction (y) to the two side portions 206b of the second P-type capping layer. The doping material of the first P-type capping layer 204 needs to first diffuse upward in the vertical direction (y) to the middle portion 206a of the second P-type capping layer, and then diffuse horizontally from the middle to the left and right to the two side portions 206b of the second P-type capping layer. The material of the diffusion barrier layer 205 may include one or a combination of materials such as boron nitride (BN), aluminum boron nitride (AlBN), gallium boron nitride (GaBN), indium boron nitride (InBN), or other suitable materials.

[0029] In the above structure, the doping concentration of the second P-type capping layer decreases from bottom to top in the vertical direction (y) and from the middle to the left and right edges in the horizontal direction (x). Therefore, as Figure 3 shown, the surface corner position 110 of the second P-type capping layer is the position with the lowest doping concentration of the entire second P-type capping layer. When the gate is forward-biased, the depletion region at the surface corner position 110 of the second P-type capping layer will be deeper, and the peak electric field formed will be lower.

[0030] In the above structure, the side walls of the first P-type capping layer 204 and the second P-type capping layer 206 are formed by etching, and there are many defects on the wall-through surface. The peak electric field at the surface corner position 110 of the second P-type capping layer is low, reducing the gate leakage current and improving the gate breakdown voltage and reliability.

[0031] Embodiment 2

[0032] A variant device embodiment of the present utility model is as Figure 4 shown, and Figure 2 the difference from the embodiment is that the width of the diffusion barrier layer 205 is larger, and the second P-type capping layer 206 is composed of a middle part 206a, two side parts 206b and two outer side parts. The two outer side parts of the second P-type capping layer are undoped regions 206c.

[0033] In the above structure, increasing the width of the diffusion barrier layer 205 can prevent the doping material of the first P-type capping layer 204 from diffusing horizontally from the middle to the left and right to the side walls of the second P-type capping layer, thereby forming the undoped regions 206c of the two outer side parts of the second P-type capping layer, and further reducing the peak electric field formed at the surface corner position of the second P-type capping layer when the gate is under positive pressure.

[0034] Embodiment 3

[0035] A variant device embodiment of the present utility model is as Figure 5 shown, and Figure 2 the difference from the embodiment is that the width (x1) of the diffusion barrier layer 205 near the source metal layer 208 is not the same as the width (x2) of the diffusion barrier layer 205 near the drain metal layer 209 (x1≠x2), as shown in 5.

[0036] In the above structure, different widths (x1) of the diffusion barrier layer 205 near the source metal layer 208 and widths (x2) of the diffusion barrier layer 205 near the drain metal layer 209 can be used to respectively adjust the peak electric fields formed at the first surface corner position 211 of the second P-type capping layer near the source metal layer 208 and the second surface corner position 212 of the second P-type capping layer near the drain metal layer 209 when the gate is under positive pressure, as Figure 6 shown.

[0037] In the above structure, the width (x2) of the diffusion barrier layer 205 near the drain metal layer 209 can be greater than the width (x1) of the diffusion barrier layer 205 near the source metal layer 208, such that the doping concentration at the surface corner position 212 of the second P-type capping layer near the drain metal layer 209 is lower than the doping concentration at the surface corner position 211 of the second P-type capping layer near the source metal layer 208. When the gate is forward biased, the depletion region at the surface corner position 212 of the second P-type capping layer near the drain metal layer 209 will be deeper, the peak electric field formed will be lower, and there will be fewer gate defects. Therefore, the drain-gate leakage current of the device is reduced, and the reliability performance of the device under high-temperature reverse bias (HTRB) is improved.

[0038] Those skilled in the art should know that the structural features mentioned in each of the above-described embodiments of the present utility model can be combined with each other to form more device structures of the embodiments of the present utility model.

[0039] Embodiment 4

[0040] According to the structural features of the above-described embodiments of the present utility model and in combination with the existing manufacturing process of gallium nitride high electron mobility transistors, various formation methods of the device embodiments of the present utility model can be obtained. An exemplary formation method of the device embodiment of the present utility model is as Figures 5 - 13 shown:

[0041] In the first step, a buffer layer 201 is formed on the substrate layer 200, then a channel layer 202 is formed on the buffer layer 201, and then a barrier layer 203 is formed on the channel layer 202, as Figure 7 shown.

[0042] The material of the substrate layer 200 is usually silicon (Si), and may also be other suitable materials such as gallium nitride (GaN), silicon carbide (SiC), sapphire, etc.

[0043] The buffer layer 201 may comprise one material or a combination of multiple materials such as aluminum gallium nitride (AlGaN), aluminum nitride (AlN), gallium nitride (GaN), etc. The one material or the combination of multiple materials may contain doping elements such as carbon (C), iron (Fe), etc., which is beneficial to reducing crystal layer misalignment and leakage current.

[0044] The material of the channel layer 202 is usually gallium nitride (GaN), and may also be other materials, and its energy band gap is smaller than the energy band gap of the material of the barrier layer 203 located above it.

[0045] The material of the barrier layer 203 is usually aluminum gallium nitride (AlGaN), and may also be other materials, and its energy band gap is greater than the energy band gap of the material of the channel layer 202 located below it.

[0046] The above structure can be formed by processes such as chemical vapor deposition, physical vapor deposition, and epitaxial growth.

[0047] In the second step, a preliminary first P-type capping layer 294 is formed above the barrier layer 203, and then a preliminary diffusion barrier layer 295 is formed above the preliminary first P-type capping layer 294, as Figure 8 shown.

[0048] The material of the preliminary first P-type capping layer 294 is usually doped gallium nitride (GaN), and may also be doped aluminum gallium nitride (AlGaN) or other materials. The doping material contains magnesium (Mg) or other suitable P-type doping elements.

[0049] The material of the preliminary diffusion barrier layer 295 may include one or a combination of materials such as boron nitride (BN), aluminum boron nitride (AlBN), gallium boron nitride (GaBN), indium boron nitride (InBN), or other suitable materials.

[0050] The above structure can be formed by processes such as chemical vapor deposition, physical vapor deposition, and epitaxial growth.

[0051] In the third step, processes such as photolithography, dry etching, and wet etching are performed on the surface of the preliminary diffusion barrier layer 295 to form a patterned two-step diffusion barrier layer 285, as Figure 9 shown.

[0052] In the fourth step, a preliminary second P-type capping layer 296 is formed on the surface of the two-step diffusion barrier layer 285, as Figure 10 shown. The preliminary second P-type capping layer 296 is an unintentionally doped layer, and its doping material is formed by the diffusion of the doping material of the preliminary first P-type capping layer 294 during the formation of the preliminary second P-type capping layer 296. Since the two-step diffusion barrier layer 285 blocks the doping material of the preliminary first P-type capping layer 294 from directly diffusing vertically from bottom to top to the two side portions 296b of the preliminary second P-type capping layer, the doping material of the preliminary first P-type capping layer 294 needs to first diffuse vertically from bottom to top to the middle portion 206a of the second P-type capping layer, and then diffuse horizontally from the middle to the left and right to the two side portions 296b of the preliminary second P-type capping layer. The two outer side portions 296c of the preliminary second P-type capping layer are undoped regions.

[0053] It is also possible to increase the width of the two-step diffusion barrier layer 285, reduce the width of the middle portion 206a of the second P-type capping layer, and increase the width of the undoped regions of the two outer side portions 296c of the preliminary second P-type capping layer.

[0054] The above structure can be formed by processes such as chemical vapor deposition, physical vapor deposition, and epitaxial growth.

[0055] In the fifth step, a preliminary gate metal layer 197 is formed on the surface of the preliminary second P-type capping layer 296, as Figure 11 shown.

[0056] The preliminary gate metal layer 197 may be formed by processes such as evaporation plating, sputtering, etc., and its constituent materials may include but are not limited to metals such as titanium (Ti), nickel (Ni), tungsten (W), aluminum (Al), copper (Cu), platinum (Pt), gold (Au), their alloys, their compounds, or other suitable materials.

[0057] Generally, the preliminary gate metal layer 197 forms a Schottky contact with the preliminary second P-type capping layer 296 located below it.

[0058] In the sixth step, processes such as photolithography, dry etching, and wet etching are performed on the preliminary gate metal layer 197, the two side portions 296b of the preliminary second P-type capping layer, the preliminary first P-type capping layer 294, and the two-step diffusion barrier layer 285 to respectively form a patterned gate metal layer 107, patterned two side portions 206b of the second P-type capping layer, a patterned diffusion barrier layer 205, and a patterned first P-type capping layer 204, as Figure 12 shown.

[0059] The second P-type capping layer 206 is composed of the middle portion 206a and the two side portions 206b of the second P-type capping layer.

[0060] In the seventh step, a source metal layer 208 is formed to the left of the gate metal layer 107 and a drain metal layer 209 is formed to the right of the gate metal layer 107, as Figure 13 shown.

[0061] The source metal layer 208 and the drain metal layer 209 may be formed by processes such as evaporation plating, sputtering, etc., and its constituent materials may include but are not limited to metals such as titanium (Ti), nickel (Ni), tungsten (W), aluminum (Al), copper (Cu), platinum (Pt), gold (Au), their alloys, their compounds, or other suitable materials.

[0062] The method of forming the patterned source metal layer 208 and the drain metal layer 209 may include process steps such as photolithography, dry etching, and wet etching.

[0063] Generally, the source metal layer 208 and the drain metal layer 209 form an ohmic contact with the channel layer 202 located below them.

[0064] Those skilled in the art should know that the above manufacturing steps only list the key steps and do not show the complete steps of forming the device. The specific detailed manufacturing steps can be obtained according to the common manufacturing process steps and general knowledge in the art and can be appropriately increased, decreased, and changed.

Claims

1. A power semiconductor device, comprising a substrate layer at the bottom, a buffer layer above the substrate layer, a channel layer above the buffer layer, a barrier layer above the channel layer, and a first P-type cap layer above the barrier layer; characterized in that: A diffusion barrier layer located at the edge portion and a second P-type cap layer located in the middle portion are also provided above the first P-type cap layer. The second P-type cap layer includes a second P-type middle cap layer located above the first P-type cap layer and a second P-type two-side cap layer extending to both sides and covering the diffusion barrier layer. A gate metal layer, a source metal layer located on one side of the gate metal layer and a drain metal layer on the other side are provided above the second P-type cap layer. The second P-type cap layer forms a Schottky contact with the gate metal layer. The channel layer and the barrier layer form a heterojunction, and a two-dimensional electron gas is formed on the surface of the channel layer below the heterojunction. The doping concentration of the second P-type cap layer decreases from bottom to top in the vertical direction and decreases from the middle to both side edges in the horizontal direction.

2. The power semiconductor device according to claim 1, characterized in that: The width of the diffusion barrier layer is wider, and undoped regions are provided above the widened diffusion barrier layer and outside the second P-type two-side cap layers.

3. The power semiconductor device according to claim 1, characterized in that: The width of the diffusion barrier layer on one side of the source metal layer is greater than the width of the diffusion barrier layer on the other side of the drain metal layer.

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