Image sensing integrated circuit device

Abstract

The embodiment of the utility model relates to an image sensing integrated circuit device. A process for forming a first deep trench isolation (DTI) structure in the pixel region of the semiconductor substrate is also used to form a second DTI structure in the guard ring region that isolates the pixel region from the surrounding region. The guard ring region may have a PNP guard ring structure. The second DTI structure may include a trench in each of an inner ring, a middle ring, and an outer ring of the PNP guard ring structure. The first and second DTI structures may have conductive cores. The conductive cores of the inner and outer rings may be biased to a first voltage, while the conductive core of the middle ring may be biased to a second voltage of opposite polarity. When the second DTI structure has a conductive core with these biases, the second DTI structure can be used as a guard ring without a PNP structure.

Description

Technical Field

[0001] An embodiment of the present utility model relates to an image sensing integrated circuit device. Background Art

[0002] Integrated circuits (ICs) incorporating image sensors are widely used in modern electronic devices such as cameras and mobile phones. In recent years, complementary metal oxide semiconductor (CMOS) image sensors have begun to be widely used, largely replacing charge-coupled device (CCD) image sensors. Compared with CCD image sensors, CMOS image sensors are increasingly favored due to their low power consumption, small size, fast data processing speed, direct data output, and low manufacturing cost. Types of CMOS image sensors include front side illuminated (FSI) image sensors and back side illuminated (BSI) image sensors. Summary of the Utility Model

[0003] An image sensing integrated circuit device includes a substrate having a pixel region, a peripheral region, and a guard ring region. The guard ring region is located between the pixel region and the peripheral region. Photo-sensing elements are formed in an array in the pixel region. A first backside deep trench isolation structure extends between the photo-sensing elements. A second backside deep trench isolation structure is in the guard ring region. The second backside deep trench isolation structure is separated from the first backside deep trench isolation structure.

[0004] An image sensing integrated circuit device includes a substrate having a pixel region, a peripheral region, and a guard ring region. The guard ring region is located between the pixel region and the peripheral region. Photo-sensing elements are arranged in the pixel region. First sidewalls of the substrate are formed on opposite sides of the photo-sensing elements and extend from the backside into one or more first trenches within the substrate. Second sidewalls of the substrate are formed in the guard ring region and extend from the backside into one or more second trenches within the substrate. The one or more second trenches laterally separate the pixel region from the peripheral region. Brief Description of the Drawings

[0005] Aspects of the present utility model will be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0006] Figure 1A A cross-sectional side view of an image sensing integrated circuit (IC) device according to some embodiments is shown.

[0007] Figure 1B A top-down sectional view of an image sensing IC device according to some embodiments is shown.

[0008] Figure 1C Shows a top cross-sectional view of an image sensing IC device according to some embodiments.

[0009] Figures 2 to 8 Shows a cross-sectional side view of an image sensing IC device according to various embodiments.

[0010] Figures 9 to 26 Is a series of cross-sectional views showing some embodiments of a method that can be used to form an image sensing IC device (such as Figure 1A the image sensing IC device).

[0011] Figures 27 to 35 Is a series of cross-sectional views showing some embodiments of a method that can be used to form an image sensing IC device (such as Figure 4 the image sensing IC device).

[0012] Figures 36 to 39 Is a series of cross-sectional views showing some embodiments of a method that can be used to form an image sensing IC device (such as Figure 5 the image sensing IC device).

[0013] Figures 40 to 42 Is a series of cross-sectional views showing some embodiments of a method that can be used to form an image sensing IC device (such as Figure 6 the image sensing IC device).

[0014] Figures 43 to 45 Is a series of cross-sectional views showing some embodiments of a method that can be used to form an image sensing IC device (such as Figure 8 the image sensing IC device).

[0015] Figure 46 Provides a flowchart showing some embodiments of a method for forming an image sensing IC device according to the present utility model. Detailed Description

[0016] The following disclosure provides several different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present utility model. Of course, these are merely examples and not restrictive. For example, the formation of the first feature above or on top of the second feature in the following description can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features can be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present utility model may repeat reference numerals or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself prescribe a relationship between the various embodiments or architectures being discussed.

[0017] In addition, for ease of description, spatial relative terms may be used herein, such as "below", "beneath", "under", "above", "over", and the like, to describe the relationship of one element or feature to another element or feature as shown in the figures. In addition to the orientation shown in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or at other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0018] Many electronic devices (e.g., cameras, mobile phones, computers, etc.) include an image sensing IC device having an array of light sensing elements configured to capture images. When exposed to light, the light sensing elements generate electron-hole pairs. An electric field generated by a diode or the like separates the charges so that these charges can be accumulated and detected. An isolation structure (e.g., a deep trench isolation structure) laterally surrounds the light sensing elements to separate signals from different light sensing elements. The isolation structure includes an insulating material disposed in a trench defined by the sidewalls of a semiconductor substrate.

[0019] When fabricating the isolation structure, the semiconductor substrate may be etched to form trenches. These trenches are then filled or lined with one or more dielectric materials. The etching process used to form the trenches may damage the semiconductor substrate, resulting in defects (such as dangling bonds, etc.) on the inner surface (sidewalls) of the semiconductor substrate defining the trenches. These defects may trap charge carriers (e.g., electrons) and cause unwanted leakage current between adjacent pixel regions, resulting in problems such as dark current or / and white pixels in the image sensing integrated circuit.

[0020] These defects can be passivated by forming a high dielectric constant (high-k) insulating material on the sidewalls of the semiconductor substrate defining the trenches. For example, the high dielectric constant insulating material can form an electric field such that holes accumulate on the sidewalls, thereby passivating the charge carriers (e.g., electrons). In some cases, the electric field provided by these high dielectric constant insulating materials may not be strong enough to achieve a sufficient hole density to effectively passivate the charge carriers trapped in the defects. For these cases, the deep trench isolation structure can have a conductive core that is separated from the semiconductor substrate by the insulating material lining the trench. The conductive core can be electrically connected to a bias source configured to apply a bias voltage to the conductive core. By applying a bias voltage to the conductive core, the conductive core can generate an electric field that accumulates holes on the sidewalls of the substrate defining the trench. These holes passivate the defects within the sidewalls of the substrate, thereby improving the performance of the image sensing integrated circuit.

[0021] Forming a photosensing element may include a plurality of dopant implants that form a PN diode within a semiconductor substrate. These dopant implants may include process implants that form a deep N-well. The deep N-well may extend into the substrate to a depth of about 3 μm, about 5 μm, or a greater depth. The depth may be such that the deep N-well extends to the backside of the semiconductor substrate after the semiconductor substrate is thinned. Forming a deep N-well with sufficient dopant concentration at a sufficient depth may involve exposing the substrate to a high dose of high-energy ions. The energy and dose of the implants may make it impractical to mask the implants. Thus, in some cases, the deep N-well is formed by blanket implantation such that the deep N-well extends through the entire semiconductor substrate.

[0022] It has been found that a deep N-well formed by blanket implantation may cause leakage current in a PNP guard ring structure of the same device. The PNP guard ring structure is a guard ring that may be used to maintain electrical isolation between different regions of a semiconductor substrate. For example, the guard ring structure may be formed in a guard ring region between a pixel region and a peripheral region to provide isolation between devices in these respective regions. The pixel region may contain an array of photosensing elements. The peripheral region may contain other elements such as transistors, capacitors, diodes, similar elements, or other semiconductor devices that provide input / output, logic, power regulation, or other functions. The guard ring structure may include an inner ring with P-type doping, a middle ring with N-type doping, and an outer ring with P-type doping. The deep N-well may interfere with the P-type doping of the inner and outer rings and form a leakage current path.

[0023] According to some aspects of the present invention, a process for forming a first deep trench isolation (DTI) structure for isolating adjacent photosensing elements in a pixel region of a semiconductor substrate is also applied to a guard ring region to form a second DTI structure in the guard ring region. In some embodiments, the trenches of the second DTI structure surround the pixel region. In certain embodiments, the trenches of the second DTI structure include trenches for one or more inner rings, trenches for one or more middle rings, and trenches for one or more outer rings. In some embodiments, both the first and second DTI structures are of a type that provides partial isolation. In some embodiments, both the first and second DTI structures are of a type that provides complete isolation. In either case, the second DTI structure may enhance the guard ring function and prevent leakage current, which is particularly useful when the photosensing element includes a deep N-well formed by high-energy blanket implantation. Examples of a backside deep trench isolation (BDTI) structure are disclosed herein, but it should be noted that a frontside deep trench isolation (FDTI) structure may also be used in other embodiments.

[0024] In some embodiments, the first and second DTI structures include conductive cores. In some embodiments, the conductive core of the second DTI structure is coupled to a front-side metal interconnect. In some embodiments, the conductive cores of the inner and outer rings are coupled to a voltage source different from the conductive core in the middle ring. In some embodiments, the conductive core in the middle ring is held at a voltage with a first polarity, while the conductive cores in the inner and outer rings are held at voltages of opposite polarities. When the second DTI structure has a conductive core biased in this manner, the second BDTI structure can provide sufficient isolation such that other guard ring structures (such as PNP structures) become redundant.

[0025] Figure 1A A cross-sectional view of an image sensing integrated circuit device (image sensing IC) 100A according to some embodiments is shown. The image sensing IC 100A includes a semiconductor substrate 102 having a front side 102a and a back side 102b opposite the front side 102a, a pixel region 105, a peripheral region 191, and a guard ring region 193 located between the peripheral region 191 and the pixel region 105. A photosensing element 104 is disposed within the pixel region 105. The photosensing element 104 is configured to generate an electrical signal in response to incident radiation 124.

[0026] The semiconductor substrate 102 includes sidewalls that form trenches 112 extending from the back side 102b of the semiconductor substrate 102 into the semiconductor substrate 102. In some embodiments, the trenches 112 extend from the back side 102b of the semiconductor substrate 102 to the front side 102a of the semiconductor substrate 102. Some of the trenches 112 are located in the pixel region 105 and provide isolation between adjacent photosensing elements 104. Some of the trenches 112 are located in the guard ring region 193 and contribute to providing electrical isolation between the pixel region 105 and the peripheral region 191. In some embodiments, the trenches 112 in the guard ring region 193 extend around the pixel region 105. In some embodiments, the trenches 112 in the guard ring region 193 divide the semiconductor substrate 102 into the pixel region 105 and the peripheral region 191.

[0027] An interlayer dielectric (ILD) structure 106 is disposed on the front side 102a of the semiconductor substrate 102. In some embodiments, the ILD structure 106 includes one or more layers of interlayer dielectric (ILD). The ILD structure 106 surrounds the interconnects 108. The interconnects 108 may include conductive contacts, middle-of-line (MEOL) interconnects, interconnect wires, and / or interconnect vias. The interconnect wires may be disposed in metallization layers.

[0028] The dielectric structure 110 is disposed on the backside 102b of the semiconductor substrate 102 and on the sidewalls of the semiconductor substrate 102 that define the trench 112. In some embodiments, the dielectric structure 110 extends continuously from the backside 102b of the semiconductor substrate 102 to the sidewalls of the semiconductor substrate 102 that define the trench 112. According to some embodiments, the conductive core 114 is disposed within the trench 112 and is laterally separated from the semiconductor substrate 102 by the dielectric structure 110. The conductive core 114 is electrically coupled to the interconnect 108. The conductive core 114 may vertically extend through the top of the photosensing element 104 facing away from the ILD structure 106. In some embodiments, the conductive core 114 vertically extends through the bottom of the dielectric structure 110 within the trench 112. The dielectric structure 110 and the conductive core 114 within the pixel region 105 form a first backside deep trench isolation (BDTI) structure 111 within the semiconductor substrate 102. The dielectric structure 110 and the conductive cores 114A, 114B, and 114C within the guard ring region 193 form a second BDTI structure.

[0029] The backside metal grid 116 may be disposed on top of the conductive core 114. The dielectric structure 110 laterally surrounds the backside metal grid 116. In some embodiments, the conductive core 114 protrudes vertically outward a non-zero distance 115 beyond the backside 102b of the semiconductor substrate 102 and toward the backside metal grid 116. By having the conductive core 114 extend outward beyond the backside 102b of the semiconductor substrate 102, the resolution between adjacent photosensing elements 104 is improved by preventing the lateral movement of incident radiation between the domains of adjacent photosensing elements 104 within the vertical span between the backside 102b of the semiconductor substrate 102 and the backside metal grid 116. In some embodiments, the non-zero distance 115 is in the range of about 500 angstroms (A) to about 5000 angstroms. In some embodiments, the color filter 118 is disposed above the backside 102b of the semiconductor substrate 102. In some embodiments, the microlens 120 is disposed above the color filter 118. The microlens 120 is configured to focus the incident radiation 124 onto the photosensing element 104.

[0030] A first bias source (not shown) is coupled to the conductive core 114 in the pixel region 105 through the inner connection line 108. The first bias source may be in the second substrate 189, the peripheral region 191, or elsewhere. The first bias source can apply a bias voltage to the conductive core 114. By applying a bias voltage to the conductive core 114, the conductive core 114 can generate an electric field to attract holes toward the sidewalls of the semiconductor substrate 102 that define the trench 112 within the pixel region 105. The holes accumulate on the sidewalls and passivate the defects (e.g., traps) on the sidewalls of the semiconductor substrate 102 within the pixel region 105. Passivating the defects can improve the isolation between adjacent photosensing elements 104, improve the modulation transfer function (MTF) of the photosensing elements 104, and / or improve the quantum efficiency of the photosensing elements 104.

[0031] The guard ring region 193 includes an inner ring 121, a middle ring 123, and an outer ring 125. The semiconductor substrate 102 has N-type doping within the middle ring 123. Thus, the sidewalls of the semiconductor substrate 102 that define the trench 112 within the middle ring 123 have N-type doping. In some embodiments, the N-type doping extends from the front side 102a to the back side 102b. The N-type doping may include a shallow N-type well 137 and a deep N-type well 131. The semiconductor substrate 102 has P-type doping within the inner ring 121 and the outer ring 125. Thus, the sidewalls of the semiconductor substrate 102 that define the trench 112 within the inner ring 121 and the outer ring 125 have P-type doping. In some embodiments, the P-type doping extends from the front side 102a to the back side 102b. The P-type doping may include a shallow P-type well 133 and a deep P-type well 135.

[0032] One or more trenches 112 are provided within each of the inner ring 121, the middle ring 123, and the outer ring 125. The conductive core 114A is located within the trench 112 of the inner ring 121. The conductive core 114B is located within the trench 112 of the middle ring 123. The conductive core 114C is located within the trench 112 of the outer ring 125. The conductive cores 114A and 114C of the inner ring 121 and the outer ring 125 extend through the front side 102a, into the ILD structure 106, and contact the inner connection line 108 that connects the conductive cores 114A and 114C to a second bias source (not shown). The conductive core 114B of the middle ring 123 contacts the inner connection line 108 that connects the conductive core 114B to a third bias source (not shown). The third bias source provides a negative voltage. These positive voltage biases and negative voltage biases enhance the isolation effect provided by the guard ring region 193 between the pixel region 105 and the peripheral region 191. The second and third bias sources may be located in the second substrate 189, the peripheral region 191, or other locations. The second bias source provides a positive voltage.

[0033] The photosensing element 104 may be a PN diode formed within the semiconductor substrate 102. The PN diode may include a shallow P-type well 133 and a deep N-type well 131. The shallow P-type well 133 may be present in the inner ring 121 and the outer ring 125 in addition to the pixel region 105. The deep N-type well 131 may extend to the backside 102b and may be present in the peripheral region 191 and the middle ring 123 in addition to the pixel region 105. The peripheral region 191 may contain one or more transistors 175 or similar semiconductor devices. These devices may not be affected by the deep N-type well 131.

[0034] The semiconductor substrate 102 may be connected to a second substrate 189. A second ILD structure 187 including second inner connections 178 may be formed above the second substrate 189. The semiconductor substrate 102 may be connected to the second substrate 189 through a first bonding layer 183 and a second bonding layer 185. The first bonding layer 183 and the second bonding layer 185 may form an electrical connection between the inner connection 108 and the second inner connection 178.

[0035] The attached drawings show the inner connection 108 and the second inner connection 178 being coupled to each other, however these are merely examples. Not all of the inner connections 108 are shown, and the inner connection 108 does not need to be coupled to the second inner connection 178. In some embodiments, the inner connection 108 coupled to the conductive cores 114, 114A, 114B, and 114C is connected to a voltage source in the peripheral region 191 and is not coupled to the second inner connection 178. In some embodiments, some of the inner connections 108 and the second inner connection 178 form a connection between the photosensing element 104 and the associated transistors on the second substrate 189. In some embodiments, the second substrate 189 is a carrier substrate that does not include the second insulating layer structure 187.

[0036] Figure 1B Is shown Figure 1A a top view 122 of the image sensing IC 100A in, for example, along Figure 1A the section line B-B' in. As shown in the top view 122, the photosensing element 104 may have a rectangular shape (e.g., a square shape, a rounded square shape or a similar shape). The trench 112 in the pixel region 105 laterally surrounds the photosensing element 104 in a closed and unbroken path (i.e., a loop). The trench 112 may be formed by the sidewalls of the semiconductor substrate 102 extending in a first direction 202 and a second direction 204 (perpendicular to the first direction 202). The insulating structure 110 is arranged along the opposite sidewalls of the trench 112. The insulating structure 110 separates the semiconductor substrate 102 from the conductive core 114 within the trench 112. In the pixel region 105, the insulating structure 110 and the conductive core 114 continuously surround the photosensing element 104 in a closed and unbroken path (i.e., a loop).

[0037] The trench 112 in the guard ring region 193 continuously surrounds the pixel region 105 in a closed and unbroken path (i.e., a loop). The conductive cores 114 in the pixel region 105 are united into a single grid structure. The conductive cores 114A, 114B, and 114C in the guard ring region 193 are all separated from the grid structure in the pixel region 105 and from each other.

[0038] Figure 1C Shows Figure 1A a top view 140 of the image sensing IC 100A in, for example, along Figure 1A the section line C-C' in. As shown in the top view 140, the backside metal grid 116 includes a second grid structure. The second grid structure is directly located above the first grid structure formed by the conductive cores 114 (see Figure 1B ). In addition, the backside metal grid 116 extends beyond the pixel region 105. In some embodiments, a portion of the backside metal grid 116 forms a conductive mask 119 around the pixel region 105 (see Figure 1A ). The conductive mask 119 blocks incident radiation to prevent dark current caused by the generation of unwanted charge carriers within the semiconductor substrate 102. A portion 141 of the backside metal grid 116, which may be part of the conductive mask 119, contacts the semiconductor substrate 102, thereby grounding the backside metal grid 116.

[0039] Figure 2 Shows a cross-sectional view of the image sensing IC 100B according to some other embodiments. The image sensing IC 100B is similar to the image sensing IC 100A, but the image sensing IC 100B has regions 201 in the inner ring 121 and the outer ring 125 within the semiconductor substrate 102. The regions 201 may correspond to the depth of the deep N-well 131. In some embodiments, the regions 201 have a lightly P-type doping. In some embodiments, the regions 201 have an N-type doping. Thus, in some embodiments, the P-type of the inner ring 121 and the outer ring 125 does not extend all the way to the backside 102b. The regions 201 can provide a leakage path through the guard ring region 193 without the isolation of a second BDTI structure (the second BDTI structure includes the trench 112, the insulating structure 110, and the conductive cores 114A, 114B, and 114C within the guard ring region 193).

[0040] Figure 3 Shows a cross-sectional view of the image sensing IC 100C according to some other embodiments. The image sensing IC 100C is similar to the image sensing IC 100A, but the image sensing IC 100C does not have a PNP guard ring structure (as compared with Figure 1Aare compared). In particular, the shallow P-well 133 and the deep P-well 135 may not be present in the inner ring 121 and the outer ring 125, and the shallow N-well 137 may not be present in the middle ring 123. The second BDTI structure including the trench 112, the insulating structure 110, and the conductive cores 114A, 114B, and 114C within the guard ring region 193 is sufficient to provide the guard ring function, especially when the conductive cores 114A and 114C are biased to a first polarity and the conductive core 114B is biased to the opposite polarity.

[0041] Figure 4 A cross-sectional view of an image sensing IC 100D according to some other embodiments is shown. The image sensing IC 100D is similar to the image sensing IC 100A, but in the image sensing IC 100D, the conductive core 114 (and the conductive cores 114A, the conductive core 114B, and the conductive core 114C) does not directly contact the inner connection 108. Instead, the conductive core 114 lands on the gate electrode 403 of the gate structure 401 located on the front side 102a. The conductive core 114 is coupled to the inner connection 108 through the gate electrode 403. Landing the conductive core 114 on the gate electrode 403 can reduce the aspect ratio of the trench 112. Reducing the aspect ratio makes the trench 112 easier to form and reduces the pinch off phenomenon of the insulating structure 110 near the back side 102b, which may interfere with the formation of the conductive core 114. In some embodiments, the gate structure 401 has the same composition as the gate structure in the transistors (not shown) in the pixel region 105. In certain embodiments, these transistors include transfer gates associated with the photosensing element 104.

[0042] Figure 5 A cross-sectional view of an image sensing IC 100E according to some other embodiments is shown. The image sensing IC 100E is similar to Figure 4 the image sensing IC 100D in, but in the image sensing IC 100E, the conductive core 114 (and the conductive cores 114A, the conductive core 114B, and the conductive core 114C) lands on the gate electrode 503 of the gate structure 501. The gate electrode 503 extends into the semiconductor substrate 102 through the front side 102a to connect to the conductive core 114 within the semiconductor substrate 102. Landing the conductive core 114 on the gate electrode 503 within the semiconductor substrate 102 further reduces the aspect ratio of the trench 112, as compared to Figure 4 the image sensing IC 100D in. In some embodiments, the gate structure 501 has the same composition as the gate structure in the transistors (not shown) in the pixel region 105. In certain embodiments, these transistors include transfer gates associated with the photosensing element 104.

[0043] Figure 6A cross-sectional view of an image sensing IC 100F according to some other embodiments is shown. The image sensing IC 100F is similar to the image sensing IC 100A in FIG. 1, but in the image sensing IC 100F, the conductive cores 114, 114A, 114B, and 114C are all absent, and the trench 112 intersects with a shallow trench isolation (STI) structure 601 formed on the front side 102a. The trench 112 and the insulating structure 110 filling the trench 112 provide a first BDTI structure 111 for the image sensing IC 100F. The BDTI structure 111 extends from the back side 102b to the front side 102a together with the STI structure 601, thereby providing complete isolation for the light sensing element 104. Although the electrical isolation may not be as good as other structures, the trench 112 can be made narrower if it only needs to contain the insulating structure 110. Narrowing the trench 112 increases the Full-Well Capacity (FWC) of the light sensing element 104. In the guard ring region 193, even if the trenches 112 are only filled with the insulating structure 110, they improve the isolation between the pixel region 105 and the surrounding region 191.

[0044] Figure 7 A cross-sectional view of an image sensing IC 100G according to some other embodiments is shown. The image sensing IC 100G is similar to Figure 6 the image sensing IC 100F therein, but without the shallow trench isolation (STI) structure 601. The trench 112 is filled with the insulating structure 110, providing a first BDTI structure 111 in the image sensing IC 100G that does not fully extend to the front side 102a. This configuration leaves space for transistors directly opposite the first BDTI structure 111 on the front side 102a. The shallower trench 112 provides partial isolation in the pixel region 105, which has been sufficient in some applications. Inside the guard ring region 193, the shallower trench 112 is deep enough to cut off the deep N-well 131 and prevent leakage current through the layer.

[0045] Figure 8 A cross-sectional view of an image sensing IC 100H according to some other embodiments is shown. The image sensing IC 100H is similar to the image sensing IC 100A in FIG. 1, but in the image sensing IC 100H, the back side 102b of the semiconductor substrate 102 has a non-planar surface, forming periodic grooves 805 arranged on each light sensing element 104. The grooves 805 are laterally separated from each other by the inclined sidewalls of the semiconductor substrate 102. In some embodiments, the inclined sidewalls of the semiconductor substrate 102 form a triangular-shaped region of the semiconductor substrate 102, as Figure 8As shown in the cross-sectional view. In some embodiments, the groove 805 includes a plurality of triangular cavities located directly above the corresponding light sensing element 104 and between the sidewalls of the semiconductor substrate 102 that define the trench 112. In some embodiments, the first absorption enhancement layer 801 is located on the backside 102b of the semiconductor substrate 102 and within the plurality of grooves 805. In some embodiments, the first absorption enhancement layer 801 contacts the semiconductor substrate 102 along a non-planar surface. The groove 805 and the first absorption enhancement layer 801 form an optional absorption enhancement structure, the topography of which increases the absorption of the semiconductor substrate 102 to incident radiation (e.g., by reducing reflection). Increasing the absorption of the semiconductor substrate 102 to incident radiation increases the quantum efficiency (QE) of the light sensing element 104, thereby improving the performance of the image sensing IC 100H.

[0046] Figures 9 to 26 A cross-sectional view illustrating a method of forming an image sensing IC having a guard ring region with a BDTI structure according to the present invention is shown. Although Figures 9 to 26 is described with reference to methods of various embodiments, it should be understood that Figures 9 to 26 the structure shown in Figures 9 to 26 is not limited to the method, but can exist independently of the method. Figures 9 to 26 is described as a series of actions. The order of these actions may be changed in other embodiments. Although Figures 9 to 26 illustrates and describes a specific set of actions, some of these actions may be omitted in other embodiments. In addition, actions not shown and / or described may be included in other embodiments. Although Figures 9 to 26 the method in

[0047] is described according to the image sensing IC 100A in FIG. 1, the method can be used to form other image sensing ICs.

[0047] As Figure 9 shown in the cross-sectional view 900, a semiconductor substrate 102 is provided, and an N-type dopant 901 is implanted to form a deep N-well 131. In various embodiments, the semiconductor substrate 102 can be any type of semiconductor bulk material (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more die on the wafer, and any other type of related semiconductor and / or epitaxial layer. In some embodiments, the implantation process is a maskless blanket implantation process such that the deep N-well 131 is formed across the semiconductor substrate 102, including portions that will become the pixel region 105, the guard ring region 193, and the peripheral region 191. In some embodiments, the energy at which the N-type dopant 901 is implanted is in the range of about 2000 keV to about 10,000 keV. In some embodiments, the energy at which the N-type dopant 901 is implanted is in the range of about 3000 keV to about 6000 keV. In some embodiments, the dose at which the N-type dopant 901 is implanted is about 1x1010 to about 1x10 13 atoms / cm 2 In some embodiments, the dose of N-type dopant 901 implanted is in the range of about 1x10 11 to about 1x10 12 atoms / cm 2 In some embodiments, the peak doping concentration of the deep N-well 131 is located about 2 to about 5 microns below the front side 102a. In some embodiments, the peak doping concentration of the deep N-well 131 is located about 3 microns below the front side 102a.

[0048] As Figure 10 shown in cross-sectional view 1000 of, a mask 1001 can be formed and N-type dopant 1003 implanted to form a shallow N-well 137 within the guard ring region 193. In some embodiments, a shallow N-well 137 is also formed in the pixel region 105. Additional N-type dopant implantation can occur in the pixel region 105 to provide the desired N-type dopant concentration profile.

[0049] As Figure 11 shown in cross-sectional view 1100 of, one or more masks 1101 can be formed and P-type dopant 1103 implanted to form a deep P-well 135 and a shallow P-well 133 within the guard ring region 193. In some embodiments, the implantation to form the shallow P-well 133 also forms a shallow P-well 133 in the pixel region 105. Additional P-type dopant implantation can occur in the pixel region 105 to provide the desired P-type dopant concentration profile.

[0050] As Figure 12 shown in cross-sectional view 1200 of, additional processing is performed to form transistors 175 in the peripheral region 191 and any floating diffusion regions, transfer gates, etc. or other structures in or on the semiconductor substrate 102, thereby completing the formation of the photosensing element 104. The transistors 175 can include planar field effect transistors, FinFETs, gate-all-around (GAA) devices, etc. or some other semiconductor devices. The photosensing element 104 is described as a type in which the semiconductor substrate 102 provides a light absorption structure, and the PN diode in the semiconductor substrate 102 provides an electric field for charge carrier separation. However, the photosensing element 104 can be of any type, for example, a type formed by implanting epitaxial germanium (Ge) on the front side 102a.

[0051] As Figure 13As shown in the cross-sectional view 1300, one or more inner connections 108 are formed within an ILD structure 106 formed along the front side 102a of a semiconductor substrate 102. The ILD structure 106 includes a plurality of stacked ILD layers, and the one or more inner connections 108 include alternating layers of conductive lines and vias. In some embodiments, one or more of the one or more inner connections 108 are formed using a damascene process (e.g., a single damascene process or a dual damascene process). The damascene process includes forming an ILD layer over the front side 102a of the semiconductor substrate 102, etching the ILD layer to form vias and / or trenches, and filling the vias and / or trenches with a conductive material. In some embodiments, the ILD layer can be deposited by a vapor deposition process, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced-CVD (PE-CVD), atomic layer deposition (ALD), etc. The conductive material is deposited using a vapor deposition process and / or an electroplating process (e.g., electroplating, electroless plating, etc.). The ILD material can be silicon dioxide (SiO2), a low-k dielectric, etc. The conductive material can be or include tungsten, copper, aluminum, etc. As Figure 13 As further shown in the cross-sectional view 1300, a first bonding layer 183, which can include a bonding pad 1301, etc., can be formed over the ILD structure 106 by a similar or different process.

[0052] As Figure 14 As shown in the cross-sectional view 1400, the semiconductor substrate 102 can be flipped and aligned with a second substrate 189. A second ILD structure 187 and a second bonding layer 185 can be disposed over the second substrate 189. In some embodiments, the second substrate 189 is a support substrate or a processing substrate. In some embodiments, the second substrate 189 includes semiconductor material, such as silicon, and semiconductor devices, such as transistors, are formed on the second substrate 189.

[0053] As Figure 15 As shown in the cross-sectional view 1500, the semiconductor substrate 102 can be bonded to the second substrate 189 through the first bonding layer 183 and the second bonding layer 185. The bonding process can be oxide-to-oxide bonding, metal-to-metal bonding, a combination thereof, etc., or any other suitable bonding process. In some embodiments, the first bonding layer 183 and the second bonding layer 185 form an electrical connection between the semiconductor substrate 102 and the second substrate 189.

[0054] As Figure 16As shown in the cross-sectional view 1600, after bonding, the semiconductor substrate 102 can be thinned from the back side 102b. Thinning the semiconductor substrate 102 allows light to be more easily transmitted to the light sensing element 104. The semiconductor substrate 102 can be thinned by etching, mechanical grinding, chemical mechanical polishing (CMP), or any other suitable process. In some embodiments, the semiconductor substrate 102 is thinned to less than about 10 μm. In some embodiments, the semiconductor substrate 102 is thinned to about 5 μm or less.

[0055] As Figure 17 shown in the cross-sectional view 1700, a mask 1701 can be formed and an etchant 1703 can be applied to form trenches 112. The trenches 112 can extend vertically from the back side 102b to the front side 102a. The trenches 112 can further extend into the ILD structure 106. In some embodiments, the etching process exposes some of the inner interconnects 108. In some embodiments, the trenches 112 have a width in the range of about 50 nm to about 400 nm. In some embodiments, the trenches 112 have a width in the range of about 80 nm to about 200 nm. Some of the trenches 112 are formed in the pixel region 105 and laterally surround the light sensing element 104. Some of the trenches 112 are formed in the guard ring region 193 and divide the semiconductor substrate 102 in the guard ring region 193. The mask 1701 can be a photoresist, a hard mask, etc., and can be patterned by photolithography, electron beam lithography, or any other suitable process. The etchant 1703 can be a dry etchant and can contain one or more of oxygen (O2), nitrogen (N2), hydrogen (H2), argon (Ar), and / or fluorine substances (such as CF4, CHF3, C4F8, etc.). The etching process can be carried out in multiple steps to keep the trenches 112 narrow and provide trenches 112 with a high aspect ratio. After etching, the mask 1701 can be stripped.

[0056] As Figure 18As shown in the cross-sectional view 1800, a dielectric structure 110 can be deposited to line the trench 112. The dielectric structure 110 can include one or more layers formed by one or more vapor deposition processes. In some embodiments, the vapor deposition process includes ALD. In some embodiments, at least the bottom layer of the dielectric structure 110 includes a high-k dielectric deposited by a conformal deposition process such as ALD. Examples of high-k dielectrics that may be suitable include hafnium oxide (HfO), aluminum oxide (AlO), zirconium oxide (ZrO), titanium oxide (TiO), strontium oxide (SrO), barium oxide (BaO), barium titanate (BaTiO3), tantalum oxide (Ta2O3), lanthanum oxide (La2O3), yttrium oxide (Y2O3), etc. Non-conformal deposition processes can be used to deposit other layers such that the dielectric structure 110 on the back side 102b is thicker than the dielectric structure 110 within the trench 112. In some embodiments, the total thickness of the dielectric structure 110 within the trench 112 is in the range of about 10 nm to about 100 nm. In some embodiments, the total thickness of the dielectric structure 110 on the back side 102b is in the range of about 50 nm to about 500 nm.

[0057] As Figure 19 shown in the cross-sectional view 1900, an etchant 1901 can be applied to etch through any dielectric within the bottom of the trench 112 and expose the interconnect 108. The etching process breaks through the dielectric structure 110 at the bottom of the trench 112. In some embodiments, the etching process is used to extend the trench 112 into the ILD structure 106. In other words, the etching process shown in Figure 17 the cross-sectional view 1700 (which can be selective to the semiconductor of the semiconductor substrate 102) can stop at or near the front side 102a. Figure 19 The etching process shown in the cross-sectional view 1900 may be more effective for etching the dielectric of the ILD structure 106.

[0058] As Figure 20 shown in the cross-sectional view 2000, a conductive material 2001 is deposited to fill the trench 112 between the sidewalls of the dielectric structure 110. The conductive material can include tungsten, aluminum, etc., or some other suitable metal or other conductive material. The conductive material can be deposited by a vapor deposition process, an electroplating process, etc., or any other suitable method.

[0059] As Figure 21 shown in the cross-sectional view 2100 in, a planarization process can be performed to remove the conductive material 2001 outside the trench 112. The remaining conductive material 2001 forms the conductive cores 114, 114A, 114B, and 114C. The planarization process can be CMP or any other suitable planarization process.

[0060] As Figure 22As shown in the cross-sectional view 2200, an additional layer 2201 of the dielectric structure 110 can be deposited. The additional layer 2201 can include one or more layers of dielectric materials, such as silicon oxide (SiO2), tantalum oxide (Ta2O3), etc., or any other suitable dielectric material. The additional layer 2201 can be formed by a vapor deposition process or the like.

[0061] As Figure 23 shown in the cross-sectional view 2300 of , a mask 2301 can be formed and an etchant 2307 can be applied to form trenches 2305 and trench 2303. The trench 2305 may be directly above the trench 112. The trench 2303 can extend beyond the pixel region 105. The trenches 2305 and 2303 can be connected. After etching, the mask 2301 can be stripped.

[0062] As Figure 24 shown in the cross-sectional view 2400 of , a mask 2401 can be formed and an etchant 2403 can be applied to form a trench 2405 within the trench 2303. The semiconductor substrate 102 is exposed through the trench 2405. The trench 2405 can extend into the semiconductor substrate 102. The trench 2405 can be one or more holes instead of a trench. After etching, the mask 2401 can be stripped. Figure 23 and Figure 24 the order of the processes shown in can be reversed.

[0063] As Figure 25 shown in the cross-sectional view 2500 of , metal can be deposited to fill the trenches 2303, 2305, and 2405. The metal can be deposited by vapor deposition, electroplating, etc., or any other suitable process. The excess metal can be removed by CMP or the like. The metal deposited in the trench 2305 forms the backside metal grid 116. The metal deposited in the trench 2303 forms the conductive mask 119. The metal deposited in the trench 2405 provides a portion 141 that grounds the backside metal grid 116 and the conductive mask 119 to the semiconductor substrate 102.

[0064] As Figure 26 shown in the cross-sectional view 2600 of , an additional layer 2601 of the dielectric structure 110 can be deposited. The additional layer 2601 can include one or more layers of dielectric materials, such as silicon oxide (SiO2), tantalum oxide (Ta2O3), etc., or any other suitable dielectric material. The additional layer 2601 can be formed by a vapor deposition process or the like. Further processing, such as forming the color filter 118 and the microlens 120, can be performed to fabricate an image sensing IC, such as the image sensing IC 100A of FIG. 1.

[0065] Figures 27 to 35 shows a variation of the foregoing process. This variation can fabricate an image sensing IC, such as Figure 4imaging sensing IC 100D. The change can start from Figure 11 the structure shown in cross-sectional view 1100.

[0066] As Figure 27 shown in cross-sectional view 2700, the gate stack 2701 can be deposited on Figure 11 the structure shown in cross-sectional view 1100. The gate stack 2701 includes a gate dielectric layer 2703 and a gate electrode layer 2705. The gate dielectric layer 2703 can include oxides (e.g., silicon oxide), nitrides (e.g., silicon oxynitride), high-k dielectrics, etc. The gate electrode layer 2705 can comprise polysilicon, metal, etc. These layers can be deposited by a chemical vapor deposition process or any other suitable process.

[0067] As Figure 28 shown in cross-sectional view 2800, a mask 2805 can be formed and an etchant 2803 can be applied to define a gate structure 401 from the gate stack 2701. The patterning process defines a gate electrode 403 from the gate electrode layer 2705 and a gate dielectric 2801 from the gate dielectric layer 2703. Some gate structures 401 are formed in the pixel region 105, and some gate structures 401 are formed in the guard ring region 193.

[0068] As Figure 29 shown in cross-sectional view 2900, a process similar to that shown in Figure 12 cross-sectional view 1200 can be performed to form a transistor 175 in the peripheral region 191. The transistor 175 can have a different gate dielectric layer thickness or composition from the gate structure 401.

[0069] As shown in cross-sectional view 3000 or Figure 30 shown, a spacer 3001 can be formed on the sidewalls of the gate structure. The spacer formation process can include the deposition and etching of spacer material. The spacer material can include one or more layers of nitride, oxide, oxynitride, carbon oxide, etc.

[0070] As Figure 31 shown in cross-sectional view 3100, a mask 3101 can be formed and dopants 3105 can be implanted to form source / drain regions 3103 adjacent to the transistor 175. The mask 3101 can be provided to prevent the dopants 3105 from being implanted around the gate structure 401 for coupling the conductive cores 114, 114A, 114B, and 114C to the interconnect 108 (see Figure 4)。Since these gate structures are used as connectors rather than transistors, the source / drain does not need to be around these area gates and may interfere with other nearby components. However, dopant 3105 can be implanted into some regions of the pixel region 105, such as adjacent to the gate structure 401 that provides a transfer gate (not shown) or a floating diffusion region (not shown). The dopant implantation can complete the formation of the photosensing element 104. After doping, the mask 3101 can be stripped. Then additional processing as described in cross-sectional views 1300 to 1600 in connection with Figures 13 to 16 can be performed to fabricate the structure shown in cross-sectional view 3200 of Figure 32 .

[0071] As Figure 33 shown in cross-sectional view 3300, a mask 1701 can then be formed and an etchant 1703 applied to form trenches 112. In some embodiments, the etching process selectively etches silicon on the oxide and stops at the gate dielectric layer 2801. The gate dielectric layer 2801 can serve as an etch stop layer. When both the gate electrode 403 and the semiconductor substrate 102 are semiconductors, stopping the etching process at the gate dielectric layer 2801 may be particularly desirable. In some embodiments, the etching process stops at the gate electrode 403.

[0072] As Figure 34 shown in cross-sectional view 3400, the dielectric structure 110 can be formed as described in connection with cross-sectional view 1800 of Figure 18 . As Figure 35 shown in cross-sectional view 3500, an etching process can be performed to break through the dielectric at the bottom of the trenches 112, as described in connection with cross-sectional view 1900 of Figure 19 . Subsequent processing can then continue as described in cross-sectional views 2000 to 2600 of Figures 20 to 26 to provide the image sensing IC in Figure 4 , such as image sensing IC 100D.

[0073] Figures 36 to 39 shows a variation of the foregoing process. This variation can fabricate an image sensing IC, such as Figure 5 image sensing IC 100E. The variation can start from the structure shown in cross-sectional view 1100 of Figure 11 .

[0074] As Figure 36 shown in cross-sectional view 3600, a mask 3601 can be formed over the structure shown in cross-sectional view 1100 of Figure 11 , and an etchant 3605 applied to form trenches 3603 in the front side 102a. As Figure 37As shown in the cross-sectional view 3700, a gate stack 3701 can then be formed. The gate stack 3701 is formed inside and around the trench 3603 and includes a gate dielectric layer 3703 and a gate electrode layer 3705. Compared with the process described in the cross-sectional view 2700 in conjunction with Figure 27 additional steps can be taken to planarize the gate electrode layer 3705.

[0075] As Figure 38 shown in the cross-sectional view 3800, the gate stack 3701 can be patterned to form a gate structure 501. The process can be as described in the cross-sectional view 2800 with respect to Figure 28 The resulting gate electrode 503 can include a portion buried in the semiconductor substrate 102 and a portion above the front side 102a.

[0076] Subsequently, the processing can continue in accordance with the methods described in the cross-sectional views 2900 to 3300 in Figures 29 to 33 As shown in the cross-sectional view 3900 in Figure 39 when an etching process is performed to form the trench 112, the etching may stop on the gate dielectric layer 3703. Then, the processing can continue in accordance with the methods described in the cross-sectional views 3400 to 3600 and the cross-sectional views 2000 to 2600 in Figures 34 to 36 and Figures 20 to 26 to provide the Figure 5 image sensing IC in

[0077] Figures 40 to 42 shows a variation of the process described in the cross-sectional views 900 - 2600 in conjunction with Figures 9 to 26 This variation can fabricate an image sensing IC, such as the Figure 6 image sensing IC 100F in

[0078] The described variation may start from the structure shown in Figure 11 As shown in the cross-sectional view 4000 in Figure 40 an STI structure 601 is formed in the front side 102a. Forming the STI structure 601 can include etching a trench, depositing a dielectric to fill the trench, and removing the excess dielectric by planarization. The dielectric can be, for example, an oxide (such as silicon oxide), a nitride (such as silicon nitride, silicon oxynitride, etc.), etc.

[0079] Subsequently, the processing can continue in accordance with the cross-sectional views 1200 to 1700 described in Figures 12 to 17 but without forming the internal connection 108 coupled to the conductive core 114 (see FIG. 1). Other internal connections 108 (not shown) can still be formed. As Figure 41As shown in the cross-sectional view 4100, when the etching process is performed to form the trench 112, the etching stops at the STI structure 601.

[0080] As Figure 42 shown in the cross-sectional view 4200 in, when the deposition process is performed to form the dielectric structure 110, it is performed in such a way that the dielectric structure 110 completely fills the trench 112. Subsequently, the processing can continue in accordance with Figures 22 to 26 the cross-sectional views 2200 to 2600 described in to provide an image sensing IC, such as Figure 6 the image sensing IC 100F.

[0081] Figures 43 to 45 shows a variation of the process described in connection with Figures 9 to 26 the cross-sectional views 900 - 2600. This variation can fabricate an image sensing IC, such as Figure 8 the image sensing IC 100H. The variation can start from the structure shown in the cross-sectional view 1600 of Figure 16 . As Figure 43 shown in the cross-sectional view 4300 of, a mask 4301 is formed and one or more etchants 4303 are applied to pattern the back side 102b of the semiconductor substrate 102. The one or more etchants 4303 remove a portion of the semiconductor substrate 102 to form a recess 805. The recess 805 is formed directly above the light sensing element 104. In some embodiments, the etching process includes a dry etching process. The dry etching process can be, for example, a coupled plasma etch process, such as an inductively coupled plasma (ICP) etch process or a capacitive coupled plasma (CCP) etch process. In some embodiments, the patterning process includes wet etching.

[0082] As Figure 44 shown in the cross-sectional view 4400 of, after removing the mask 4301, it can be Figure 43Above the structure shown in the cross-sectional view 4300, a first absorption enhancement layer 801, a second absorption enhancement layer 803, and a dielectric layer 807 are formed. These layers can be formed by chemical vapor deposition or any other suitable process. The first absorption enhancement layer 801 lines the back side 102b. In some embodiments, the first absorption enhancement layer 801 includes a high-k dielectric layer, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), etc. The second absorption enhancement layer 803 is optional. If included, the second absorption enhancement layer 803 can be an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride, silicon oxynitride, etc.), a carbide (e.g., silicon carbide, silicon carbon oxide, etc.), etc. The dielectric layer 807 can fill the plurality of recesses 805. The dielectric layer 807 can be a dielectric, such as one of the dielectrics included in the dielectric structure 110 (see Figure 8 ).

[0083] As Figure 45 shown in the cross-sectional view 4500, a process can be performed to planarize the dielectric layer 807. The planarization process can include CMP, etching processes, etc. Processing can continue in accordance with Figures 17 to 26 the cross-sectional views 1700 to 2600 described to provide an image sensing IC, such as Figure 8 the image sensing IC 100H.

[0084] Figure 46 FIG. presents a flowchart of a process 4600 according to the present invention that can be used to form an image transmitting IC. Although Figure 46 the process 4600 is shown and described herein as a series of actions or events, it should be understood that the order of the shown actions or events should not be construed as restrictive. For example, some actions can occur in a different order and / or concurrently with other actions or events other than those shown and / or described herein. In addition, not all of the shown actions are required to implement one or more aspects or embodiments described herein, and one or more of the actions described herein can be performed in one or more separate actions and / or phases.

[0085] The process 4600 can start with an action 4601 of doping to form a light-sensing PN diode. Examples are provided in the cross-sectional views 900 to 1100 of Figures 9 to 11 . In some embodiments, this includes an action 4603, which is a comprehensive deep well implant of the type shown in the cross-sectional view 900 of Figure 9 . The action 4601 includes an action 4605 of masked P-type well implant. In some embodiments, the masked P-type well implant forms a P-type well in the guard ring region and a portion of the pixel region. In Figure 11A cross-sectional view 1100 provides an example. It should be understood that in addition to what is described, operation 4601 may also include additional dopant implantations.

[0086] Operation 4607 is to implant dopants to form a PNP or NPN guard ring structure. Figures 9 to 11 Cross-sectional views 900 to 1100 also provide an example of this process. As shown in these figures, the processes of operation 4601 and operation 4607 may overlap to reduce the number of processing steps. It should be understood that in addition to the examples shown, the dopant types and voltage polarities may be opposite to the examples provided.

[0087] Operation 4609 is to form and pattern a gate stack. Figure 27 and Figure 28 Cross-sectional views 2700 and 2800 provide an example. Figures 36 to 38 Cross-sectional views 3600 to 3800 provide another example.

[0088] Operation 4611 is to form spacer walls around the gate structure. Figure 30 Cross-sectional view 3000 provides an example. Operation 4613 is to dope to form source / drain regions aligned with the spacer walls. The gate structure for direct connection to the conductive core of the backside deep trench isolation structure may be masked during the implantation process. Figure 31 Cross-sectional view 3100 provides an example.

[0089] Operation 4615 is to bond the semiconductor substrate to a carrier or a processing substrate. Figures 14 to 15 Cross-sectional views 1400 - 1500 provide an example. Operation 4617 is to flip and thin the semiconductor substrate. Figure 16 Cross-sectional view 1600 provides an example.

[0090] Operation 4619 is to etch to form trenches for the backside deep trench isolation structure in the pixel region and the guard ring region. Figure 17 Cross-sectional view 1700 provides an example, where these trenches stop on the metal structure in the front-side interlayer dielectric. The metal structure may be, for example, a first (M1) metallization layer line. Figure 33 Cross-sectional view 3300 and Figure 39 Cross-sectional view 3900 provide an example, where the trenches stop on the gate oxide layer. Figure 42 Cross-sectional view 4200 provides an example, where the trenches stop on the front-side STI structure. The trenches may also stop within the semiconductor substrate to provide only partial isolation.

[0091] Operation 4621 is to deposit a dielectric in the trenches. Figure 18 Cross-sectional views 1800 and Figure 34Cross-sectional view 3400 provides an example where the dielectric lines the trench. Figure 42 Cross-sectional view 4200 provides an example where the dielectric fills the trench.

[0092] Actions 4623 and 4625 are optional steps for a backside deep trench isolation structure with a conductive core. Action 4623 is to etch through any dielectric at the bottom of the trench. Figure 19 Cross-sectional view 1900 and Figure 35 Cross-sectional view 3500 provides an example. Action 4625 is to fill the trench with a conductive material. Figures 20 to 21 Cross-sectional views 2000 to 2100 provide examples.

[0093] Some aspects of the present utility model relate to an image sensing integrated circuit device, which includes a substrate having a pixel region, a peripheral region, and a guard ring region. The guard ring region is located between the pixel region and the peripheral region. Light sensing elements are formed in an array in the pixel region. A first backside deep trench isolation structure extends between the light sensing elements. A second backside deep trench isolation structure is in the guard ring region. The second backside deep trench isolation structure is separated from the first backside deep trench isolation structure. In some embodiments, the substrate includes a semiconductor body having one side; the semiconductor body includes a deep N-well extending to the side; and the deep N-well is in the pixel region, the guard ring region, and the peripheral region. In some embodiments, the image sensing integrated circuit device further includes a plurality of metal interconnects disposed above the substrate, wherein the first deep trench isolation structure and the second deep trench isolation structure are coupled to different ones of the plurality of metal interconnects. In some embodiments, the second deep trench isolation structure includes an inner ring conductive core, a middle ring conductive core, and an outer ring conductive core; and the inner ring conductive core and the outer ring conductive core are coupled to a first voltage source; and the middle ring conductive core is coupled to a second voltage source different from the first voltage source. In some embodiments, the image sensing integrated circuit device further includes a guard ring in the guard ring region, the guard ring including an inner ring having a first doping type, a middle ring having an opposite doping type, and an outer ring having the first doping type, wherein each of the inner ring, the middle ring, and the outer ring of the second deep trench isolation structure has a component.

[0094] Some aspects of the present utility model relate to an image sensing integrated circuit device, which includes a substrate having a pixel region, a peripheral region, and a guard ring region. The guard ring region is located between the pixel region and the peripheral region. Light sensing elements are arranged in the pixel region. A first sidewall of the substrate forms one or more first trenches extending from the back side into the substrate on opposite sides of the light sensing elements. A second sidewall of the substrate forms one or more second trenches extending from the back side into the substrate in the guard ring region. The one or more second trenches laterally separate the pixel region from the peripheral region. In some embodiments, the one or more second trenches surround the pixel region. In some embodiments, the one or more second trenches include a plurality of second trenches. In some embodiments, the guard ring region includes a PNP guard ring structure. In some embodiments, the image sensing integrated circuit device further includes: a dielectric structure arranged on the second sidewall; a first conductive core arranged in the one or more second trenches, laterally separated from the substrate by the dielectric structure, and coupled to a first voltage source; a second conductive core arranged in the one or more second trenches, laterally separated from the substrate by the dielectric structure, and coupled to a second voltage source; and a third conductive core arranged in the one or more second trenches, laterally separated from the substrate by the dielectric structure, and coupled to the first voltage source; wherein the second conductive core is between the first conductive core and the third conductive core; and the first voltage source and the second voltage source are different. In some embodiments, a P-type doped sidewall of the substrate laterally surrounds the first conductive core and the third conductive core; and an N-type doped sidewall of the substrate laterally surrounds the second conductive core. In some embodiments, the image sensing integrated circuit device further includes: an interconnection arranged in an interlayer dielectric structure on the first side; a dielectric structure arranged on the second sidewall; and a conductive core arranged in the one or more second trenches and laterally separated from the substrate by the dielectric structure; wherein the conductive core is electrically coupled to the interconnection.

[0095] Some aspects of the present disclosure relate to a method, the method including forming a photosensing element in a pixel region of a substrate, forming a transistor in a peripheral region of the substrate, forming one or more internal connections in an ILD structure on a front side of the substrate, and forming trenches in a back side of the substrate. The trenches include a first trench in the pixel region and a second trench in a guard ring region disposed between the pixel region and the peripheral region. In some embodiments, the second trench includes a second trench forming a first ring around the pixel region and a second trench forming a second ring around the first ring. In some embodiments, the method further includes forming a conductive core in the trenches, wherein the conductive core is coupled to the one or more internal connections. In some embodiments, the method further includes: forming a gate structure on the first side, wherein the gate structure includes a first gate electrode in the pixel region and a second gate electrode in the guard ring region; the one or more internal connections being coupled to the gate electrode; and the conductive core contacting the gate electrode. In some embodiments, a portion of the gate electrode is embedded in the substrate. In some embodiments, forming the photosensing element in the pixel region of the substrate includes a blanket doping implantation process forming a deep N-well across the substrate. In some embodiments, the method further includes forming a PNP guard ring structure in the guard ring region, wherein the PNP guard ring structure includes a P-type doped inner ring, an N-type doped middle ring, and a P-type doped outer ring. In some embodiments, the second trench includes a second trench in the inner ring, a second trench in the middle ring, and a second trench in the outer ring.

[0096] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. An image sensor integrated circuit device, characterized in that: include: A substrate comprising a pixel region, a peripheral region, and a guard ring region between the pixel region and the peripheral region; an array of light sensing elements in the pixel region; a first deep trench isolation structure extending between the light sensing elements in the array; as well as A second deep trench isolation structure is provided in the guard ring region, wherein the second deep trench isolation structure is separated from the first deep trench isolation structure.

2. The image sensor integrated circuit device according to claim 1, wherein: The substrate includes a semiconductor body having a side; The semiconductor body includes a deep N-type well extending to the side; and The deep N-type well is in the pixel region, the guard ring region, and the surrounding region.

3. The image sensor integrated circuit device according to claim 1, wherein: The second deep trench isolation structure includes an inner ring conductive core, a middle ring conductive core and an outer ring conductive core; and The inner ring conductive core and the outer ring conductive core are coupled to a first voltage source; and The mid-ring conductive core is coupled to a second voltage source different from the first voltage source.

4. The image sensor integrated circuit device according to claim 1 further includes a guard ring in the guard ring area, the guard ring including an inner ring having a first doping type, a middle ring having an opposite doping type, and an outer ring having the first doping type, wherein each of the inner ring, the middle ring, and the outer ring of the second deep trench isolation structure has a component.

5. An image sensor integrated circuit device, characterized in that: include: A substrate comprising a first side, a second side, a pixel region, a peripheral region, and a guard ring region between the pixel region and the peripheral region; as well as a light sensing element in the pixel region, wherein a first sidewall of the substrate is formed with one or more first trenches extending from the second side into the substrate on opposite sides of the light sensing element; wherein the second sidewall of the substrate is formed in the guard ring region and includes one or more second trenches extending from the second side into the substrate; as well as The one or more second trenches laterally separate the pixel region from the surrounding region. 6 . The image sensor integrated circuit device according to claim 5 , wherein the one or more second trenches surround the pixel region. 7 . The image sensor integrated circuit device according to claim 5 , wherein the one or more second trenches comprises a plurality of second trenches. 8 . The image sensor integrated circuit device according to claim 5 , wherein the guard ring region comprises a PNP guard ring structure.

9. The image sensor integrated circuit device according to claim 5, further comprising: a dielectric structure, arranged on the second side wall; a first conductive core disposed within the one or more second trenches, laterally separated from the substrate by the dielectric structure, and coupled to a first voltage source; a second conductive core disposed within the one or more second trenches, laterally separated from the substrate by the dielectric structure, and coupled to a second voltage source; as well as a third conductive core disposed within the one or more second trenches, laterally separated from the substrate by the dielectric structure, and coupled to the first voltage source; wherein the second conductive core is between the first conductive core and the third conductive core; and The first voltage source and the second voltage source are different.

10. The image sensor integrated circuit device according to claim 5, further comprising: an internal connection line arranged in the interlayer dielectric structure of the first side; a dielectric structure, arranged on the second side wall; as well as a conductive core disposed within the one or more second trenches and laterally separated from the substrate by the dielectric structure; The conductive core is electrically coupled to the inner connection line.

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