Semiconductor test board card, semiconductor test equipment and test system

Abstract

The utility model provides a semiconductor test board card, semiconductor test equipment and a test system. The semiconductor test board card comprises a main control board and a resource daughter board detachably connected with the main control board through a daughter board connector, wherein the resource daughter board comprises a first processor and a parameter measurement unit which are connected in sequence; the main control board comprises a second processor, a logic switch circuit and a calibration circuit which are connected in sequence; the second processor is connected with the first processor and is used for receiving an instruction of the upper computer and then arbitrating and transmitting the instruction to the first processor, so that the first processor controls the parameter measurement unit to output a test signal to a tested device through the logic switch circuit and / or controls the parameter measurement unit to measure voltage and / or current at two ends of the tested device; and the parameter measuring unit is selectively connected with the logic switch circuit, so that the calibration circuit calibrates the parameter measuring unit to correct the deviation of the test signal output by the parameter measuring unit. The calibration efficiency of the parameter measurement unit is improved.

Description

Technical Field

[0001] The present application relates to the field of testing, and particularly to a semiconductor test board, a semiconductor test device, and a test system. Background Art

[0002] Chip testing refers to using a semiconductor test device to output test signals to detect various parameter indicators of a device under test, and rejecting defective products to control the ex-factory quality of semiconductor devices.

[0003] During the testing process of a semiconductor test device, it is necessary to use a parameter measurement unit in the semiconductor test board to provide excitation and measure the voltage and / or current at both ends of the device under test. Since the test signals output by the parameter measurement unit itself may be biased, it needs to be calibrated before measurement. In the prior art, external instruments are usually used to calibrate the parameter measurement unit, which requires special wiring and other operations, and the interaction efficiency between the instrument and the parameter measurement unit is relatively low, resulting in low calibration efficiency. Summary of the Utility Model

[0004] Based on this, it is necessary to provide a semiconductor test board, a semiconductor test device, and a test system for the above technical problems.

[0005] In a first aspect, an embodiment of the present application provides a semiconductor test board, which is connected to a device under test and includes a main control board and a resource sub-board detachably connected to the main control board through a daughter-board connector. The resource sub-board includes: a first processor and a parameter measurement unit connected in sequence; the main control board includes: a second processor, a logic switch circuit, and a calibration circuit connected in sequence; the logic switch circuit is respectively connected to the daughter-board connector and the device under test;

[0006] The second processor is connected to the first processor and is used to arbitrate and transmit the received host computer instructions to the first processor, so that the first processor controls the parameter measurement unit to output test signals to the device under test through the logic switch circuit and / or controls the parameter measurement unit to measure the voltage and / or current at both ends of the device under test;

[0007] The parameter measurement unit is selectively connected to the logic switch circuit, so that the calibration circuit calibrates the parameter measurement unit to correct the deviation of the test signals output by the parameter measurement unit.

[0008] In some embodiments, the main control board further includes a health management module connected to the second processor; the resource sub-board further includes a first monitoring module connected to the first processor;

[0009] The first monitoring module is used to detect the first detection information of the resource daughter board and transmit it to the first processor;

[0010] The health management module is connected to the first processor via the daughter board connector, and is used to obtain the first detection information and perform real-time monitoring on the resource daughter board.

[0011] In some embodiments, the main control board further includes a second monitoring module connected to the second processor;

[0012] The second monitoring module is used to detect the second detection information of the main control board and transmit it to the second processor;

[0013] The health management module is further used to obtain the second detection information and perform real-time monitoring on the main control board.

[0014] In some embodiments, the first monitoring module includes a first temperature monitoring module and a first power supply monitoring module connected to the first processor, and / or, the second monitoring module includes a second temperature monitoring module and a second power supply monitoring module connected to the second processor.

[0015] In some embodiments, the logic switch circuit includes a plurality of relays. The first end of each relay is connected to the daughter board connector, the second end is connected to the device under test, and the third end is connected to the calibration circuit.

[0016] In some embodiments, the calibration circuit includes at least one calibration module. The calibration module is connected to the instrument bus and then accesses an external instrument; when the calibration circuit includes at least two calibration modules, the at least two calibration modules are connected in parallel.

[0017] In some embodiments, the parameter measurement unit includes an error comparator, an integrator, an operational amplifier, a sampling resistor, a first differential amplifier, and a second differential amplifier;

[0018] The first processor, the error comparator, the integrator, the operational amplifier, the sampling resistor, and the first differential amplifier are connected to form a current feedback loop;

[0019] The first processor, the error comparator, the integrator, the operational amplifier, the sampling resistor, the device under test, and the second differential amplifier are connected to form a voltage feedback loop.

[0020] In some embodiments, the main control board further includes a second clock management module connected to the daughter board connector and the second processor, configured to obtain an external clock signal and send it to the second processor and the resource daughter board for clock signal synchronization; and / or, the resource daughter board further includes a first clock management module connected to the daughter board connector and the first processor, configured to obtain the clock signal sent by the main control board via the daughter board connector and send it to the first processor.

[0021] In a second aspect, an embodiment of the present application provides a semiconductor test device, including a communication board and a semiconductor test board card as described in the first aspect connected to the communication board.

[0022] In a third aspect, an embodiment of the present application provides a test system, which includes a host computer and a semiconductor test device as described in the second aspect communicatively connected to the host computer.

[0023] Compared with the prior art, in this technical solution, by setting a calibration circuit and a logic switch circuit on the main control board, the calibration of the parameter measurement unit is realized through the calibration circuit. Compared with the calibration method of external instruments, it is more convenient and improves the calibration efficiency;

[0024] By multiplexing the logic switch circuit, it is possible to measure the voltage and / or current across the device under test, and it is also possible to calibrate the parameter measurement unit, thus simplifying the wiring;

[0025] The resource daughter board is detachably connected to the main control board, which facilitates the installation and removal of the resource daughter board. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic structural diagram of a semiconductor test board card in an embodiment of the present application;

[0027] Figure 2 is a schematic overall structural diagram of a semiconductor test board card in an embodiment of the present application;

[0028] Figure 3 is a schematic connection diagram of a parameter measurement unit and a calibration module in an embodiment of the present application;

[0029] Figure 4 is a schematic connection diagram of a calibration bus in an embodiment of the present application.

[0030] Among them, 10 is the main control board; 20 is the resource sub-board; 30 is the device under test; 110 is the second processor; 120 is the switch control circuit; 130 is the logic switch circuit; 140 is the calibration circuit; 141 is the calibration module; 151 is the second temperature monitoring module; 152 is the second power supply monitoring module; 160 is the health management module; 170 is the second clock management module; 180 is the in-board power supply; 210 is the sub-board connector; 220 is the parameter measurement unit; 221 is the parameter measurement module; 230 is the first processor; 241 is the first temperature monitoring module; 242 is the first power supply monitoring module; 250 is the first clock management module; 260 is the DC-DC power module. Detailed implementation manners

[0031] In order to make the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0032] Obviously, the accompanying drawings in the following description are only some examples or embodiments of the present application. For those of ordinary skill in the art, without creative efforts, the present application can also be applied to other similar scenarios based on these drawings. In addition, it can also be understood that although the efforts made in this development process may be complex and lengthy, for those of ordinary skill in the art related to the content disclosed in the present application, some design, manufacturing or production changes based on the technical content disclosed in the present application are only conventional technical means and should not be understood that the content disclosed in the present application is insufficient.

[0033] When "embodiment" is mentioned in the present application, it means that the specific features, structures or characteristics described in combination with the embodiment can be included in multiple embodiments of the present application. The appearance of this phrase in various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. It is explicitly and implicitly understood by those of ordinary skill in the art that the embodiments described in the present application can be combined with other embodiments without conflict.

[0034] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the ordinary meanings understood by those with ordinary skills in the technical field to which this application belongs. The words such as "a", "an", "one kind", "the" and the like involved in this application do not indicate a quantity limitation and may represent a singular or plural number. The terms "comprise", "include", "have" and any variations thereof involved in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may further include unlisted steps or units, or may further include other steps or units inherent to these processes, methods, products or devices. The words such as "connect", "be connected", "couple" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "plurality" involved in this application means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, "A and / or B" may represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the front and back associated objects. The terms "first", "second", "third" and the like involved in this application are only used to distinguish similar objects and do not represent a specific sorting of the objects.

[0035] As Figure 1 shown, an embodiment of this application further provides a semiconductor test board card, which is connected to a device under test 30 and includes a main control board 10 and a resource daughter board 20 detachably connected to the main control board 10 through a daughter board connector 210. The resource daughter board 20 includes: a first processor 230 and a parameter measurement unit 220 connected in sequence; the main control board 10 includes: a second processor 110, a logic switch circuit 130, and a calibration circuit 140 connected in sequence; the logic switch circuit 130 is connected to the device under test 30. The second processor 110 is connected to the first processor 230 and is used to receive a host computer instruction and then arbitrate and deliver it to the first processor 230, so that the first processor 230 controls the parameter measurement unit 220 to output a test signal to the device under test 30 through the logic switch circuit 130 and / or controls the parameter measurement unit 220 to measure the voltage and / or current at both ends of the device under test 30; the parameter measurement unit 220 is selectively connected to the logic switch circuit 130, so that the calibration circuit 140 calibrates the parameter measurement unit 220 to correct the deviation of the test signal output by the parameter measurement unit 220.

[0036] In this embodiment, both the main control board 10 and the resource daughter board 20 include a daughter board connector 210, and the daughter board connectors 210 are connected to each other to realize the connection between the main control board 10 and the resource daughter board 20. The resource daughter board 20 includes a first processor 230 and a parameter measurement unit 220.

[0037] After receiving the host computer instruction, the second processor 110 arbitrates and transfers it to the first processor 230. The first processor 230 controls the parameter measurement unit 220 to connect to the daughter board connector 210, and then outputs a test signal to the device under test 30 through the logic switch circuit 130, or controls the parameter measurement unit 220 to measure the voltage and / or current at both ends of the device under test 30. Of course, it is also possible to realize that the parameter measurement unit 220 outputs a test signal to the device under test 30, and measure the voltage and / or current at both ends of the device under test 30. The above operations are all determined by the host computer instruction received by the second processor 110. The main control board 10 is provided with a calibration circuit 140. The calibration circuit 140, the logic switch circuit 130 and the parameter measurement unit 220 are connected. The calibration of the parameter measurement unit 220 is realized through the calibration circuit 140, which is more convenient than the calibration method of external instruments and improves the calibration efficiency.

[0038] Furthermore, through the multiplexing of the logic switch circuit 130, it is possible to measure the voltage and / or current at both ends of the device under test 30 and calibrate the parameter measurement unit 220, thus simplifying the wiring.

[0039] Furthermore, the resource daughter board 20 is detachably connected to the main control board 10, which is convenient for the installation and disassembly of the resource daughter board 20.

[0040] Figure 2 It is a schematic diagram of the overall structure of the semiconductor test board in an embodiment. The following will be combined with Figure 2 to describe this device in detail.

[0041] In this embodiment, the main control board 10 includes a second processor 110, a switch control circuit 120, a logic switch circuit 130, and a calibration circuit 140. The switch control circuit 120 is connected to the second processor 110 and the logic switch circuit 130. The logic switch circuit 130 is connected to the daughter board connector 210 and is connected to the device under test 30 through the output connector. The calibration circuit 140 is connected to the second processor 110 and the logic switch circuit 130. The second processor 110 outputs a control signal through the switch control circuit 120 to control the logic switch circuit 130 to form a test loop or a calibration loop.

[0042] The main control board 10 further includes a health management module 160 and a second monitoring module. The health management module 160 and the second monitoring module are connected to the second processor 110. The second monitoring module is used to detect the second detection information of the main control board 10 and transmit it to the second processor 110. The health management module 160 obtains the second detection information from the second processor 110 to monitor the main control board 10 in real time.

[0043] Specifically, the second monitoring module includes a second temperature monitoring module 151 and a second power supply monitoring module 152. The second processor 110 obtains the second temperature information collected by the second temperature monitoring module 151 and the second power supply information collected by the second power supply monitoring module 152. The health management module 160 obtains the second temperature information and the second power supply information from the second processor 110 to monitor the main control board 10.

[0044] The main control board 10 further includes an on-board power supply 180. The on-board power supply 180 is connected to the second processor 110, the health management module 160, and is connected to an external power supply through a power connector, and is used to supply power to the second processor 110 and the health management module 160.

[0045] The health management module 160 is connected to the resource daughter board 20 and is also used for power-on and power-off control of the resource daughter board 20.

[0046] The main control board 10 may further include a second clock management module 170. The second clock management module 170 is connected to the second processor 110 and the resource daughter board 20, and is used to obtain an external clock signal and send it to the second processor 110 and the resource daughter board 20 for clock signal synchronization.

[0047] The resource daughter board 20 includes a daughter board connector 210, a parameter measurement unit 220, and a first processor 230. The first processor 230 controls the parameter measurement unit 220 to output a test signal to the device under test 30 through the logic switch circuit 130 according to a host computer instruction and / or controls the parameter measurement unit 220 to measure the voltage and / or current across the device under test 30.

[0048] The parameter measurement unit 220 has functions such as voltage application, voltage measurement, current application, and current measurement.

[0049] The resource daughter board 20 further includes a first monitoring module connected to the first processor 230. The first monitoring module is used to detect the first detection information of the resource daughter board 20 and transmit it to the first processor 230; the health management module 160 is connected to the first processor 230 through the daughter board connector 210 and is used to obtain the first detection information from the first processor 230 to monitor the resource daughter board 20 in real time.

[0050] Specifically, the first monitoring module includes a first temperature monitoring module 241 and a first power supply monitoring module 242.

[0051] The first processor 230 obtains the first temperature information collected by the first temperature monitoring module 241 and the first power supply information collected by the first power supply monitoring module 242. The health management module 160 obtains the first temperature information and the first power supply information from the first processor 230 to monitor the resource daughter board 20.

[0052] The resource daughter board 20 may further include a first clock management module 250 connected to the daughter board connector 210 and the first processor 230, configured to obtain the clock signal sent by the main control board 10 via the daughter board connector 210 and send it to the first processor 230.

[0053] The resource daughter board 20 further includes a power supply module 260 connected to the daughter board connector 210, the parameter measurement unit 220, the first power supply monitoring module 242, and the first processor 230, configured to obtain the power supply of the main control board 10 via the daughter board connector 210, and after voltage conversion, provide the required voltages for the parameter measurement unit 220, the first processor 230, and the first power supply monitoring module 242. The first power supply monitoring module 242 collects the first power supply information of the DC-DC power supply module 260. In this embodiment, the power supply module 260 is a DC-DC power supply. Of course, it is not limited thereto. For example, an LDO power supply can be used as long as it can provide the required voltages for the parameter measurement unit 220, the first processor 230, and the first power supply monitoring module 242.

[0054] The daughter board connector 210 is provided with a high-speed communication interface, a low-speed communication interface, a firmware download port, etc., for data interaction between the first processor 230 and the second processor 110. As Figure 3 shown, the logic switch circuit 130 includes three relays (HF_K, HS_K, LS_K). The first end of each relay is connected to the daughter board connector 210, the second end is connected to the device under test 30 via the output connector, and the third end is connected to the calibration module 141 via the calibration bus.

[0055] As Figure 3 shown, the parameter measurement unit 220 internally includes relays PMU_HF, PMU_HS, and PMU_LS. When the relays PMU_HF, PMU_HS, and PMU_LS are closed and the relays HF_K, HS_K, and LS_K are switched to the output connector, a test loop is formed to test the device under test 30. When the relays PMU_HF, PMU_HS, and PMU_LS are closed and the relays HF_K, HS_K, and LS_K are switched to the output calibration bus, a calibration circuit 140 is formed to calibrate the parameter measurement unit 220.

[0056] The parameter measurement unit 220 includes an error comparator U1, an integrator U2, an operational amplifier PA, a sampling resistor RL, a first differential amplifier U3, and a second differential amplifier U4. The first processor 230, the error comparator U1, the integrator U2, the operational amplifier PA, the sampling resistor RL, and the first differential amplifier U3 are connected to form a current feedback loop; the first processor 230, the error comparator U1, the integrator U2, the operational amplifier PA, the sampling resistor RL, the device under test 30, and the second differential amplifier U4 are connected to form a voltage feedback loop. The device under test 30 is connected to the sampling resistor RL and the second differential amplifier U4 via an output connector.

[0057] The parameter measurement unit 220 further includes a channel selection switch S1, one digital-to-analog converter DAC, two analog-to-digital converters ADC, and a grounding resistor RS connected to the second differential amplifier U4.

[0058] When the first processor 230 selects the first differential amplifier U3 to be connected through the channel selection switch S1, the error comparator receives the reference signal from the digital-to-analog converter DAC, outputs the reference signal to the integrator U2 after taking the difference, the integrator U2 outputs the reference signal to the operational amplifier PA after integral operation, the operational amplifier PA amplifies the power of the reference signal and outputs a current signal, the sampling resistor RL samples the current signal to obtain a voltage signal, and the subsequent first differential amplifier U3 is connected across the sampling resistor RL to inject the voltage signal into the error comparator U1 to take the difference of the voltage signal. When the output of the error comparator U1 is 0, the output of the integrator U2 is also 0, and at this time, the current reaches a steady state. At the same time, the output signal of the first differential amplifier U3 can also be sampled by the analog-to-digital converter ADC.

[0059] When the first processor 230 selects the second differential amplifier U4 to be connected through the channel selection switch S1, the second differential amplifier U4 is connected to two interfaces of the output connector, takes the difference of the voltage signals at the two interfaces of the output connector and converts them into a voltage feedback signal, which is reinjected into the error comparator U1 for taking the difference. When the output of the error comparator U1 is 0, the output of the integrator U2 is also 0, and at this time, the voltage reaches a steady state. At the same time, the output signal of the second differential amplifier U4 can also be sampled by the analog-to-digital converter ADC.

[0060] The calibration circuit 140 includes at least one calibration module 141. The calibration module 141 is connected to the instrument bus and then accesses an external instrument through a backplane connector. The parameter measurement unit 220 includes at least one parameter measurement module 221. Calibration of the calibration circuit 140 can be achieved through an external instrument.

[0061] In an exemplary embodiment, as Figure 4 shown, the calibration circuit 140 includes two calibration modules 141, and the parameter measurement unit 220 includes multiple parameter measurement modules 221 (Figure 4 Only 2 are shown. Two calibration modules 141 are connected in parallel to the instrument bus via two calibration buses (DCC_BUS1, DCC_BUS2). Two parameter measurement modules 221 are respectively connected to the two calibration buses. A switch for controlling the access of one calibration bus is also provided on the instrument bus.

[0062] The instrument bus is connected to an external instrument via a backplane connector. The external instrument calibrates the two calibration modules by acquiring the two calibration signals of the two calibration buses.

[0063] In one embodiment, an embodiment of the present application provides a semiconductor test device, including a communication board and a semiconductor test board as described in the above embodiment connected to the communication board.

[0064] Since the semiconductor test device includes the semiconductor test board in the above embodiment, it can solve the same technical problems and achieve the same technical effects, which will not be elaborated here.

[0065] In one embodiment, an embodiment of the present application provides a test system, the system including a host computer and a semiconductor test device as described in the above embodiment communicatively connected to the host computer.

[0066] Since the test system includes the semiconductor test device in the above embodiment, it can solve the same technical problems and achieve the same technical effects, which will not be elaborated here.

[0067] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0068] The above embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the utility model patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A semiconductor test board connected to a device under test, characterized in that: It comprises a main control board and a resource sub-board detachably connected to the main control board through a sub-board connector, wherein the resource sub-board comprises: a first processor and a parameter measurement unit connected in sequence; the main control board comprises: a second processor, a logic switch circuit, and a calibration circuit connected in sequence; the logic switch circuit is respectively connected to the sub-board connector and the device under test; The second processor is connected to the first processor and is used for receiving a command from a host computer and then transmitting the command to the first processor through arbitration, so that the first processor controls the parameter measurement unit to output a test signal to the device under test through the logic switch circuit and / or controls the parameter measurement unit to measure the voltage and / or current at both ends of the device under test; The parameter measurement unit is selectively connected to the logic switch circuit so that the calibration circuit calibrates the parameter measurement unit to correct the deviation of the test signal output by the parameter measurement unit.

2. The semiconductor test board according to claim 1, characterized in that: The main control board also includes a health management module connected to the second processor; the resource sub-board also includes a first monitoring module connected to the first processor; The first monitoring module is used to detect first detection information of the resource sub-board and transmit the first detection information to the first processor; The health management module is connected to the first processor via the daughter board connector, and is used to obtain the first detection information and monitor the resource daughter board in real time.

3. The semiconductor test board according to claim 2, characterized in that: The main control board also includes a second monitoring module connected to the second processor; The second monitoring module is used to detect second detection information of the main control board and transmit the second detection information to the second processor; The health management module is further used to obtain the second detection information and monitor the main control board in real time.

4. The semiconductor test board according to claim 3, characterized in that: The first monitoring module includes a first temperature monitoring module and a first power monitoring module connected to the first processor, and / or the second monitoring module includes a second temperature monitoring module and a second power monitoring module connected to the second processor.

5. The semiconductor test board according to claim 1, characterized in that: The logic switch circuit includes a plurality of relays, wherein a first end of each of the relays is connected to the daughter board connector, a second end is connected to the device under test, and a third end is connected to the calibration circuit.

6. The semiconductor test board according to claim 1, characterized in that: The calibration circuit includes at least one calibration module, which is connected to an instrument bus and then connected to an external instrument; when the calibration circuit includes at least two calibration modules, the at least two calibration modules are connected in parallel.

7. The semiconductor test board according to claim 1, characterized in that: The parameter measurement unit includes an error comparator, an integrator, an operational amplifier, a sampling resistor, a first differential amplifier, and a second differential amplifier; The first processor, the error comparator, the integrator, the operational amplifier, the sampling resistor, and the first differential amplifier are connected to form a current feedback loop; The first processor, the error comparator, the integrator, the operational amplifier, the sampling resistor, the device under test, and the second differential amplifier are connected to form a voltage feedback loop.

8. The semiconductor test board according to claim 1, characterized in that: The main control board also includes a second clock management module connected to the daughter board connector and the second processor, which is used to obtain an external clock signal and send it to the second processor and the resource daughter board to synchronize the clock signal; And / or, the resource daughter board also includes a first clock management module connected to the daughter board connector and the first processor, which is used to obtain the clock signal sent by the main control board through the daughter board connector and send it to the first processor.

9. A semiconductor testing device, characterized in that: The invention comprises a communication board and a semiconductor test board card as claimed in any one of claims 1 to 8 connected to the communication board.

10. A testing system, characterized in that: The system includes a host computer and the semiconductor testing device as claimed in claim 9 which is communicatively connected to the host computer.

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