Circuit and system for chip debugging and computer

Abstract

The utility model relates to the technical field of chip debugging, and discloses a circuit, a system and a computer for chip debugging, which comprise a switch module, a chip to be debugged, a platform path controller and a universal interface, the switch module is respectively connected with the chip to be debugged, the platform path controller and the universal interface; and the chip to be debugged is also connected with the platform path controller and the universal interface. The switch module is respectively connected with the to-be-debugged chip, the platform path controller and the universal interface, and the connection among the to-be-debugged chip, the platform path controller and the universal interface can be changed through the switch module, so that the to-be-debugged chip can be directly debugged through the universal interface under the condition that a machine is not disassembled.

Description

Technical Field

[0001] The utility model relates to the technical field of chip debugging, in particular to a circuit, a system and a computer for chip debugging. Background Art

[0002] In the field of computers, if an engineer wants to debug chips on the motherboard of a whole computer, such as EC (Embedded Controller), BMC (Baseboard Management Controller), superIO (Super Input / Output) chip, and PD (Power Management) chip, etc., the following general steps are usually required: First is the preparation stage, ensuring there are appropriate debugging tools, such as a programmer, an oscilloscope, a multimeter, etc.; preparing flying wires and tiny soldering tools for connecting the debugging interface; second is disassembly and positioning, opening the case of a laptop or server and taking out the motherboard; accurately positioning the chips to be debugged, which are usually located at key positions on the motherboard, for example, the EC chip is often near the keyboard interface, and the BMC chip is associated with the network interface; then it is necessary to lead out the debugging interface. For chips with a debugging interface, directly connect the debugging tool. If there is no ready-made interface, it is necessary to connect specific pins of the chip (such as debugging pins, including but not limited to IIC interface / UART interface / SWD interface / JTAG interface) to the debugging adapter or programmer through fine flying wires; leading out the debugging interface requires delicate operations to avoid damaging the motherboard or the chip; after leading out the debugging interface is the debugging process, which requires using special software or hardware tools to communicate with the chip to read or write the firmware of the chip; for chips such as EC and BMC, serial communication may be required for debugging, while the superIO chip may involve controlling an analog old I / O device; the debugging of the PD chip may involve adjusting the power management strategy and requires specific software tools for configuration; finally is safety and testing. After debugging, recheck all connections to ensure that no flying wires that may cause a short circuit are left; then reinstall the motherboard and test whether the system works properly to avoid introducing new problems due to the debugging operation.

[0003] However, the above steps are very cumbersome. The engineer needs to first disassemble the computer (such as a laptop), then take out the motherboard, and then lead out the debugging interface of the chip to be debugged in the motherboard through flying wires for debugging. Besides being cumbersome, it also requires the engineer to have strong soldering and hands-on skills; and during the disassembly process, the whole machine may be damaged or depreciated severely; during the flying wire process, there is also a high probability of irreversibly damaging the components on the motherboard, resulting in economic losses.

[0004] Therefore, there is a need to provide a circuit, a system and a computer for chip debugging that can reduce the damage to the whole computer during debugging and are convenient. Summary of the Utility Model

[0005] To solve the above problems, the present utility model proposes a circuit, a system and a computer for chip debugging.

[0006] In a first aspect, the present utility model proposes a circuit for chip debugging, comprising: a switch module, a chip to be debugged, a platform path controller and a general-purpose interface;

[0007] The switch module is respectively connected to the chip to be debugged, the platform path controller and the general-purpose interface;

[0008] The chip to be debugged is also connected to the platform path controller and the general-purpose interface.

[0009] Preferably, the first input terminal and the second input terminal of the switch module are both connected to the chip to be debugged and the platform path controller, the output terminal is connected to the general-purpose interface, and the enable terminal and the control signal input terminal are both connected to the chip to be debugged.

[0010] Preferably, the first sub-input terminal of the first input terminal of the switch module is connected to the first debugging interface of the chip to be debugged, the second sub-input terminal of the first input terminal is connected to the first signal terminal of the platform path controller, the third sub-input terminal of the second input terminal is connected to the second debugging interface of the chip to be debugged, and the fourth sub-input terminal of the second input terminal is connected to the second signal terminal of the platform path controller;

[0011] The first sub-output terminal of the output terminal of the switch module is connected to the first signal terminal of the general-purpose interface, and the second sub-output terminal of the output terminal is connected to the second signal terminal of the general-purpose interface;

[0012] The first sub-input terminal and the second sub-input terminal of the switch module are both connected to the first sub-output terminal, and the third sub-input terminal and the fourth sub-input terminal are both connected to the second sub-output terminal.

[0013] Preferably, the general-purpose interface includes a general-purpose female socket.

[0014] Preferably, the switch module and the chip to be debugged are also connected to a working power supply.

[0015] Preferably, the chip to be debugged is also connected to a cover sensor.

[0016] In a second aspect, the present utility model proposes a system for chip debugging, comprising the circuit for motherboard debugging according to any one of the first aspect and a debugging module; the debugging module is connected to the general-purpose interface

[0017] In a third aspect, the present utility model provides a computer, including the circuit for motherboard debugging described in any one of the first aspects.

[0018] Compared with the prior art, the circuit for chip debugging disclosed by the present utility model connects the switch module to the chip to be debugged, the platform path controller, and the general interface respectively. The connection between the chip to be debugged, the platform path controller, and the general interface can be changed through the switch module, so that the chip to be debugged can be directly debugged through the general interface without disassembling the machine. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present utility model. Moreover, throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0020] Figure 1 is a schematic diagram of a circuit for chip debugging provided by the present utility model;

[0021] Figure 2 is a schematic diagram of the switch module of a circuit for chip debugging provided by the present utility model;

[0022] Figure 3 is a connection schematic diagram of the switch module of a circuit for chip debugging provided by the present utility model;

[0023] Figure 4 is a schematic diagram of another circuit for chip debugging provided by the present utility model;

[0024] Figure 5 is a schematic diagram of a system of a circuit for chip debugging provided by the present utility model;

[0025] Figure 6 is a schematic diagram of the debugging module of a system for chip debugging provided by the present utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] The following further describes the exemplary embodiments of the present utility model with reference to the drawings. Although the exemplary embodiments of the present utility model are shown in the drawings, it should be understood that the present utility model can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present utility model and to fully convey the scope of the present utility model to those skilled in the art.

[0027] The embodiments of the present utility model will be described in detail below with reference to the drawings.

[0028] In a first aspect, as Figure 1 shown, the present utility model proposes a circuit for chip debugging, including: a switch module, a chip to be debugged, a platform path controller, and a general-purpose interface. The switch module 100 is respectively connected to the chip to be debugged 200, the platform path controller 300, and the general-purpose interface 400. The chip to be debugged 200 is also connected to the platform path controller 300 and the general-purpose interface 400.

[0029] As Figure 2 shown, the first input terminal 101 and the second input terminal 102 of the switch module 100 are both connected to the chip to be debugged 200 and the platform path controller (Platform Controller Hub, PCH) 300, the output terminal 103 is connected to the general-purpose interface, and the enable terminal EN and the control signal input terminal IN are both connected to the chip to be debugged 200.

[0030] As Figure 3 shown, the first sub-input terminal 101A of the first input terminal 101 of the switch module 100 is connected to the first debug interface 201 of the chip to be debugged 200, the second sub-input terminal 101B of the first input terminal is connected to the first signal terminal D+ of the platform path controller 300, the third sub-input terminal 102A of the second input terminal 102 is connected to the second debug interface 202 of the chip to be debugged 200, and the fourth sub-input terminal 102B of the second input terminal 102 is connected to the second signal terminal D- of the platform path controller 300.

[0031] The first sub-output terminal 103A of the output terminal 103 of the switch module 100 is connected to the first signal terminal D+ of the general-purpose interface 400, and the second sub-output terminal 103B of the output terminal 103 is connected to the second signal terminal D- of the general-purpose interface 400.

[0032] The first sub-input terminal 101A and the second sub-input terminal 101B of the switch module 100 are both connected to the first sub-output terminal 103A, and the third sub-input terminal 102A and the fourth sub-input terminal 102B are both connected to the second sub-output terminal 103B.

[0033] Among them, the switch module 100 may include any switch chip that can implement a single-pole double-throw function. The decoding and driving unit 104 in the switch module 100 controls the conduction and disconnection between the sub-input terminals and the sub-output terminals according to the signals received by the enable terminal EN and the control signal input terminal IN, so as to realize the selection of two paths for output from the four paths of input.

[0034] As Figure 3As shown in the figure, the general interface 400 includes a general female socket 401. Among them, the general interface 400 may include a USB interface, such as USB type-A, USB type-C, etc. The general female socket 401 may include the female socket of the USB interface. The first signal terminal D+ of the general female socket 401 is connected to the first sub-output terminal 103A of the output terminal of the switch module 100, and the second signal terminal D- of the general female socket 401 is connected to the second sub-output terminal 103B of the output terminal of the switch module 100.

[0035] The switch module 100 and the chip to be debugged 200 are also connected to the working power supply. The working power supply can be 3.3V.

[0036] The switch module 100, the chip to be debugged 200, the platform path controller 300, and the general interface 400 are also connected to the ground terminal GND.

[0037] The chip to be debugged is also connected to a Lid sensor.

[0038] Next, taking the chip to be debugged 200 in a laptop computer (the whole computer) 10 as an example, the embodiments of the present application will be described in detail, as Figure 4 shown.

[0039] When it is necessary to debug the chip (the chip to be debugged 200) in the laptop computer, a common magnet is brought close to the Lid sensor of the laptop computer, that is, the action of closing the laptop computer is simulated. At this time, the power-on button is pressed and held for 3 seconds and then released. The chip to be debugged 200 receives the signal sent by the Lid sensor through the pin connected to the Lid sensor, such as the LID_INT pin, and the chip to be debugged 200 receives the signal sent by the power-on button through the pin connected to the power-on button, such as the PWRBTN_IN pin. When the chip to be debugged 200 detects the triggering actions of receiving signals on these two pins and finds that the state is the non-debugged state, the chip to be debugged 200 switches the connection of the switch unit 100; connects the first sub-input terminal 101A to the first sub-output terminal 103A, and connects the third sub-input terminal 102A to the second sub-output terminal 103B, so that the first signal terminal D+ of the general female socket 401 of the general interface 400 is connected (conducted) to the first debug interface 201 of the chip to be debugged 200 through the first sub-output terminal 103A of the switch module 100, and the second signal terminal D- of the general female socket 401 is connected (conducted) to the second debug interface 202 of the chip to be debugged 200 through the second sub-output terminal 103B of the switch module 100. At the same time, the connection between the first signal terminal D+ and the second signal terminal D- of the platform path controller 300 and the first signal terminal D+ and the second signal terminal D- of the general female socket 401 is disconnected.

[0040] After that, connect the debugging device (such as a debugger) 20 used to debug the chip 200 to be debugged to the general socket 401, then the debugging interface of the chip 200 to be debugged can be conveniently led out from the general socket 401 and connected to the debugger for debugging. Among them, the debugging device 20 used to debug the chip 200 to be debugged includes a general male head 21 corresponding to the general socket 401 and a debugger body 22. The debugger body 22 is connected to the general socket 401 through the first debugging interface 21A of the general male head 21, and is connected to the general socket 401 through the second debugging interface 21B of the general male head 21. The ground interface GND of the general male head 21 is connected to the ground interface GND of the debugger body 22.

[0041] When the debugging is over, disconnect the connection between the device (such as a debugger) used to debug the chip 200 to be debugged and the general socket 401. Then bring an ordinary magnet close to the lid sensor of the laptop, that is, simulate the action of closing the laptop lid. At this time, press and hold the power-on button for 3 seconds and then release it. After the chip 200 to be debugged detects the triggering actions of these two signals and finds that the state is the debugging state, the chip 200 to be debugged switches the connection of the switching unit 100; connects the second sub-input terminal 101B to the first sub-output terminal 103A, and connects the fourth sub-input terminal 102B to the second sub-output terminal 103B, so that the first signal terminal D+ of the general socket 401 of the general interface 400 is connected (conducted) to the first signal terminal D+ of the platform path controller 300 through the first sub-output terminal 103A of the switching module 100, and the second signal terminal D- of the general socket 401 is connected (conducted) to the second signal terminal D- of the platform path controller 300 through the second sub-output terminal 103B of the switching module 100. At the same time, the connections between the first debugging interface 201 and the second debugging interface 202 of the chip 200 to be debugged and the first signal terminal D+ and the second signal terminal D- of the general socket 401 are disconnected, and the function of the general interface 400 of this laptop returns to normal. The debugging state and the non-debugging state can be determined by means such as the current conduction state of the switching module 100, the signal output by the chip 200 to be debugged to the control signal input terminal of the switching module 100, and the current state of the chip 200 to be debugged. The chip 200 to be debugged and the switching module 100 are also connected to the working power supply +V3P3A.

[0042] The above method of determining the debugging state by detecting the triggering actions of the signals received by the LID_INT pin and the PWRBTN_IN pin is only an exemplary embodiment of the present application. This embodiment does not specifically limit the signals of the triggering actions, as long as the functions of the triggering actions can be achieved.

[0043] In a second aspect, the present utility model proposes a system for chip debugging, such as Figure 5As shown, it includes the circuit for motherboard debugging described in any one of the first aspects and a debugging module 500; the debugging module 500 is connected to the general interface 400.

[0044] Among them, the debugging module 500 includes a general interface unit 501 and a debugger body. The general interface unit 501 is used to connect to the general interface 400. The general interface unit 501 includes a general male head 511 corresponding to the corresponding general female socket 401, such as the male head of USB type-A, USB type-C, etc.

[0045] Such as Figure 6 As shown, the first debugging interface 511A of the general male head 511 of the debugging module 500 is connected to the first debugging interface 401A of the general female socket 401, the second debugging interface 511B of the general male head 511 is connected to the second debugging interface 401B of the general female socket 401, and the ground interface GND of the general male head 511 is connected to the ground interface GND of the general female socket 401.

[0046] In the third aspect, the present invention proposes a computer, including the circuit for motherboard debugging described in any one of the first aspects.

[0047] The benefits of this embodiment are that the switch module is respectively connected to the chip to be debugged, the platform path controller, and the general interface. The connection between the chip to be debugged, the platform path controller, and the general interface can be changed through the switch module, so that it is possible to directly debug the chip to be debugged through the general interface without disassembling the machine. There are general interfaces on existing computer integrations, such as USB interfaces. Through the switch module, the two signal lines of the first signal terminal D+ and the second signal terminal D- of the general interface can be switched with the signal lines of the two debugging interfaces of the chip to be debugged on the motherboard, realizing the debugging of the chip to be debugged on the motherboard without disassembling the whole machine or flying wires. Thus, the chip on the computer motherboard can be quickly and conveniently debugged through the general interface. Changing the connection between the chip to be debugged, the platform path controller, and the general interface through the switch module to debug the chip to be debugged without disassembling the whole machine or flying wires will not only cause damage to the whole machine, affect the sale of the whole machine, but also cause damage to the components on the motherboard, and will not cause economic losses.

[0048] What is described above in this specification is only an example of the present invention. Those skilled in the technical field to which the present invention belongs can make various modifications or supplements to the described specific embodiments or use similar methods for substitution, as long as they do not deviate from the content of the specification of the present invention or exceed the scope defined by this claim book, they should all belong to the protection scope of the present invention.

Claims

1. A circuit for chip debugging, characterized in that: include: Switch module, chip to be debugged, platform path controller and general interface; The switch module is connected to the chip to be debugged, the platform path controller and the universal interface respectively; The chip to be debugged is also connected to the platform path controller and the universal interface.

2. The circuit according to claim 1, characterized in that The first input terminal and the second input terminal of the switch module are both connected to the chip to be debugged and the platform path controller, the output terminal is connected to the universal interface, and the enable terminal and the control signal input terminal are both connected to the chip to be debugged.

3. The circuit according to claim 2, characterized in that The first sub-input end of the first input end of the switch module is connected to the first debugging interface of the chip to be debugged, the second sub-input end of the first input end is connected to the first signal end of the platform path controller, the third sub-input end of the second input end is connected to the second debugging interface of the chip to be debugged, and the fourth sub-input end of the second input end is connected to the second signal end of the platform path controller; The first sub-output end of the output end of the switch module is connected to the first signal end of the universal interface, and the second sub-output end of the output end is connected to the second signal end of the universal interface; The first sub-input terminal and the second sub-input terminal of the switch module are both connected to the first sub-output terminal, and the third sub-input terminal and the fourth sub-input terminal are both connected to the second sub-output terminal.

4. The circuit according to claim 1, characterized in that The universal interface includes a universal female socket.

5. The circuit according to claim 1, characterized in that The switch module and the chip to be debugged are also connected to a working power supply.

6. The circuit according to claim 1, characterized in that The chip to be debugged is also connected to a cover sensor.

7. A system for chip debugging, characterized in that: It comprises a circuit and a debugging module for mainboard debugging as described in any one of claims 1 to 6; the debugging module is connected to the universal interface.

8. A computer, characterized in that: The invention comprises a circuit for mainboard debugging as claimed in any one of claims 1 to 6.

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