Simulation performance acceleration co-processing daughter card in PCIe form

Abstract

The utility model discloses a PCIe-form simulation performance acceleration co-processing daughter card, and relates to the technical field of hardware simulation. The co-processing daughter card comprises a processor module used for task scheduling and data flow control; the storage module is electrically connected with the processor module and is used for temporarily storing and caching simulation data; the communication module is electrically connected with the processor module and used for data transmission; and the interface module is electrically connected with the processor module and is used for connecting external equipment. The co-processing daughter card is installed in a PCIe slot of a main board of a host system, provides a corresponding hardware platform for simulation, has obvious advantages in scenes requiring high precision, high performance and underlying hardware support, can more accurately simulate and execute behaviors of a hardware instruction set, has higher precision and authenticity, and can be widely applied to the field of hardware simulation. Lower delay and higher real-time response capability can be provided; in addition, an isolation and control environment can be provided, and influences or risks cannot be caused to a real system.

Description

Technical Field

[0001] The utility model relates to the technical field of hardware simulation, and particularly relates to a simulation performance acceleration coprocessor sub-card in the form of PCIe. Background Art

[0002] With the needs of production and life, various processor architectures and instruction sets have been developed in different industries and scenarios, including x86, ARM, PowerPC, MIPS, and SPARC, etc. Various instruction sets are also constantly evolving and optimizing to adapt to new requirements and market trends. Instruction set simulation provides effective solution and tool support for cross-platform development and testing, old hardware support, education and research, old system maintenance, and security testing, etc., and has important application value in various scenarios. The common methods of instruction set simulation mainly include: dynamic binary translation, interpreter, static binary conversion, simulator, hardware-assisted simulation, etc.

[0003] The existing instruction set simulation method is to simulate and execute the instruction set of another instruction set architecture on a processor or computer system. It is limited to the software level. Instruction set simulation provides important help in cross-platform development and testing, education and research, and old hardware support, etc., but there are still some challenges and limitations in terms of performance, accuracy, real-time performance, and security, etc. Content of the Utility Model

[0004] In order to solve the problems of the existing technology, the utility model provides a simulation performance acceleration coprocessor sub-card in the form of PCIe. The coprocessor sub-card is in the form of a PCIe board and is installed in the PCIe slot of the mainboard of the host system. The coprocessor sub-card includes:

[0005] A processor module, which is used for task scheduling and data flow control;

[0006] A storage module, which is electrically connected to the processor module and is used for temporarily storing and caching simulation data;

[0007] A communication module, which is electrically connected to the processor module and is used for data transmission;

[0008] An interface module, which is electrically connected to the processor module and is used for connecting external devices.

[0009] Furthermore, the communication module is a two-way network module;

[0010] One of the network modules is used to convert the PCIe signal of the host system into a network, and the other network module is used to convert the PCIe signal of the processor module into a network. The two network signals are docked to complete data transmission.

[0011] Further, the network module is a PCIe to 40G network module.

[0012] Further, the interface module includes:

[0013] A USB interface for connecting a mouse, a keyboard, and a USB flash drive;

[0014] An indicator interface for connecting an indicator to indicate the power supply and operating status of the coprocessor daughter card;

[0015] A network interface for connecting to an external network device for debugging and data transmission and reception;

[0016] A video interface for connecting to a display device.

[0017] Further, the processor module architecture is any one of the x86, ARM, PowerPC, MIPS, and SPARC architectures.

[0018] The beneficial effects of the technical solution provided by the present utility model are as follows: In the present utility model, the coprocessor daughter card includes a processor module, a storage module, a communication module, and an interface module, and is installed in the PCIe slot of the host system motherboard. As a coprocessor of the host system, it provides a corresponding hardware platform for simulation, and has obvious advantages in scenarios that require high precision, high performance, and underlying hardware support. It can not only accelerate the hardware development and testing processes, but also provide a more realistic and actual-hardware-close simulation environment, thereby helping developers more effectively develop, optimize, and test application programs; and can more precisely simulate and execute the behavior of the hardware instruction set, with higher precision and authenticity, and can provide lower latency and higher real-time response capabilities; in addition, it can provide an isolated and controlled environment. Compared with testing on real hardware, hardware simulation will not affect or pose risks to the real system. Description of the Drawings

[0019] Figure 1 is a schematic structural diagram of a component composition diagram of a host system provided by the present utility model;

[0020] Figure 2 is a composition diagram of a simulation performance acceleration coprocessor daughter card in the form of PCIe provided by the present utility model.

[0021] Reference numerals: 1 - host system chassis; 2 - coprocessor daughter card; 3 - host system motherboard; 4 - processor module; 5 - storage module; 6 - communication module; 7 - interface module. Detailed Embodiments

[0022] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0023] To make the objectives, technical solutions, and advantages of the present utility model clearer, the embodiments of the present utility model will be further described in detail below in conjunction with the accompanying drawings.

[0024] It should be noted that in this embodiment, the orientation or positional relationship indicated by "bottom", "top", "left", "right", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application. In addition, the terms "first", "second", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0025] It should also be noted that in this embodiment, unless otherwise clearly specified and defined, the terms "set" and "connect" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0026] See Figure 1 and Figure 2 , a simulation performance acceleration coprocessor sub-card in the form of PCIe, including: a processor module 4, a storage module 5, a communication module 6, and an interface module 7. This coprocessor sub-card is in the form of a PCIe board card and is installed in the PCIe slot of the host system motherboard 3. As a coprocessor of the host system, it provides a corresponding hardware platform for simulation and is used to accelerate the calculation and processing of complex simulation tasks.

[0027] Among them, the architecture of the processor module 4 is any one of the x86, ARM, PowerPC, MIPS, and SPARC architectures. The processor module 4 is responsible for co-processing task scheduling and data flow control within the daughter card, and effectively utilizes each functional module. The storage module 5 is electrically connected to the processor module 4 and is used for temporarily storing and caching simulation data, reducing frequent data exchanges with the host system, and improving processing efficiency. The communication module 6 is electrically connected to the processor module and the host system. The communication module 6 is a two-way PCIe to 40G network module. One way converts the PCIe signal of the host system into a network, and the other way converts the PCIe signal of the processor module of the co-processing daughter card into a network. The two network signals are docked to complete data transmission. Its 40G bandwidth can meet the real-time requirement of data transmission. The host system sends the data, instructions, software, etc. required for simulation to the co-processing daughter card 2 through PCIe. The co-processing daughter card 2 performs simulation processing. The temporarily stored and cached simulation data generated during simulation is stored in the storage module 5. After the simulation is completed, the simulation results and data are sent to the host system through PCIe.

[0028] The interface module 7 is electrically connected to the processor module 4. The interface module 7 serves as the peripheral interface of the co-processing daughter card and includes a USB interface, an indicator light interface, a network interface, a video interface, etc., and can be connected to external devices for use as an independent system. The USB interface is used to connect a mouse, a keyboard, and a USB flash drive. The indicator light interface is used to connect an indicator light to indicate the power supply and operating status of the co-processing daughter card. The network interface is used to connect to external network devices for debugging and data sending and receiving. The video interface is used to connect to a display device.

[0029] It should be noted that this co-processing daughter card provides a corresponding hardware platform for simulation and has obvious advantages in scenarios that require high precision, high performance, and underlying hardware support. It can not only accelerate the hardware development and testing process, but also provide a more real and actual-hardware-like simulation environment, thereby helping developers to develop, optimize, and test application programs more effectively. Hardware instruction set simulation can more accurately simulate and execute the behavior of hardware instruction sets, with higher precision and authenticity, and can provide lower latency and higher real-time response capabilities. It directly utilizes the execution capabilities of the underlying hardware, can provide higher performance, and can simulate and support all functions and features of specific hardware instruction sets, including processor-level operations, memory access, and I / O control, etc. Hardware simulation can provide an isolated and controllable environment. Compared with testing on real hardware, hardware simulation will not cause any impact or risk to the real system.

[0030] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A PCIe-based simulation performance acceleration co-processing daughter card, characterized in that: The co-processing daughter card is in the form of a PCIe card, installed in a PCIe slot of a host system motherboard, and the co-processing daughter card includes: Processor module for task scheduling and data flow control; A storage module, electrically connected to the processor module, for temporarily storing and caching simulation data; A communication module, electrically connected to the processor module, for data transmission; The interface module is electrically connected to the processor module and is used to connect to external devices.

2. The PCIe-based simulation performance acceleration co-processing daughter card according to claim 1, characterized in that: The communication module is a two-way network module; One of the network modules is used to convert the PCIe signal of the host system into the network, and the other network module is used to convert the PCIe signal of the processor module into the network. The two network signals are connected to complete the data transmission.

3. The PCIe-based simulation performance acceleration co-processing daughter card according to claim 2, characterized in that: The network module is a PCIe to 40G network module.

4. The PCIe-based simulation performance acceleration co-processing daughter card according to claim 1, characterized in that: The interface module comprises: USB interface, used to connect mouse, keyboard, and USB flash drive; The indicator light interface is used to connect the indicator light to indicate the power supply and operation status of the co-processing daughter card; Network interface, used to connect external network devices for debugging and data transmission and reception; Video interface, used to connect display devices.

5. The PCIe-based simulation performance acceleration co-processing daughter card according to any one of claims 1 to 4, characterized in that: The processor module architecture is any one of x86, ARM, PowerPC, MIPS and SPARC architectures.

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