Zero-sensing closed-loop phase modulation system device of low-voltage power distribution network

Abstract

The utility model discloses a zero-sensing closed-loop phase modulation system device of a low-voltage power distribution network. The zero-sensing closed-loop phase modulation system device comprises a main control chip U1, a protection circuit U3, a thyristor Q1, a magnetic latching relay KA1 and a magnetic latching relay KA2, the main control chip controls the thyristor Q1, the magnetic latching relay KA1 and the magnetic latching relay KA2; the current transformer obtains current IA during phase line commutation and inputs the current IA to the protection circuit U3, and the current IA is output to the main control chip U1 after gain stabilization of the current IA through the protection circuit U3; the thyristor Q1 is connected with the magnetic latching relay KA2 in series and then connected with the magnetic latching relay KA1 in parallel to form a parallel branch, and the phase line is connected with the load through the parallel branch. When the equipment has a commutation demand, the on-off of the equipment is controlled through the single-chip microcomputer so as to obtain different current values, and the current values are converted into corresponding voltage values through the circuit for monitoring, thereby achieving the effect of protecting each piece of equipment.

Description

Technical Field

[0001] The utility model relates to the technical field of power distribution, in particular to a zero-sensing closed-loop phase modulation system device and a control method for a low-voltage distribution network. Background Technique

[0002] With the acceleration of the industrialization and urbanization processes, the power demand in China continues to grow, posing higher requirements for the stability and reliability of the power system. Three-phase imbalance is one of the reasons that cause relatively serious power losses. Three-phase imbalance will cause uneven current distribution, resulting in a decline in the capacity and efficiency of the power system. Unbalanced current will cause power equipment to be overloaded, shorten the service life of the equipment, and even cause equipment failures.

[0003] There have been many research results on intelligent phase-changing systems at home and abroad. Classified by whether they have the function of short-circuit protection, there are mainly two categories: predicting in advance whether the device is controlled and the system performing feedback operations after the device is not controlled; the method of predicting in advance whether the device is controlled mainly uses voltage detection; the system performing feedback operations after the device is not controlled mainly uses power outage. Classified by whether they have a unified control phase-changing algorithm, they are mainly divided into two categories: multiple times, high balance degree and few times, low balance degree; the algorithms with multiple times and high balance degree mainly include multi-objective algorithms, serialization-based algorithms, etc.; the algorithms with few times and low balance degree include improved pigeon flock algorithms, etc. Classified by whether they have a load data storage method, there are mainly two categories: internal storage in the host and storage in the upper computer; the internal storage method in the host is mainly determined by the internal memory module, and the storage method in the upper computer is mainly determined by the internal memory module in the upper computer.

[0004] For example, an intelligent phase-changing switch with a short-circuit protection mechanism disclosed in Chinese Patent Publication No. CN117081551A designs an intelligent phase-changing switch with a short-circuit protection mechanism by using the characteristics of IGBT modules. This device only conducts short-circuit protection tests on the machine switches of the equipment. For example, when the equipment is in the process of phase change between phase A and phase B, if the IGBT device in the detection circuit is not damaged, there may be a voltage detection value that allows the equipment to operate normally, which may lead to a short-circuit accident.

[0005] Another example is a three-phase load automatic balancing system for low-voltage substations disclosed in Chinese Patent Publication No. CN206442118U, which uses DSP series chips as the MCU and simultaneously uses GPRS as the communication method to make a system with a unified control algorithm. The algorithm used in this device belongs to the medium phase-changing times and medium balance degree algorithm. Although it can meet the requirements of the equipment, it has high requirements for the performance of DSP, high equipment loss, and the adjustment of the balance degree does not reach the best effect. At the same time, the GPRS communication used by this device has high costs, high power consumption, and requires an authorized frequency band and other disadvantages, and cannot meet the requirements of some relatively special areas. Summary of the Invention

[0006] The technical problem to be solved by the utility model is to provide a zero-sensing closed-loop phase-adjusting system device for a low-voltage distribution network, to make up for the problem that the existing phase-changer device does not have self-checking of the device itself.

[0007] To solve the above technical problem, the technical solution of the utility model is: a zero-sensing closed-loop phase-adjusting system device for a low-voltage distribution network, including a main control chip U1, a protection circuit U3, a thyristor Q1, a magnetic latching relay KA1 and a magnetic latching relay KA2; the main control chip controls the thyristor Q1, the magnetic latching relay KA1 and the magnetic latching relay KA2; the current transformer obtains the current IA during the phase change of the phase line and inputs it to the protection circuit U3, and the current IA is output to the main control chip U1 after passing through the protection circuit U3; the thyristor Q1 and the magnetic latching relay KA2 are connected in series and then connected in parallel with the magnetic latching relay KA1 to form a parallel branch, and the phase line is connected to the load through the parallel branch. The principle of the utility model: Taking the example of changing from phase A to phase B, in the early stage of equipment access, the primary voltage will be obtained through AD acquisition. Since only KA1 is connected to phase A, there is no current in the circuit of KA2 and thyristor Q1 itself, so the protection circuit can output a voltage close to 0V. In the early stage of equipment phase change, the circuit of KA2 and thyristor Q1 will be turned on. Since it is impossible for the circuits of KA2 and thyristor Q1 to be damaged at the same time, according to the theoretical principle of AD detection and circuit, because there is a relatively high tube voltage drop in the circuit with thyristor Q1, the voltage collected by the protection circuit at this time is almost 0V. After the circuit with thyristor Q1 is completely closed, KA1 will be disconnected. If the voltage remains 0V unchanged, it means that KA1 has not been normally disconnected, and the device will return to the main interface and give an alarm; if the voltage is greater than 1.65V, it means that KA1 has been normally disconnected and the phase change action is normal; after the thyristor circuit of phase B is closed, the thyristor Q1 of phase A will be automatically disconnected due to the three-phase voltage. At this time, the protection circuit of phase B will call AD acquisition to obtain the abnormal voltage. If the voltage is greater than 1.65V, it means that phase A is completely disconnected and the device phase change action continues.

[0008] As an improvement, the protection circuit includes operational amplifier U11 and operational amplifier U12.1. The current IA is input to the pin 2 of operational amplifier U11. The pin 3 of operational amplifier U11 is grounded. The pin 4 of operational amplifier U11 is grounded through decoupling capacitor C19. The pin 7 of operational amplifier U11 is grounded through decoupling capacitor C18. A feedback resistor R41 is provided between the pin 6 and the pin 2 of operational amplifier U11. The pin 6 of operational amplifier U11 outputs to the pin 3 of operational amplifier U12.1 and is paralleled with +1.65V for voltage biasing. The pin 2 of operational amplifier U12.1 is grounded. The pin 4 of operational amplifier U12.1 is grounded through decoupling capacitor C21. The pin 8 of operational amplifier U12.1 is grounded through decoupling capacitor C20. A feedback resistor R45 is provided between the pin 1 and the pin 2 of operational amplifier U12.1. The pin 1 of operational amplifier U12.1 outputs current to the main control chip U1. The pin 1 of operational amplifier U12.1 is connected to +3.3V through a forward Schottky diode D7. The pin 1 of operational amplifier U12.1 is grounded through a reverse Schottky diode D8.

[0009] As an improvement, the voltage biasing circuit is connected to the +1.65V interface. The voltage biasing circuit includes operational amplifier U12.2 and voltage reference chip U13. +5V is connected to the pin 5 of operational amplifier U12.2 and the pin 1 of voltage reference chip U13 through resistor RF4. +5V is connected to the pin 2 of the voltage reference chip through resistor RF4 and resistor RF5. +5V is grounded through resistor RF4, resistor RF5 and resistor RF6. The pin 3 of the voltage reference chip is grounded. The pin 3 of the voltage reference chip is connected to the pin 5 of operational amplifier U12.2 through decoupling capacitor C22. A feedback resistor R46 is provided between the pin 7 and the pin 6 of operational amplifier U12.2. The pin 7 of operational amplifier U12.2 is connected to the pin 3 of operational amplifier U12.1.

[0010] As an improvement, the main control chip is STM32ZET6.

[0011] As an improvement, the main control chip U1 is the host, H1 is the LORA device docked with the host, U2 is the slave, and H2 is the LORA device docked with the slave U2. When the host sends a command to the slave, the host sends data to the RX port of the LORA device H1 through the PB10 pin interface. The LORA device H1 sends the data to the LORA device H2 through electromagnetic waves, and the LORA device H2 sends the data to the slave through the TXD pin interface. When the slave sends data to the host, the slave sends data to the RX port of the LORA device H2 through the PB10 pin interface. The LORA device H2 sends the data to the LORA device H1 through electromagnetic waves, and the LORA device H1 sends the data to the host through the TXD pin interface.

[0012] As an improvement, H3 is a 4G Internet of Things module, and the main control chip sends data to the 4G Internet of Things module H3 through the PA2 pin.

[0013] The beneficial effects brought by the present utility model compared with the prior art are:

[0014] The device is built-in with a protection circuit to make up for the problem of self-checking of the device itself that the existing commutation device does not have. Description of the Drawings

[0015] Figure 1 It is the system circuit schematic diagram.

[0016] Figure 2 It is the commutation protection circuit schematic diagram.

[0017] Figure 3 It is the voltage bias circuit schematic diagram.

[0018] Figure 4 It is the time flow chart of the line protection algorithm.

[0019] Figure 5 It is the program design flow chart of the intelligent commutation system.

[0020] Figure 6 It is the commutation simplification algorithm flow chart.

[0021] Figure 7 It is the main-slave communication schematic diagram of the intelligent commutation system.

[0022] Figure 8 It is the circuit schematic diagram of the 4G Internet of Things module of the intelligent commutation system.

[0023] Figure 9 It is the cloud commutation algorithm flow chart.

[0024] Figure 10 It is the power load LSTM algorithm flow chart.

[0025] Figure 11It is a curve graph of the cloud historical data algorithm. Specific implementation mode

[0026] The present utility model will be further described below in conjunction with the accompanying drawings of the specification.

[0027] As Figure 1 shown, a zero-sensing closed-loop phase modulation system device for a low-voltage distribution network includes a main control chip U1, a protection circuit U3, a thyristor Q1, a magnetic latching relay KA1, and a magnetic latching relay KA2. The main control chip is STM32F103ZET6, and the main control chip controls the thyristor Q1, the magnetic latching relay KA1, and the magnetic latching relay KA2; a current transformer obtains the current IA during phase change of the phase wire and inputs it to the protection circuit U3, and the current IA is output to the main control chip U1 after being amplified and stabilized by the protection circuit U3; the thyristor Q1 and the magnetic latching relay KA2 are connected in series and then connected in parallel with the magnetic latching relay KA1 to form a parallel branch, and the phase wire is connected to the load through the parallel branch.

[0028] As Figure 2 shown, the protection circuit includes an operational amplifier U11 and an operational amplifier U12.1. The current IA is input to the 2nd pin of the operational amplifier U11, the 3rd pin of the operational amplifier U11 is grounded, the 4th pin of the operational amplifier U11 is grounded through a decoupling capacitor C19, the 7th pin of the operational amplifier U11 is grounded through a decoupling capacitor C18, a feedback resistor R41 is provided between the 6th pin and the 2nd pin of the operational amplifier U11, the 6th pin of the operational amplifier U11 outputs to the 3rd pin of the operational amplifier U12.1 and is biased with +1.65V in parallel, the 2nd pin of the operational amplifier U12.1 is grounded, the 4th pin of the operational amplifier U12.1 is grounded through a decoupling capacitor C21, the 8th pin of the operational amplifier U12.1 is grounded through a decoupling capacitor C20, a feedback resistor R45 is provided between the 1st pin and the 2nd pin of the operational amplifier U12.1, the 1st pin of the operational amplifier U12.1 outputs current to the main control chip U1, the 1st pin of the operational amplifier U12.1 is connected to +3.3V through a forward Schottky diode D7, and the 1st pin of the operational amplifier U12.1 is grounded through a reverse Schottky diode D8.

[0029] As Figure 3As shown, the voltage bias circuit is connected to the +1.65V interface. The voltage bias circuit includes an operational amplifier U12.2 and a voltage reference chip U13. +5V is connected to the 5th pin of the operational amplifier U12.2 and the 1st pin of the voltage reference chip U13 through a resistor RF4. +5V is connected to the 2nd pin of the voltage reference chip through a resistor RF4 and a resistor RF5. +5V is grounded through a resistor RF4, a resistor RF5, and a resistor RF6. The 3rd pin of the voltage reference chip is grounded. The 3rd pin of the voltage reference chip is connected to the 5th pin of the operational amplifier U12.2 through a decoupling capacitor C22. A feedback resistor R46 is provided between the 7th pin and the 6th pin of the operational amplifier U12.2. The 7th pin of the operational amplifier U12.2 is connected to the 3rd pin of the operational amplifier U12.1.

[0030] As Figure 4 shown, from the start of the commutation of the device until the time point T1, the device can detect the thyristor Q1 and the magnetic latching relays KA1 and KA2. As Figure 5 shown, taking the commutation from phase A to phase B as an example, during the early stage of the device access, the primary voltage is obtained through AD acquisition. Since only KA1 is connected to phase A, there is no current in the circuits of KA2 and thyristor Q1 themselves. The protection circuit can output a voltage close to 0V. During the early stage of the device commutation, the circuits of KA2 and thyristor Q1 are conducted. Since it is impossible for the circuits of KA2 and thyristor Q1 to be damaged simultaneously, based on the theoretical principle of AD detection and the circuit, due to the high voltage drop across the circuit with thyristor Q1, the voltage collected by the protection circuit is almost 0V at this time. After the circuit with thyristor Q1 is completely closed, KA1 is disconnected. If the voltage remains at 0V unchanged, KA1 has not been normally disconnected, and the device returns to the main interface and alarms; if the voltage is greater than 1.65V, KA1 is normally disconnected and the commutation operates normally; after the thyristor circuit of phase B is closed, the thyristor Q1 of phase A is automatically disconnected due to the three-phase voltage. At this time, the protection circuit of phase B will call AD acquisition to obtain the abnormal voltage. If the voltage is greater than 1.65V, phase A is completely disconnected, and the device commutation operation continues.

[0031] Intelligent protection circuit strategy:

[0032] (1) When the device needs to perform the commutation operation from phase A to phase B, the device will have pre-operations in the early stage. During the pre-operations, the devices to be used during the commutation between phase A and phase B are separately switched off;

[0033] (2) Different currents are provided to the acquisition circuit in the protection circuit during the switching-off of different devices;

[0034] (3) When the protection circuit receives different currents, it will perform voltage conversion through its own circuit;

[0035] (4)The converted voltage is supplied to the AD acquisition port of the main control chip for voltage acquisition;

[0036] (5)The main control chip judges the acquired voltage. If it reaches the preset value, the next operation is allowed. If it does not reach the preset value, it returns to the initial power supply state and remains unchanged.

[0037] As Figure 7 shown, in the master-slave communication circuit of the intelligent phase conversion system: the main control chip U1 is the master, H1 is the LORA device docked with the master, U2 is the slave, H2 is the LORA device docked with the slave U2, and both the master and the slave use STM32F103ZET6. When the master sends a command to the slave, the main control chip STM32F103ZET6 of the master sends data to the RX port of the LORA device H1 through the PB10 pin interface. The LORA device H1 sends the data to the LORA device H2 through electromagnetic waves, and the LORA device H2 sends the data to the main control chip STM32F103ZET6 of the slave through the TXD pin interface; when the slave sends data to the master, the main control chip STM32F103ZET6 of the slave sends data to the RX port of the LORA device H2 through the PB10 pin interface. The LORA device H2 sends the data to the LORA device H1 through electromagnetic waves, and the LORA device H1 sends the data to the main control chip STM32F103ZET6 of the master through the TXD pin interface.

[0038] As Figure 6 shown, the phase conversion system is optimized to be applicable to the phase conversion simplified algorithm of the single-chip microcomputer STM32F103ZET6. Taking the conversion from phase A to phase B as an example, when the master selects to use the device algorithm, the algorithm will obtain the current three-phase current data of the distribution network through the AD acquisition device of the master and calculate the three-phase unbalance degree. If the unbalance degree is normal, the master does not send a control signal and the algorithm ends. If the three-phase unbalance degree of the device is abnormal, the algorithm will obtain all the slave device information of the affiliated distribution network, such as phase, current load, etc. After the acquisition is completed, the algorithm starts to calculate. If the number of calculations reaches a certain limit value, it returns to the page and does not perform subsequent operations. If the calculated result is greater than the set three-phase unbalance value, it uniformly controls all slaves to perform phase conversion operations and saves the phase conversion results to 24C02 and the cloud, and the algorithm ends here.

[0039] Intelligent master-slave control strategy:

[0040] (1)When the user performs a unified phase conversion operation through the host device, the single main control chip predicts the three-phase unbalance degree through the single-chip microcomputer phase conversion algorithm;

[0041] (2)After the prediction is completed, the data before and after the phase conversion is compared and displayed through the display screen;

[0042] (3) After the user confirms, they only need to press the confirmation button to send information via LORA;

[0043] (4) When the slave device receives a data signal via the LORA device, it can perform a commutation operation;

[0044] (5) After the operation is completed, a completion signal is returned via LORA;

[0045] (6) When the master device receives the completion signal sent back by LORA, it controls the next slave device to perform an operation.

[0046] As Figure 8 shown, in the intelligent commutation system, the 4G IoT module circuit: H3 is the 4G IoT module, and the main control chip sends data to the 4G IoT module H3 through the PA2 pin.

[0047] As Figure 9 shown, due to the relatively comprehensive modern substation-level commutation strategy, the design of the cloud commutation algorithm is directly used. Based on the accelerated particle, the connection states of the A, B, and C phase switches are represented by 1, 2, and 3 respectively, and the initial state matrix KX of the N commutation switches in the substation can be defined. The particle swarm algorithm has more advantages in solving continuous range problems. In this paper, the discrete problem is transformed into a continuous problem, and the discrete numbers 1, 2, and 3 corresponding to each switch state are mapped to the continuous range of [0, 3]. When xi Î [0, 1], the corresponding switch xi is rounded up, and the corresponding switch xi = 1, that is, the switch is switched to the A phase. Similarly, it is switched to the B phase and C phase respectively. After the established commutation model is discretized and continuousized, it is solved according to the multi-objective accelerated particle swarm algorithm, and the weight function introduced by the pre-action scheme of the solved switch is evaluated.

[0048] The combined historical data algorithm in the cloud of the intelligent commutation system (such as Figure 10 shown in the power load LSTM algorithm flow chart), the application of the LSTM algorithm in the prediction of the grid current load benefits from its unique long-term memory ability, which can effectively handle the long-term dependence problem in time series data, thereby improving the prediction accuracy. As Figure 11 shown, when the user uses the cloud page, they can observe the load curve. The solid line is the current load curve of the device, the dotted line is the predicted load curve, and the O point is the handover point. The algorithm first cleans and formats the original power load data. Meaningful features are extracted from the preprocessed data and the LSTM network model is constructed at the same time. At this time, the algorithm starts to call the historical load data to train the LSTM model, and updates the network weights through the backpropagation algorithm until convergence. Finally, the prediction performance of the model is evaluated through specific evaluation indicators to achieve the prediction effect and is displayed in the form of a load curve.

[0049] Intelligent Phase Converter and Cloud Collaborative Control Strategy:

[0050] During normal operation of the device, the cloud can detect three-phase current load data and single-phase load data connected to each slave device;

[0051] The cloud can perform historical data algorithm prediction on each single-phase load and evaluate the line;

[0052] When the device is not in a hurry to change phases, the cloud phase change algorithm can be used to predict the three-phase unbalance degree before and after phase change;

[0053] When the device requirements are met, the cloud communication device can send phase change suggestions to the host;

[0054] After receiving the phase change suggestions, the host needs to perform unified phase change control through manual determination.

Claims

1. A zero-sensing closed-loop phase modulation system device for a low-voltage distribution network, characterized in that: It includes a main control chip U1, a protection circuit U3, a thyristor Q1, a magnetic latching relay KA1 and a magnetic latching relay KA2; the main control chip controls the thyristor Q1, the magnetic latching relay KA1 and the magnetic latching relay KA2; the current transformer obtains the current IA when the phase line is switched and inputs it to the protection circuit U3, and the current IA is output to the main control chip U1 after passing through the protection circuit U3; the thyristor Q1 is connected in series with the magnetic latching relay KA2 and then connected in parallel with the magnetic latching relay KA1 to form a parallel branch, and the phase line is connected to the load through the parallel branch.

2. A low-voltage distribution network zero-sensing closed-loop phase modulation system device according to claim 1, characterized in that: The protection circuit includes an operational amplifier U11 and an operational amplifier U12.1, a current IA is input to pin 2 of the operational amplifier U11, pin 3 of the operational amplifier U11 is grounded, pin 4 of the operational amplifier U11 is grounded via a decoupling capacitor C19, pin 7 of the operational amplifier U11 is grounded via a decoupling capacitor C18, a feedback resistor R41 is provided between pin 6 and pin 2 of the operational amplifier U11, pin 6 of the operational amplifier U11 is output to pin 3 of the operational amplifier U12.1 and is connected in parallel with +1.65V for voltage bias, and the operational amplifier U11 is connected to the ground via a decoupling capacitor C19. Pin 2 of amplifier U12.1 is grounded, pin 4 of operational amplifier U12.1 is grounded through decoupling capacitor C21, pin 8 of operational amplifier U12.1 is grounded through decoupling capacitor C20, feedback resistor R45 is provided between pin 1 and pin 2 of operational amplifier U12.1, pin 1 of operational amplifier U12.1 outputs current to main control chip U1, pin 1 of operational amplifier U12.1 is connected to +3.3V through forward Schottky diode D7, and pin 1 of operational amplifier U12.1 is grounded through reverse Schottky diode D8.

3. A low-voltage distribution network zero-sensing closed-loop phase modulation system device according to claim 2, characterized in that: The voltage bias circuit is connected to the +1.65V interface, and the voltage bias circuit includes an operational amplifier U12.2 and a voltage reference chip U13. +5V is connected to pin 5 of the operational amplifier U12.2 and pin 1 of the voltage reference chip U13 through resistor RF4, +5V is connected to pin 2 of the voltage reference chip through resistor RF4 and resistor RF5, +5V is grounded through resistor RF4, resistor RF5 and resistor RF6, pin 3 of the voltage reference chip is grounded, pin 3 of the voltage reference chip is connected to pin 5 of the operational amplifier U12.2 through a decoupling capacitor C22, a feedback resistor R46 is provided between pin 7 and pin 6 of the operational amplifier U12.2, and pin 7 of the operational amplifier U12.2 is connected to pin 3 of the operational amplifier U12.

1.

4. A low-voltage distribution network zero-sensing closed-loop phase modulation system device according to claim 1, characterized in that: The main control chip is STM32F103ZET6.

5. A low-voltage distribution network zero-sensing closed-loop phase modulation system device according to claim 4, characterized in that: The main control chip U1 is the host, H1 is the LORA device docked with the host, U2 is the slave, H2 is the LORA device docked with the slave U2, when the host sends a command to the slave, the host sends data to the RX port of the LORA device H1 through the PB10 pin interface, the LORA device H1 sends the data to the LORA device H2 through electromagnetic waves, and the LORA device H2 sends data to the slave through the TXD pin port; when the slave sends data to the host, the slave sends data to the RX port of the LORA device H2 through the PB10 pin interface, the LORA device H2 sends the data to the LORA device H1 through electromagnetic waves, and the LORA device H1 sends data to the host through the TXD pin port.

6. A low-voltage distribution network zero-sensing closed-loop phase modulation system device according to claim 4, characterized in that: H3 is a 4G IoT module. The main control chip sends data to the 4G IoT module H3 through the PA2 pin.

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