Circuit for eliminating CP signal peak interference pulse

Abstract

The utility model discloses a circuit for eliminating CP signal peak interference pulse, which belongs to the technical field of charging piles and comprises an input signal voltage division circuit used for performing voltage division on CP input forward signals, and a signal peak interference filtering circuit connected with the input signal voltage division circuit and used for filtering CP signal bidirectional peak interference pulse. And the signal emitter follower output circuit is connected with the signal peak interference filtering circuit and is used for signal coupling. According to the utility model, through carrying out forward filtering and inverse clamping on CP feedback input signals, filtering of CP signal edge peak interference pulse signals is realized, so that stable output waveforms are provided, the sampling precision of CP feedback signals is improved, and the device has the characteristics of simple structure, low cost and high reliability.

Description

Technical Field

[0001] The utility model belongs to the technical field of charging piles, and particularly relates to a pulse circuit for eliminating CP signal peak interference. Background Technique

[0002] With the rapid development of new energy vehicles, the market for charging piles has gradually expanded. As an important supporting facility for new energy vehicles, the reliability of the product design of charging piles has attracted much attention from consumers. In the charging control application of AC charging piles, the charging pile determines the working state of the current vehicle-end OBC by the voltage amplitude of the output CP pulse width signal, so as to execute the correct charging control action.

[0003] At present, most of them adopt the method of voltage-dividing feedback sampling circuit for CP signals. However, since the CP signal is a positive / negative bipolar voltage signal, in actual work, the CP pulse feedback signal will generate edge jump peak pulse interference waveforms, affecting the accuracy of signal acquisition.

[0004] Therefore, there is an urgent need for a pulse circuit for eliminating CP signal peak interference, which is used to filter the edge peak interference pulse signals of the CP signal, provide a stable output waveform, and improve the sampling accuracy of the CP feedback signal. Summary of the Utility Model

[0005] The purpose of the utility model is to provide a pulse circuit for eliminating CP signal peak interference to solve the problems put forward in the above background technique. A pulse circuit for eliminating CP signal peak interference provided by the utility model has the characteristics of being able to filter the edge peak interference pulse signals of the CP signal, provide a stable output waveform, and improve the sampling accuracy of the CP feedback signal.

[0006] To achieve the above purpose, the utility model provides the following technical solution: A pulse circuit for eliminating CP signal peak interference includes an input signal voltage-dividing circuit for voltage-dividing the CP input positive signal, a signal peak interference filtering circuit connected to the input signal voltage-dividing circuit for filtering the bidirectional peak interference pulses of the CP signal, and a signal emitter follower output circuit connected to the signal peak interference filtering circuit for signal coupling.

[0007] In order to divide the voltage of the positive CP input signal of 6 to 12V, so as to obtain the voltage range that can be processed by the ADC sampling pin of the subsequent MCU microprocessor. Further, the input signal voltage dividing circuit includes a bidirectional transient suppression diode D1, an inverter diode D2, a resistor R1 and a resistor R2. Among them, one end of the bidirectional transient suppression diode D1 is connected to the positive terminal of the inverter diode D2 as the CP signal input end. The negative terminal of the inverter diode D2 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to one end of the resistor R2, and the other ends of the bidirectional transient suppression diode D1 and the resistor R2 are respectively connected to the ground terminal.

[0008] In order to filter the positive spike pulses of the positive voltage-dividing signal on the resistor R2. Further, the signal spike interference filtering circuit includes a capacitor C1. Among them, the capacitor C1 is connected in parallel with the resistor R2.

[0009] In order to clamp the amplitude of the negative voltage spike interference wave on the resistor R2 and filter the negative voltage spike pulses. Further, the signal spike interference filtering circuit also includes a fast diode D3. Among them, the fast diode D3 is connected in parallel with the capacitor C1, and the positive terminal of the fast diode D3 is connected to the ground terminal.

[0010] In order to couple the front-stage CP voltage-dividing signal with the subsequent circuit. Further, the signal emitter follower output circuit includes an operational amplifier U1A. Among them, the pin 3 of the operational amplifier U1A is connected to the negative terminal of the fast diode D3, and the pin 2 of the operational amplifier U1A is connected to the pin 1.

[0011] In order to achieve impedance matching. Further, the pin 1 of the operational amplifier U1A is connected to one end of a resistor R3, and the other end of the resistor R3 is connected to the ADC sampling pin of the MCU microprocessor.

[0012] In order to filter the output signal. Further, a capacitor C2 is also connected between the resistor R3 and the ADC sampling pin of the MCU microprocessor, and the other end of the capacitor C2 is connected to the ground terminal.

[0013] Compared with the prior art, the beneficial effects of the present utility model are:

[0014] The present utility model filters the edge spike interference pulse signal of the CP signal by performing positive filtering and inverting clamping on the CP feedback input signal, thereby providing a stable output waveform, improving the sampling accuracy of the CP feedback signal, and having the characteristics of simple structure, low cost and high reliability. Description of the Drawings

[0015] Figure 1 It is the circuit diagram of the present utility model; Detailed Embodiments

[0016] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0017] Embodiment 1

[0018] Please refer to Figure 1 , the present invention provides the following technical solutions: An anti-CP signal spike interference pulse circuit includes an input signal voltage dividing circuit for dividing the positive CP input signal, a signal spike interference filtering circuit connected to the input signal voltage dividing circuit for filtering the bidirectional spike interference pulses of the CP signal, and a signal emitter follower output circuit connected to the signal spike interference filtering circuit for signal coupling.

[0019] By adopting the above technical solutions, the present invention filters the edge spike interference pulse signals of the CP signal by performing forward filtering and inverting clamping on the CP feedback input signal, thereby providing a stable output waveform, improving the sampling accuracy of the CP feedback signal, and having the characteristics of simple structure, low cost, and high reliability.

[0020] Specifically, the input signal voltage dividing circuit includes a bidirectional transient suppression diode D1, an inverting diode D2, a resistor R1, and a resistor R2. Among them, one end of the bidirectional transient suppression diode D1 is connected to the positive electrode end of the inverting diode D2 as the CP signal input end, the negative electrode end of the inverting diode D2 is connected to one end of the resistor R1, one end of the resistor R1 is connected to one end of the resistor R2, and the other ends of the bidirectional transient suppression diode D1 and the resistor R2 are respectively connected to the ground terminal.

[0021] By adopting the above technical solutions, the 6 to 12V voltage signal of the CP input positive signal is divided to obtain a voltage range that can be processed by the ADC sampling pin of the subsequent MCU microprocessor.

[0022] Specifically, the signal spike interference filtering circuit includes a capacitor C1. Among them, the capacitor C1 is connected in parallel with the resistor R2, and the capacitor C1 is a filtering capacitor with a capacitance value of 100 pF.

[0023] By adopting the above technical solutions, the positive voltage-divided signal on the resistor R2 is filtered for spike pulses.

[0024] Specifically, the signal emitter follower output circuit includes an operational amplifier U1A. Among them, the 3rd pin of the operational amplifier U1A is connected to the negative electrode end of the fast diode D3, and the 2nd pin of the operational amplifier U1A is connected to the 1st pin.

[0025] By adopting the above technical solution, as an emitter follower circuit, the pre-stage CP voltage-dividing signal is coupled with the post-stage circuit for signal.

[0026] Embodiment 2

[0027] The difference between this embodiment and Embodiment 1 is that specifically, the signal spike interference filtering circuit further includes a fast diode D3, model number SS14. Among them, the fast diode D3 is connected in parallel with the capacitor C1, and the positive terminal of the fast diode D3 is connected to the ground terminal.

[0028] By adopting the above technical solution, the amplitude of the negative voltage spike interference wave on the resistor R2 is clamped, and the negative voltage spike pulse is filtered.

[0029] Embodiment 3

[0030] The difference between this embodiment and Embodiment 1 is that specifically, pin 1 of the operational amplifier U1A is connected to one end of the resistor R3, the other end of the resistor R3 is connected to the ADC sampling pin of the MCU microprocessor, and the resistance value of the resistor R3 is 1K.

[0031] By adopting the above technical solution, impedance matching is achieved.

[0032] Specifically, a capacitor C2 is also connected between the resistor R3 and the ADC sampling pin of the MCU microprocessor, the other end of the capacitor C2 is connected to the ground terminal, and the capacitor C2 is a filtering capacitor with a capacitance value of 100 nF.

[0033] By adopting the above technical solution, the output signal is filtered.

[0034] In the present utility model, the model number of the bidirectional transient voltage suppression diode D1 is SMBJ15CA, which is used for overvoltage suppression protection of the input CP signal; the model number of the fast diode D2 is SS14, which is used to conduct the positive signal of the CP signal and cut off the reverse signal of the CP signal to obtain the positive wave of the CP signal; the resistors R1 and R2 form a voltage-dividing circuit, the resistance value of the resistor R1 is 100K, and the resistance value of the resistor R2 is 33K.

[0035] The working principle of the present utility model is as follows:

[0036] (1), The CP feedback signal of the charging pile is input through the reverse diode D2. The reverse diode D2 reversely cuts off the negative half-wave pulse of the CP signal and conducts forwardly the positive half-wave of the CP signal to obtain the positive half-wave pulse signal of the CP signal. The resistors R1 and R2 perform voltage division processing on the input positive half-wave signal of the CP to obtain the voltage-dividing signal on the resistor R2.

[0037] (2) The capacitor C1 filters the positive half-wave spike interference pulses of the voltage-dividing signal on the resistor R2, and the fast diode D3 clamps and filters the negative spike interference pulses of the voltage-dividing signal on the resistor R2, thereby filtering out the positive / negative spike pulse waveforms of the edge jump of the CP signal;

[0038] (3) After being filtered, the CP signal is input to the non-inverting input terminal 3 of the operational amplifier U1A. The operational amplifier U1A forms an emitter follower circuit. The signal output from the 1st pin of the operational amplifier U1A passes through the impedance matching resistor R3 and the filtering capacitor C2 and then is output to the ADC sampling input pin of the subsequent MCU microprocessor;

[0039] (4) The MCU microprocessor judges the working state of the current vehicle-mounted OBC by sampling and calculating the current voltage amplitude of the CP signal.

[0040] In summary, the utility model filters the edge spike interference pulse signals of the CP signal by performing positive filtering and inverting clamping on the CP feedback input signal, thereby providing a stable output waveform, improving the sampling accuracy of the CP feedback signal, and having the characteristics of simple structure, low cost and high reliability.

[0041] Although the embodiments of the present utility model have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principle and spirit of the present utility model. The scope of the present utility model is defined by the appended claims and their equivalents.

Claims

1. A circuit for eliminating CP signal spike interference pulses, characterized in that: The invention comprises an input signal voltage dividing circuit for dividing the voltage of the CP input forward signal, a signal spike interference filtering circuit connected to the input signal voltage dividing circuit for filtering the bidirectional spike interference pulses of the CP signal, and a signal emitter-follower output circuit connected to the signal spike interference filtering circuit for signal coupling.

2. A circuit for eliminating CP signal spike interference pulses according to claim 1, characterized in that: The input signal voltage divider circuit includes a bidirectional transient suppression diode D1, an inverting diode D2, a resistor R1 and a resistor R2, wherein one end of the bidirectional transient suppression diode D1 is connected to the positive end of the inverting diode D2 as the CP signal input end, the negative end of the inverting diode D2 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to one end of the resistor R2, and the other ends of the bidirectional transient suppression diode D1 and the resistor R2 are respectively connected to the ground end.

3. A circuit for eliminating CP signal spike interference pulses according to claim 2, characterized in that: The signal spike interference filtering circuit includes a capacitor C1, wherein the capacitor C1 is connected in parallel with a resistor R2.

4. A circuit for eliminating CP signal spike interference pulses according to claim 3, characterized in that: The signal spike interference filtering circuit further includes a fast diode D3, wherein the fast diode D3 is connected in parallel with the capacitor C1, and the positive terminal of the fast diode D3 is connected to the ground terminal.

5. A circuit for eliminating CP signal spike interference pulses according to claim 4, characterized in that: The signal emitter-follower output circuit includes an operational amplifier U1A, wherein pin 3 of the operational amplifier U1A is connected to the negative terminal of the fast diode D3, and pin 2 of the operational amplifier U1A is connected to pin 1.

6. A circuit for eliminating CP signal spike interference pulses according to claim 5, characterized in that: Pin 1 of the operational amplifier U1A is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the ADC sampling pin of the MCU microprocessor.

7. The circuit for eliminating CP signal spike interference pulse according to claim 6, characterized in that: A capacitor C2 is also connected between the resistor R3 and the ADC sampling pin of the MCU microprocessor, and the other end of the capacitor C2 is connected to the ground end.

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