Test power supply device and chip test system
By designing a multi-mode test power supply device, it is solved that it is difficult to quickly screen out faults caused by component quality problems in the prior art, and efficient testing and deterioration screening of the chip to be tested is realized.
Patent Information
- Application Number
- CN202421308085.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-07
- Publication Date
- 2025-06-27
- Estimated Expiration
- 2034-06-07
AI Technical Summary
The prior art is difficult to effectively screen out failures caused by component quality problems in electronic products, which makes it difficult for the product failure curve to quickly reach a low and stable accidental failure period.
A test power supply device is designed, including a bias voltage output module and a test voltage output module, which can operate in normal test mode, high-voltage stress test mode and shutdown mode. By outputting different bias voltages and test voltages, multiple tests of the chip to be tested, including functional tests and degradation tests.
It realizes efficient testing of the chip to be tested, can complete functional testing in normal test mode, and quickly complete deterioration testing under high-voltage stress test, thereby screening out chips that do not meet the standards or have been damaged, ensuring that the chips that pass the test achieve low and stable failure efficiency.
Smart Images
Figure CN223038018U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of testing, in particular to a test power supply device and a chip test system. Background Art
[0002] Electronic products are composed of numerous electronic components, and their performance, quality, and reliability depend on the used electronic components. In engineering practice, a large part of the failures of electronic products are caused by problems with the quality of electronic components. The integrated circuit failure data published at home and abroad shows that the first in the failure distribution is the failure of electronic components. Therefore, it is crucial to improve the efficiency in product failure screening and enable the product to enter the time period with high reliability as soon as possible.
[0003] Generally speaking, the failure rate curve of a product includes a constant type, an increasing type, and a decreasing type, etc. In engineering practice, the failure rate curves of many products are very similar. Because the shape of the curve is similar to a bathtub, high at both ends and low in the middle, this failure rate curve is called the "bathtub curve", as Figure 1 shown, there are three stages of product failure: (1) Early failure period, characterized by a high failure rate in the early stage and a continuous decline later; (2) Random failure period, characterized by relatively stable product quality during this period, a relatively low failure rate, and basically can be considered as a constant; (3) Wear-out failure period, characterized by a continuous increase in the failure rate over time.
[0004] It is usually desired that the device quickly reaches the random failure period with a low and stable failure rate, that is, the bottom of the bathtub curve. Summary of the Utility Model
[0005] According to one aspect of the present utility model, there is provided a test power supply device, the device includes a bias voltage output module and a test voltage output module, the bias voltage output module is connected to the test voltage output module, and the test voltage output module is connected to at least one chip under test. Among them, the bias voltage output module and the test voltage output module are configured to operate in at least one of a normal test mode, a high-voltage stress test mode, and a shutdown mode. Among them,
[0006] In the normal test mode, the bias voltage output module outputs a first bias voltage, and the test voltage output module generates a first test voltage according to the first bias voltage to test the chip under test;
[0007] In the high-voltage stress test mode, the bias voltage output module outputs a second bias voltage, and the test voltage output module generates at least one second test voltage according to the second bias voltage to test the chip under test. The second bias voltage is higher than the first bias voltage, and the second test voltage is higher than the first bias voltage;
[0008] In the off mode, neither the bias voltage output module nor the test voltage output module outputs a voltage.
[0009] In a possible implementation, the bias voltage output module includes a bias transistor, a first current source, a first switch component, a second switch component, and a third switch component, where
[0010] The positive terminal of the first current source is used to receive the power supply voltage, and the negative terminal of the first current source is connected to the drain terminal of the bias transistor, the gate terminal of the bias transistor, the first end of the first switch component, and the first end of the second switch component.
[0011] The source terminal of the bias transistor is connected to the second end of the first switch component and grounded.
[0012] The second end of the second switch component and the first end of the third switch component are connected together as the output terminal of the bias voltage output module.
[0013] The second end of the third switch component is used to receive the power supply voltage.
[0014] In a possible implementation, when the first switch component is off, the second switch component is on, and the third switch component is off, the bias voltage output module is configured in the normal test mode;
[0015] In a possible implementation, when the first switch component is off or on, the second switch component is off, and the third switch component is on, the bias voltage output module is configured in the high-voltage stress test mode;
[0016] In a possible implementation, when the first switch component is on, the second switch component is off, and the third switch component is off, the bias voltage output module is configured in the off mode.
[0017] In a possible implementation, the test voltage output module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first switch unit, a second switch unit, a third switch unit, and a fourth switch unit, where
[0018] The source terminal of the first transistor, the source of the third transistor, the source of the fifth transistor, the first end of the third switching unit, and the first end of the fourth switching unit are connected to the output terminal of the bias voltage output module for receiving the first bias voltage or the second bias voltage.
[0019] The drain of the first transistor is connected to the first end of the first switching unit, and the drain of the second transistor is connected to the second end of the first switching unit.
[0020] The gate of the first transistor and the gate of the third transistor are both connected to the third end of the first switching unit.
[0021] The gate of the second transistor and the gate of the fourth transistor are both connected to the fourth end of the first switching unit.
[0022] The drain of the third transistor is connected to the first end of the second switching unit, and the drain of the fourth transistor is connected to the second end of the second switching unit.
[0023] The gate of the fifth transistor is connected to the third end of the second switching unit and the third end of the third switching unit, and the second end of the third switching unit is grounded.
[0024] The gate of the sixth transistor is connected to the fourth end of the second switching unit and the third end of the fourth switching unit.
[0025] The source of the second transistor, the source of the fourth transistor, the second end of the fourth switching unit, and the source of the sixth transistor are all grounded.
[0026] The drain of the fifth transistor is connected to the drain of the sixth transistor to serve as the output terminal of the test voltage output module.
[0027] In a possible implementation manner, the first switching unit includes a fourth switching component, a fifth switching component, a sixth switching component, a seventh switching component, and a second current source, where
[0028] The first end of the fourth switching component serves as the first end of the first switching unit.
[0029] The second end of the fourth switching component is connected to the first end of the fifth switching component to serve as the third end of the first switching unit.
[0030] The second end of the fifth switching component is connected to the positive terminal of the second current source, and the negative terminal of the second current source is connected to the first end of the seventh switching component.
[0031] The second end of the seventh switch component is connected to the first end of the sixth switch component to serve as the fourth end of the first switch unit.
[0032] The second end of the sixth switch component serves as the second end of the first switch unit.
[0033] In a possible implementation, the second switch unit includes an eighth switch component, a ninth switch component, a tenth switch component, an eleventh switch component, and a third current source, where
[0034] The first end of the eighth switch component serves as the first end of the second switch unit.
[0035] The second end of the eighth switch component is connected to the first end of the ninth switch component to serve as the third end of the second switch unit.
[0036] The second end of the ninth switch component is connected to the positive extreme of the third current source, and the negative extreme of the third current source is connected to the first end of the eleventh switch component.
[0037] The second end of the eleventh switch component is connected to the first end of the tenth switch component to serve as the fourth end of the second switch unit.
[0038] The second end of the tenth switch component serves as the second end of the second switch unit.
[0039] In a possible implementation, the third switch unit includes a twelfth switch component and a thirteenth switch component, where
[0040] The first end of the twelfth switch component serves as the first end of the third switch unit.
[0041] The second end of the twelfth switch component is connected to the first end of the thirteenth switch component to serve as the third end of the third switch unit.
[0042] The second end of the thirteenth switch component serves as the second end of the third switch unit.
[0043] In a possible implementation, the fourth switch unit includes a fourteenth switch component and a fifteenth switch component, where
[0044] The first end of the fourteenth switch component serves as the first end of the fourth switch unit.
[0045] The second end of the fourteenth switch component is connected to the first end of the fifteenth switch component to serve as the third end of the fourth switch unit.
[0046] The second end of the fifteenth switch component serves as the second end of the fourth switch unit.
[0047] In a possible implementation manner, in the normal test mode, the first end of the first switch unit is communicated with the second end of the first switch unit, the first end of the second switch unit is communicated with the second end of the second switch unit, the first end of the third switch unit is disconnected from the third end of the third switch unit, the second end of the third switch unit is disconnected from the third end of the third switch unit, the first end of the fourth switch unit is disconnected from the third end of the fourth switch unit, the second end of the fourth switch unit is disconnected from the third end of the fourth switch unit, and the output end of the test voltage output module outputs the first test voltage.
[0048] In a possible implementation manner, in the high-voltage stress test mode, the source electrode of the third transistor, the first end of the second switch unit, the third end of the second switch unit, the gate electrode of the fifth transistor, the output end of the test voltage output module are communicated, and / or, the drain electrode of the fourth transistor, the fourth end of the second switch unit, the gate electrode of the sixth transistor and the output end of the test voltage output module are communicated to output a corresponding second test voltage.
[0049] In a possible implementation manner, in the off mode, both the fifth transistor and the sixth transistor are disconnected.
[0050] In a possible implementation manner, the chip under test includes at least one of a touch chip, a display driver chip, a display driver and touch integrated single chip, a fingerprint recognition chip, a digital processing chip, an FPGA chip, a CPLD chip, a power management chip, a baseband chip, and a baseboard management chip.
[0051] According to one aspect of the present invention, a chip test system is provided, and the system includes the test power supply device described above.
[0052] The test power supply device according to the embodiment of the present utility model can operate in at least one of a normal test mode, a high-voltage stress test mode, and a shutdown mode. In the normal test mode, the bias voltage output module outputs a first bias voltage, and the test voltage output module generates a first test voltage based on the first bias voltage to test the chip under test. In the high-voltage stress test mode, the bias voltage output module outputs a second bias voltage, and the test voltage output module generates at least one second test voltage based on the second bias voltage to test the chip under test. The second bias voltage is higher than the first bias voltage, and the second test voltage is higher than the first bias voltage. Therefore, the embodiment of the present utility model can efficiently implement various tests on the chip under test, complete the functional test in the normal test mode, and output at least one second test voltage with a high voltage in the high-voltage stress test to conveniently and quickly complete the chip degradation test, so as to pick out the chips under test that do not meet the standards or have been damaged. The chips under test that pass the test are considered to have reached the accidental failure period with a low failure rate and high stability. It can be seen that the test power supply device according to the embodiment of the present utility model can achieve efficient testing of the chips under test.
[0053] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and do not limit the present utility model. According to the following detailed description of the exemplary embodiments with reference to the accompanying drawings, other features and aspects of the present utility model will become clear. BRIEF DESCRIPTION OF THE DRAWINGS
[0054] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification. These drawings illustrate embodiments consistent with the present utility model and are used together with the specification to explain the technical solutions of the present utility model.
[0055] Figure 1 A schematic diagram showing the failure rate curve of the product is shown.
[0056] Figure 2 A block diagram showing the test power supply device according to the embodiment of the present utility model is shown.
[0057] Figure 3 A schematic diagram showing the bias voltage output module according to the embodiment of the present utility model is shown.
[0058] Figure 4 A schematic diagram showing the test voltage output module according to the embodiment of the present utility model is shown.
[0059] Figure 5a 、 Figure 5b A simulation schematic diagram showing the test using the test power supply device according to the embodiment of the present utility model is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0060] Exemplary embodiments, features, and aspects of the present utility model will be described in detail below with reference to the accompanying drawings. The same reference numerals in the drawings denote elements having the same or similar functions. Although various aspects of the embodiments are shown in the drawings, the drawings do not have to be drawn to scale unless otherwise specified.
[0061] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by terms such as "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present utility model.
[0062] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present utility model, "a plurality" means two or more unless otherwise specifically defined.
[0063] In the present utility model, unless otherwise clearly specified and defined, terms such as "mounted", "connected", "coupled", "fixed", etc. should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral body; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.
[0064] The special term "exemplary" herein means "serving as an example, embodiment, or illustration". Any embodiment described as "exemplary" herein does not have to be construed as superior to or better than other embodiments.
[0065] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the term "at least one" in this article represents any one of a plurality or any combination of at least two of a plurality. For example, including at least one of A, B, and C may represent including any one or more elements selected from the set composed of A, B, and C.
[0066] In addition, to better illustrate the present invention, numerous specific details are given in the following detailed implementation manners. Those skilled in the art should understand that the present invention can be implemented without some specific details. In some instances, methods, means, elements, and circuits well-known to those skilled in the art are not described in detail to highlight the gist of the present invention.
[0067] Please refer to Figure 2 , Figure 2 which shows a block diagram of a test power supply device according to an embodiment of the present invention.
[0068] As Figure 2 shown, the device includes a bias voltage output module 10 and a test voltage output module 20. The bias voltage output module 10 is connected to the test voltage output module 20, and the test voltage output module 20 is connected to at least one chip under test 30. Among them, the bias voltage output module 10 and the test voltage output module 20 are configured to operate in at least one of a normal test mode, a high voltage stress (HVS) test mode, and a shutdown mode. Among them,
[0069] In the normal test mode, the bias voltage output module 10 outputs a first bias voltage, and the test voltage output module 20 generates a first test voltage according to the first bias voltage to test the chip under test 30.
[0070] In the high voltage stress test mode, the bias voltage output module 10 outputs a second bias voltage, and the test voltage output module 20 generates at least one second test voltage according to the second bias voltage to test the chip under test 30. The second bias voltage is higher than the first bias voltage, and the second test voltage is higher than the first bias voltage.
[0071] In the shutdown mode, neither the bias voltage output module 10 nor the test voltage output module 20 outputs a voltage.
[0072] The test power supply device of the embodiment of the present utility model can operate in at least one of a normal test mode, a high-voltage stress test mode, and a shutdown mode. In the normal test mode, the bias voltage output module 10 outputs a first bias voltage, and the test voltage output module 20 generates a first test voltage according to the first bias voltage to test the chip under test 30. In the high-voltage stress test mode, the bias voltage output module 10 outputs a second bias voltage, and the test voltage output module 20 generates at least one second test voltage according to the second bias voltage to test the chip under test 30. The second bias voltage is higher than the first bias voltage, and the second test voltage is higher than the first bias voltage. Therefore, the embodiment of the present utility model can switch the test mode and efficiently implement various tests on the chip under test 30, complete the functional test in the normal test mode, and output at least one second test voltage with a high voltage in the high-voltage stress test to conveniently and quickly complete the chip degradation test, so as to pick out the chips under test that do not meet the standards or have been damaged. The chips under test that pass the test are considered to reach the accidental failure period with a low failure rate and stability. It can be seen that the test power supply device of the embodiment of the present utility model can achieve efficient testing of the chips under test.
[0073] The embodiment of the present utility model does not limit the specific implementation manners of the bias voltage output module 10 and the test voltage output module 20. Those skilled in the art can adopt appropriate technical means according to the actual situation and needs as long as the corresponding functions can be achieved.
[0074] The embodiment of the present utility model does not limit the specific test items and test methods for the chip under test 30 in the normal working mode, does not limit the magnitude of the first bias voltage, and does not limit the magnitude of the first test voltage. Those skilled in the art can set them according to the actual situation and needs.
[0075] The embodiment of the present utility model does not limit the specific test items and test methods for the chip under test 30 in the high-voltage stress test mode, does not limit the magnitude of the second bias voltage, and does not limit the magnitude of the second test voltage. Those skilled in the art can set them according to the actual situation and needs.
[0076] The embodiment of the present utility model does not limit the specific type of the chip under test 30. Those skilled in the art can set it according to the actual situation and needs. In a possible implementation manner, the chip under test 30 may include at least one of a touch chip, a display driver chip, a display driver and touch integrated single chip, a fingerprint recognition chip, a digital processing chip, an FPGA chip, a CPLD chip, a power management chip, a baseband chip, and a baseboard management chip, etc.
[0077] Next, the preferred implementation manners of the bias voltage output module 10 and the test voltage output module 20 are introduced exemplarily.
[0078] Please refer to Figure 3 , Figure 3 which shows a schematic diagram of the bias voltage output module 10 according to an embodiment of the present invention.
[0079] In a possible implementation, as Figure 3 shown, the bias voltage output module 10 may include a bias transistor Q0, a first current source Iref1, a first switch component SW1, a second switch component SW2, and a third switch component SW3. Among them,
[0080] The positive terminal of the first current source Iref1 is used to receive the power supply voltage VDDA, and the negative terminal of the first current source Iref1 is connected to the drain terminal of the bias transistor Q0, the gate terminal of the bias transistor Q0, the first end of the first switch component SW1, and the first end of the second switch component SW2.
[0081] The source terminal of the bias transistor Q0 is connected to the second end of the first switch component SW1 and grounded.
[0082] The second end of the second switch component SW2 and the first end of the third switch component SW3 are connected as the output terminal of the bias voltage output module 10.
[0083] The second end of the third switch component SW3 is used to receive the power supply voltage VDDA.
[0084] Among them, the output terminal of the voltage output module 10 is used to output a bias voltage VOUT, such as a first bias voltage and a second bias voltage.
[0085] The embodiments of the present invention do not limit the specific implementation manners of the bias transistor Q0, the first current source Iref1, the first switch component SW1, the second switch component SW2, and the third switch component SW3. Those skilled in the art can select appropriate devices according to needs. Exemplarily, the bias transistor Q0 can be a MOSFET transistor, and the first switch component SW1, the second switch component SW2, and the third switch component SW3 can include any one of a relay, a reed switch, a thyristor, a switching diode, a switching triode, an electronic bidirectional switch, an optocoupler, a transistor, etc. The transistor can be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) or an Insulated Gate Bipolar Transistor (IGBT). Among them, the transistor can be implemented based on silicon carbide (SiC) or gallium nitride (GaN) to improve performance.
[0086] In a possible implementation, when the first switch component SW1 is turned off, the second switch component SW2 is turned on, and the third switch component SW3 is turned off, the bias voltage output module 10 is configured in a normal test mode.
[0087] In a possible implementation, when the first switch component SW1 is turned off or on, the second switch component SW2 is turned off, and the third switch component SW3 is turned on, the bias voltage output module 10 is configured in a high-voltage stress test mode.
[0088] In a possible implementation, when the first switch component SW1 is turned on, the second switch component SW2 is turned off, and the third switch component SW3 is turned off, the bias voltage output module 10 is configured in a shutdown mode.
[0089] Embodiments of the present utility model can control the on / off states of the first switch component SW1, the second switch component SW2, and the third switch component SW3 by generating a first switch control signal SL_B, a second switch control signal SW_B, and a third switch control signal SH_B, respectively.
[0090] Please refer to Table 1, which arranges the corresponding relationships between the first switch component SW1, the second switch component SW2, the third switch component SW3, and the bias voltage output module 10 operating in the normal test mode, the high-voltage stress test mode, and the shutdown mode.
[0091] Table 1
[0092]
[0093] Please refer to Figure 4 , Figure 4 which shows a schematic diagram of the test voltage output module 20 according to an embodiment of the present utility model.
[0094] In a possible implementation, as Figure 4 shown, the test voltage output module 20 may include a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a first switch unit 210, a second switch unit 220, a third switch unit 230, and a fourth switch unit 240, where
[0095] The source terminal of the first transistor Q1, the source of the third transistor Q3, the source of the fifth transistor Q5, the first end of the third switch unit 230, and the first end of the fourth switch unit 240 are connected to the output end of the bias voltage output module 10 for receiving the first bias voltage or the second bias voltage (VOUT).
[0096] The drain of the first transistor Q1 is connected to the first end of the first switch unit 210, and the drain of the second transistor Q2 is connected to the second end of the first switch unit 210.
[0097] The gates of the first transistor Q1 and the third transistor Q3 are both connected to the third end of the first switch unit 210.
[0098] The gates of the second transistor Q2 and the fourth transistor Q4 are both connected to the fourth end of the first switch unit 210.
[0099] The drain of the third transistor Q3 is connected to the first end of the second switch unit 220, and the drain of the fourth transistor Q4 is connected to the second end of the second switch unit 220.
[0100] The gate of the fifth transistor Q5 is connected to the third end of the second switch unit 220 and the third end of the third switch unit 230, and the second end of the third switch unit 230 is grounded.
[0101] The gate of the sixth transistor Q6 is connected to the fourth end of the second switch unit 220 and the third end of the fourth switch unit 240.
[0102] The sources of the second transistor Q2, the fourth transistor Q4, the second end of the fourth switch unit 240, and the source of the sixth transistor Q6 are all grounded.
[0103] The drain of the fifth transistor Q5 is connected to the drain of the sixth transistor Q6 as the output end of the test voltage output module 20.
[0104] Exemplarily, as Figure 4 shown, the first transistor Q1, the third transistor Q3, and the fifth transistor Q5 are all P-channel MOSFET transistors, and the second transistor Q2, the fourth transistor Q4, and the sixth transistor Q6 are all N-channel MOSFET transistors. Of course, the specific transistor types of the first transistor Q1, the third transistor Q3, the fifth transistor Q5, the second transistor Q2, the fourth transistor Q4, and the sixth transistor Q6 in the embodiments of the present invention are not limited, and those skilled in the art can set them according to actual situations and needs.
[0105] The embodiments of the present utility model do not limit the specific implementation manners of the first switch unit 210, the second switch unit 220, the third switch unit 230, and the fourth switch unit 240. Those skilled in the art can adopt appropriate technical solutions according to the actual situation and needs to implement them.
[0106] In a possible implementation manner, as Figure 4 shown, the first switch unit 210 includes a fourth switch component SW4, a fifth switch component SW5, a sixth switch component SW6, a seventh switch component SW7, and a second current source 125, where
[0107] The first end of the fourth switch component SW4 serves as the first end of the first switch unit 210,
[0108] The second end of the fourth switch component SW4 is connected to the first end of the fifth switch component SW5 to serve as the third end of the first switch unit 210,
[0109] The second end of the fifth switch component SW5 is connected to the positive extreme of the second current source 125, and the negative extreme of the second current source 125 is connected to the first end of the seventh switch component SW7,
[0110] The second end of the seventh switch component SW7 is connected to the first end of the sixth switch component SW6 to serve as the fourth end of the first switch unit 210,
[0111] The second end of the sixth switch component SW6 serves as the second end of the first switch unit 210.
[0112] Exemplarily, as Figure 4 shown, the fourth switch component SW4, the fifth switch component SW5, the sixth switch component SW6, and the seventh switch component SW7 are respectively controlled by a fourth switch control signal CP1, a fifth switch control signal CP2, a sixth switch control signal CN1, and a seventh switch control signal CN2.
[0113] In a possible implementation manner, as Figure 4 shown, the second switch unit 220 includes an eighth switch component SW8, a ninth switch component SW9, a tenth switch component SW10, an eleventh switch component SW11, and a third current source 126, where
[0114] The first end of the eighth switch component SW8 serves as the first end of the second switch unit 220,
[0115] The second end of the eighth switch component SW8 is connected to the first end of the ninth switch component SW9 to serve as the third end of the second switch unit 220,
[0116] The second end of the ninth switch component SW9 is connected to the positive extreme of the third current source 126, and the negative extreme of the third current source 126 is connected to the first end of the eleventh switch component SW11.
[0117] The second end of the eleventh switch component SW11 is connected to the first end of the tenth switch component SW10 to serve as the fourth end of the second switch unit 220.
[0118] The second end of the tenth switch component SW10 serves as the second end of the second switch unit 220.
[0119] Exemplarily, as Figure 4 shown, the eighth switch component SW8, the ninth switch component SW9, the tenth switch component SW10, and the eleventh switch component SW11 are respectively controlled by the fourth switch control signal CP1, the fifth switch control signal CP2, the sixth switch control signal CN1, and the seventh switch control signal CN2.
[0120] In a possible implementation manner, as Figure 4 shown, the third switch unit 230 includes a twelfth switch component SW12 and a thirteenth switch component SW13, wherein
[0121] The first end of the twelfth switch component SW12 serves as the first end of the third switch unit 230.
[0122] The second end of the twelfth switch component SW12 is connected to the first end of the thirteenth switch component SW13 to serve as the third end of the third switch unit 230.
[0123] The second end of the thirteenth switch component SW13 serves as the second end of the third switch unit 230.
[0124] Exemplarily, as Figure 4 shown, the twelfth switch component SW12 and the thirteenth switch component SW13 are respectively controlled by the eighth switch control signal SP1 and the ninth switch control signal SP2.
[0125] In a possible implementation manner, as Figure 4 shown, the fourth switch unit 240 includes a fourteenth switch component SW14 and a fifteenth switch component SW15, wherein
[0126] The first end of the fourteenth switch component SW14 serves as the first end of the fourth switch unit 240.
[0127] The second terminal of the fourteenth switch component SW14 is connected to the first terminal of the fifteenth switch component SW15 to serve as the third terminal of the fourth switch unit 240.
[0128] The second terminal of the fifteenth switch component SW15 serves as the second terminal of the fourth switch unit 240.
[0129] Exemplarily, as Figure 4 shown, the fourteenth switch component SW14 and the fifteenth switch component SW15 are respectively controlled by the tenth switch control signal SN1 and the eleventh switch control signal SN2.
[0130] The embodiments of the present invention do not limit the specific implementation manners of the fourth switch component SW4 to the fifteenth switch component SW15. The bias transistor Q0 can be a MOSFET transistor. The fourth switch component SW4 to the fifteenth switch component SW15 can include any one of a relay, a reed switch, a thyristor, a switching diode, a switching triode, an electronic bidirectional switch, an optocoupler, a transistor, etc. The transistor can be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) or an Insulated Gate Bipolar Transistor (IGBT). Among them, the transistor can be implemented based on silicon carbide (SiC) or gallium nitride (GaN) to improve performance.
[0131] In a possible implementation manner, as Figure 4 shown, in the normal test mode, the first terminal of the first switch unit 210 is connected to the second terminal of the first switch unit 210 (each switch component in the first switch unit 210 is turned on), the first terminal of the second switch unit 220 is connected to the second terminal of the second switch unit 220 (each switch component in the second switch unit 220 is turned on), the first terminal of the third switch unit 230 is disconnected from the third terminal of the third switch unit 230, the second terminal of the third switch unit 230 is disconnected from the third terminal of the third switch unit 230, the first terminal of the fourth switch unit 240 is disconnected from the third terminal of the fourth switch unit 240, the second terminal of the fourth switch unit 240 is disconnected from the third terminal of the fourth switch unit 240, and the output terminal of the test voltage output module 20 outputs the first test voltage.
[0132] Exemplarily, as Figure 4As shown, by adjusting / transforming the voltage levels of the fourth switch control signal CP1, the fifth switch control signal CP2, the sixth switch control signal CN1, the seventh switch control signal CN2, the eighth switch control signal SP1, the ninth switch control signal SP2, the tenth switch control signal SN1, and the eleventh switch control signal SN2, embodiments of the present invention can achieve the connection between the first end and the second end of the first switch unit 210, the connection between the first end and the second end of the second switch unit 220, the disconnection between the first end and the third end of the third switch unit 230, the disconnection between the second end and the third end of the third switch unit 230, the disconnection between the first end and the third end of the fourth switch unit 240, and the disconnection between the second end and the third end of the fourth switch unit 240.
[0133] In a possible implementation manner, in the high-voltage stress test mode, the source of the third transistor Q3, the first end of the second switch unit 220, the third end of the second switch unit 220, the gate of the fifth transistor Q5, the output end of the test voltage output module 20 are connected, and / or, the drain of the fourth transistor Q4, the fourth end of the second switch unit 220, the gate of the sixth transistor Q6 and the output end of the test voltage output module 20 are connected to output a corresponding second test voltage.
[0134] Exemplarily, as Figure 4 shown, in the high-voltage stress test mode, the voltage levels of the tenth switch control signal SN1, the eleventh switch control signal SN2, the sixth switch control signal CN1 and the seventh switch control signal CN2 can be adjusted / transformed to connect the gate terminal of the sixth transistor Q6 and the drain terminal of the fourth transistor Q4, and connect the drain terminal of the sixth transistor Q6 to the output end of the test voltage output module 20, so that the output end of the test voltage output module 20 outputs a second test voltage with a high bias voltage to at least one pad of the chip under test 30.
[0135] Exemplarily, as Figure 4As shown, in the high-voltage stress test mode, the voltage levels of the eighth switch control signal SP1, the ninth switch control signal SP2, the fourth switch control signal CP1, and the fifth switch control signal CP2 can also be adjusted / transformed, so that the gate terminal of the fifth transistor Q5 is connected to the drain terminal of the third transistor Q3, and the drain terminal of the fifth transistor Q5 is connected to the output terminal of the test voltage output module 20, thereby enabling the output terminal of the test voltage output module 20 to output a second test voltage with a high bias voltage to at least one pad of the device under test 30.
[0136] In a possible implementation, in the off mode, both the fifth transistor Q5 and the sixth transistor Q6 are turned off.
[0137] Exemplarily, as Figure 4 shown, the fifth transistor Q5 and the sixth transistor Q6 can be turned off by adjusting / transforming the voltage levels of the eleventh switch control signal SN2, the eighth switch control signal SP1, the tenth switch control signal SN1, the ninth switch control signal SP2, the sixth switch control signal CN1, the seventh switch control signal CN2, the fourth switch control signal CP1, and the fifth switch control signal CP2, so as to enter the off mode.
[0138] Please refer to Figure 5a 、 Figure 5b , Figure 5a 、 Figure 5b which show the simulation diagrams of testing using the test power supply device according to the embodiments of the present invention.
[0139] Exemplarily, assuming that the power supply voltage VDDA is 9V and the power supply of each switch component is 18V, as Figure 5a shown, the embodiments of the present invention can achieve that the third terminal of the second switch unit 220, the third terminal of the third switch unit 230 ( Figure 4 AA in), the fourth terminal of the second switch unit 220, and the fourth terminal of the third switch unit 230 ( Figure 4 AB in) are simultaneously pulled high to a high level or simultaneously pulled low to a low level.
[0140] In an example, as Figure 5a and Figure 4As shown, in an embodiment of the present utility model, the fourth switch control signal CP1 can be used to control the fourth switch component SW4 and the eighth switch component SW8 to conduct (CP1 close), the fifth switch control signal CP2 can be used to control the fifth switch component SW5 and the ninth switch component SW9 to disconnect (CP2 OPEN), the eighth switch control signal SP1 can be used to control the twelfth switch component SW12 to conduct (SP1 CLOSE), and the ninth switch control signal SP2 can be used to control the thirteenth switch component SW13 to disconnect (SP2 OPEN), so that the third terminal of the second switch unit 220 and the third terminal of the third switch unit 230 (AA) are at a high level (AA = H, where H represents a high level).
[0141] In one example, as Figure 5a and Figure 4 shown, in an embodiment of the present utility model, the sixth switch control signal CN1 can be used to control the sixth switch component SW6 and the tenth switch component SW10 to both conduct (CN1 CLOSE), the seventh switch control signal CN2 can be used to control the seventh switch component SW7 and the eleventh switch component SW11 to both conduct (CN2 CLOSE), the tenth switch control signal SN1 can be used to control the fourteenth switch component SW14 to conduct (SN1 CLOSE), and the eleventh switch control signal SN2 can be used to control the fifteenth switch component SW15 to disconnect (SN2 OPEN), so as to raise the fourth terminal of the second switch unit 220 and the fourth terminal of the third switch unit 230 (AB) to a high level (AB = H).
[0142] In one example, as Figure 5a and Figure 4 shown, in an embodiment of the present utility model, the fourth switch control signal CP1 can be used to control the fourth switch component SW4 and the eighth switch component SW8 to conduct (CP1 close), the fifth switch control signal CP2 can be used to control the fifth switch component SW5 and the ninth switch component SW9 to disconnect (CP2 OPEN), the eighth switch control signal SP1 can be used to control the twelfth switch component SW12 to disconnect (SP1 OPEN), and the ninth switch control signal SP2 can be used to control the thirteenth switch component SW13 to conduct (SP2 CLOSE), so that the third terminal of the second switch unit 220 and the third terminal of the third switch unit 230 (AA) are pulled down to a low level (AA = L, where L represents a low level).
[0143] In one example, as Figure 5a and Figure 4As shown, in the embodiment of the present utility model, the sixth switch assembly SW6 and the tenth switch assembly SW10 can be controlled to be turned on (CN1 CLOSE) by the sixth switch control signal CN1, the seventh switch assembly SW7 and the eleventh switch assembly SW11 can be controlled to be turned off (CN2 OPEN) by the seventh switch control signal CN2, the fourteenth switch assembly SW14 can be controlled to be turned off (SN1 OPEN) by the tenth switch control signal SN1, and the fifteenth switch assembly SW15 can be controlled to be turned on (SN2 CLOSE) by the eleventh switch control signal SN2, so as to pull down the fourth terminal of the second switch unit 220 and the fourth terminal of the third switch unit 230 (AB) to a low level (AB = L).
[0144] By making the third terminal of the second switch unit 220, the third terminal of the third switch unit 230 (AA), the fourth terminal of the second switch unit 220, and the fourth terminal of the third switch unit 230 (AB) be pulled up to a high level simultaneously, or be pulled down to a low level simultaneously, the embodiment of the present utility model can implement the high-voltage stress test HVS of the AA or AB branch.
[0145] In one example, as Figure 5b and Figure 4 shown, the embodiment of the present utility model can pull up the third terminal of the second switch unit 220 and the third terminal of the third switch unit 230 (AA) to a high level, and pull down the fourth terminal of the second switch unit 220 and the fourth terminal of the third switch unit 230 (AB) to a low level, and then pull up the output point to a high level.
[0146] In one example, as Figure 5b and Figure 4As shown, in the embodiment of the present utility model, the fourth switch control signal CP1 can be used to control the fourth switch component SW4 and the eighth switch component SW8 to conduct (CP1 close), the fifth switch control signal CP2 can be used to control the fifth switch component SW5 and the ninth switch component SW9 to disconnect (CP2 OPEN), the eighth switch control signal SP1 can be used to control the twelfth switch component SW12 to conduct (SP1 CLOSE), and the ninth switch control signal SP2 can be used to control the thirteenth switch component SW13 to disconnect (SP2 OPEN), so that the third terminal of the second switch unit 220 and the third terminal of the third switch unit 230 (AA) are at a high level (AA = H). At the same time, in one example, in the embodiment of the present utility model, the sixth switch control signal CN1 can be used to control the sixth switch component SW6 and the tenth switch component SW10 to conduct (CN1 CLOSE), the seventh switch control signal CN2 can be used to control the seventh switch component SW7 and the eleventh switch component SW11 to disconnect (CN2 OPEN), the tenth switch control signal SN1 can be used to control the fourteenth switch component SW14 to disconnect (SN1 OPEN), and the eleventh switch control signal SN2 can be used to control the fifteenth switch component SW15 to conduct (SN2 CLOSE), so as to pull down the fourth terminal of the second switch unit 220 and the fourth terminal of the third switch unit 230 (AB) to a low level (AB = L).
[0147] In a possible implementation manner, the test power supply device of the embodiment of the present utility model may further include a control module to output the first switch control signal SL_B, the second switch control signal SW_B, the third switch control signal SH_B, the fourth switch control signal CP1, the fifth switch control signal CP2, the sixth switch control signal CN1, the seventh switch control signal CN2, the eighth switch control signal SP1, the ninth switch control signal SP2, the tenth switch control signal SN1, and the eleventh switch control signal SN2. Of course, the specific implementation manner of the control module in the embodiment of the present utility model is not limited, and those skilled in the art can set it according to the actual situation and needs.
[0148] In one example, the control module may include a processing component. Exemplarily, the processing component includes, but is not limited to, a separate processor, or discrete components, or a combination of a processor and discrete components. The processor may include a controller in an electronic device that has a function of executing instructions. The processor may be implemented in any suitable manner. For example, it may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Inside the processor, the executable instructions may be executed through hardware circuits such as logic gates, switches, application specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.
[0149] In a possible implementation manner, each control signal may be pre-configured and stored in the storage module. The control module generates a first switch control signal SL_B, a second switch control signal SW_B, a third switch control signal SH_B, a fourth switch control signal CP1, a fifth switch control signal CP2, a sixth switch control signal CN1, a seventh switch control signal CN2, an eighth switch control signal SP1, a ninth switch control signal SP2, a tenth switch control signal SN1, and an eleventh switch control signal SN2 by retrieving the stored information in the storage module. The specific implementation manner of the control module in the embodiments of the present invention is not limited, and those skilled in the art may set it according to the actual situation and needs.
[0150] In one example, the storage module may include a computer-readable storage medium, which can be a tangible device that can hold and store instructions used by an instruction execution device. The computer-readable storage medium can be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. More specific examples (non-exhaustive list) of the computer-readable storage medium include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), programmable read-only memory (PROM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanical encoding devices, such as punched cards or raised structures in grooves storing instructions thereon, and any suitable combination of the above. The computer-readable storage medium used herein is not construed as an instantaneous signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., optical pulses through an optical fiber cable), or electrical signals transmitted through wires.
[0151] The test power supply device of the embodiment of the present utility model can switch among multiple working modes, including normal test mode, high-voltage stress test mode, or shutdown mode. Thus, the embodiment of the present utility model can be applied to CP testing to implement chip degradation testing based on a high bias voltage for at least one electronic chip, thereby picking out chips that do not meet the standards or have been damaged.
[0152] According to one aspect of the present utility model, a chip test system is provided, and the system includes the above-mentioned test power supply device.
[0153] The embodiments of the present utility model have been described above. The above description is exemplary and not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art in the technical field without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technologies in the market, or to enable other ordinary skill in the art in the technical field to understand the embodiments disclosed herein.
Claims
1. A test power supply device, characterized in that: The device comprises a bias voltage output module and a test voltage output module, wherein the bias voltage output module is connected to the test voltage output module, and the test voltage output module is connected to at least one chip to be tested, wherein the bias voltage output module and the test voltage output module are configured to operate in at least one of a normal test mode, a high voltage stress test mode, and a shutdown mode, wherein: In the normal test mode, the bias voltage output module outputs a first bias voltage, and the test voltage output module generates a first test voltage according to the first bias voltage to test the chip to be tested; In the high-voltage stress test mode, the bias voltage output module outputs a second bias voltage, and the test voltage output module generates at least one second test voltage according to the second bias voltage to test the chip to be tested, wherein the second bias voltage is higher than the first bias voltage, and the second test voltage is higher than the first bias voltage; In the shutdown mode, the bias voltage output module and the test voltage output module do not output voltage.
2. The device according to claim 1, characterized in that The bias voltage output module includes a bias transistor, a first current source, a first switch component, a second switch component, and a third switch component, wherein: The positive terminal of the first current source is used to receive a power supply voltage, and the negative terminal of the first current source is connected to the drain terminal of the bias transistor, the gate terminal of the bias transistor, the first terminal of the first switch component, and the first terminal of the second switch component. The source terminal of the bias transistor is connected to the second terminal of the first switch component and is grounded. The second end of the second switch component and the first end of the third switch component are connected to serve as the output end of the bias voltage output module. The second end of the third switch component is used to receive the power supply voltage.
3. The device according to claim 2, characterized in that When the first switch component is disconnected, the second switch component is turned on, and the third switch component is disconnected, the bias voltage output module is configured to be in a normal test mode; When the first switch component is disconnected or turned on, the second switch component is disconnected, and the third switch component is turned on, the bias voltage output module is configured to be in a high voltage stress test mode; When the first switch component is turned on, the second switch component is turned off, and the third switch component is turned off, the bias voltage output module is configured to be in a shutdown mode.
4. The device according to claim 1, characterized in that The test voltage output module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first switch unit, a second switch unit, a third switch unit, and a fourth switch unit, wherein: The source terminal of the first transistor, the source terminal of the third transistor, the source terminal of the fifth transistor, the first terminal of the third switch unit and the first terminal of the fourth switch unit are connected to the output terminal of the bias voltage output module for receiving the first bias voltage or the second bias voltage. The drain of the first transistor is connected to the first end of the first switch unit, and the drain of the second transistor is connected to the second end of the first switch unit. The gate of the first transistor and the gate of the third transistor are both connected to the third end of the first switch unit. The gate of the second transistor and the gate of the fourth transistor are both connected to the fourth end of the first switch unit. The drain of the third transistor is connected to the first end of the second switch unit, and the drain of the fourth transistor is connected to the second end of the second switch unit. The gate of the fifth transistor is connected to the third end of the second switch unit and the third end of the third switch unit, and the second end of the third switch unit is grounded. The gate of the sixth transistor is connected to the fourth terminal of the second switch unit and the third terminal of the fourth switch unit. The source of the second transistor, the source of the fourth transistor, the second end of the fourth switch unit, and the source of the sixth transistor are all grounded. The drain of the fifth transistor is connected to the drain of the sixth transistor as the output end of the test voltage output module.
5. The device according to claim 4, characterized in that The first switch unit includes a fourth switch component, a fifth switch component, a sixth switch component, a seventh switch component, and a second current source, wherein: The first end of the fourth switch component serves as the first end of the first switch unit, The second end of the fourth switch component is connected to the first end of the fifth switch component as the third end of the first switch unit, The second end of the fifth switch component is connected to the positive end of the second current source, and the negative end of the second current source is connected to the first end of the seventh switch component. The second end of the seventh switch component is connected to the first end of the sixth switch component as the fourth end of the first switch unit, The second end of the sixth switch component serves as the second end of the first switch unit.
6. The device according to claim 4, characterized in that The second switch unit includes an eighth switch component, a ninth switch component, a tenth switch component, an eleventh switch component, and a third current source, wherein: The first end of the eighth switch component serves as the first end of the second switch unit, The second end of the eighth switch component is connected to the first end of the ninth switch component as the third end of the second switch unit, The second end of the ninth switch component is connected to the positive end of the third current source, and the negative end of the third current source is connected to the first end of the eleventh switch component. The second end of the eleventh switch component is connected to the first end of the tenth switch component as the fourth end of the second switch unit, The second end of the tenth switch component serves as the second end of the second switch unit.
7. The device according to claim 4, characterized in that The third switch unit includes a twelfth switch component and a thirteenth switch component, wherein: The first end of the twelfth switch component serves as the first end of the third switch unit, The second end of the twelfth switch component is connected to the first end of the thirteenth switch component as the third end of the third switch unit, The second end of the thirteenth switch component serves as the second end of the third switch unit.
8. The device according to claim 4, characterized in that The fourth switch unit includes a fourteenth switch component and a fifteenth switch component, wherein: The first end of the fourteenth switch component serves as the first end of the fourth switch unit, The second end of the fourteenth switch component is connected to the first end of the fifteenth switch component as the third end of the fourth switch unit, The second end of the fifteenth switch component serves as the second end of the fourth switch unit.
9. The device according to any one of claims 4 to 8, characterized in that: In the normal test mode, the first end of the first switch unit is connected to the second end of the first switch unit, the first end of the second switch unit is connected to the second end of the second switch unit, the first end of the third switch unit is disconnected from the third end of the third switch unit, the second end of the third switch unit is disconnected from the third end of the third switch unit, the first end of the fourth switch unit is disconnected from the third end of the fourth switch unit, the second end of the fourth switch unit is disconnected from the third end of the fourth switch unit, and the output end of the test voltage output module outputs the first test voltage. In the high-voltage stress test mode, the source of the third transistor, the first end of the second switch unit, the third end of the second switch unit, the gate of the fifth transistor, and the output end of the test voltage output module are connected, and / or the drain of the fourth transistor, the fourth end of the second switch unit, the gate of the sixth transistor and the output end of the test voltage output module are connected to output a corresponding second test voltage. In the off mode, the fifth transistor and the sixth transistor are both turned off.
10. The device according to claim 1, characterized in that The chip to be tested includes at least one of a touch chip, a display driver chip, a display driver and touch integrated single chip, a fingerprint recognition chip, a digital processing chip, an FPGA chip, a CPLD chip, a power management chip, a baseband chip, and a substrate management chip.
11. A chip testing system, characterized in that: The system comprises the test power supply device according to any one of claims 1-9.