Interface detection device

Abstract

An interface detection device is provided. In the embodiment of the invention, the power line switching circuit and the data line switching circuit are additionally arranged in the interface detection equipment, so that the system controller can independently conduct any one of the four power lines in the detected device. Therefore, according to the interface detection equipment provided by the embodiment of the invention, the power supply function of each power supply pin pair of the interface can be detected one by one in the test process, so that a stricter and more comprehensive Type-C interface test is realized.

Description

Technical Field

[0001] The present disclosure relates to an interface detection device. Background Art

[0002] Currently, more and more consumer electronic products mostly include components such as a battery, a charger, and a microcontroller unit (MCU) with a Type-C interface. These consumer electronic products include electronic devices such as mobile phones, tablet computers, laptop computers, speakers, and headphones.

[0003] The Type-C interface is a new USB interface standard with 24 pins. These 24 pins include paired power pins, data pins, configuration pins, etc. Each pair of Type-C interfaces can achieve a data transmission rate of up to 10 Gbps and support multiple functions such as power supply, video output, and peripheral connection. With its characteristics of high bandwidth, diverse functions, and reversible plugs, the application of the Type-C interface is becoming more and more extensive.

[0004] Currently, on the production line, it is necessary to test the Type-C interface to verify the integrity of its pin functions, signal paths, and interconnection with external devices. Conventionally, during the test, the power supply pins (Voltage Bus, VBUS) in multiple pairs of power pins are usually commonly connected to the same power line, and the ground pins in multiple pairs of power pins are connected to the same ground line to directly measure the charging function of the Type-C interface. At the same time, multiple data pins may also be commonly connected to the same data line to test the communication function of the Type-C interface.

[0005] However, in such a test scheme, it is impossible to separately test the working state of each power supply pin or ground pin. This parallel connection method equates all power lines (or ground lines) to one line and cannot separately detect whether each line fails.

[0006] For some devices that need to provide a stable and relatively high voltage through the Type-C interface, more strict and comprehensive testing of the Type-C interface is required to separately control and measure the performance of each pin during the test. Therefore, it is necessary to improve such a test scheme. Summary of the Utility Model

[0007] To solve the above problems, the present disclosure provides an interface detection device, characterized in that the interface detection device includes: a power supply line switching circuit, including: a first power supply line switch coupled to a first power supply line, the first power supply line switch being configured to conduct a path for supplying power to a first power pin pair at the interface of the device under test; a second power supply line switch coupled to a second power supply line, the second power supply line switch being configured to conduct a path for supplying power to a second power pin pair at the interface of the device under test; a data line switching circuit, including: a first data line switch pair coupled to a first data line pair, the first data line switch pair being configured to conduct a path for receiving a first detection result from a first data pin pair at the interface of the device under test, wherein the first detection result includes at least one of a detection result for the first power pin pair and a detection result for the second power pin pair; a second data line switch pair coupled to a second data line pair, the second data line switch pair being configured to conduct a path for receiving a second detection result from a second data pin pair at the interface of the device under test, wherein the second detection result includes at least one of a detection result for the first power pin pair and a detection result for the second power pin pair; and a system controller, the system controller being coupled to the power supply line switching circuit and the data line switching circuit, wherein the system controller is configured to: control the conduction and shutdown of the first power supply line switch, the second power supply line switch, the first data line switch pair, and the second data line switch pair.

[0008] In an embodiment of the present disclosure, by adding a power supply line switching circuit and a data line switching circuit to the interface detection device, the system controller can individually conduct any one of the four power supply lines in the device under test. Therefore, the interface detection device according to the embodiment of the present disclosure can individually detect the power supply functions of each power pin pair of the interface during the test process, thereby achieving a more stringent and comprehensive Type-C interface test. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some exemplary embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0010] Figure 1 shows an interface detection device according to an embodiment of the present disclosure;

[0011] Figure 2 shows a detailed view of an interface pin assembly according to an embodiment of the present disclosure;

[0012] Figure 3Shows a detailed diagram of the interface of the device under test according to an embodiment of the present disclosure;

[0013] Figure 4 Shows another schematic diagram of the interface detection device according to an embodiment of the present disclosure;

[0014] Figure 5 Shows a flowchart of the interface detection device performing a detection process according to an embodiment of the present disclosure;

[0015] Figure 6 Shows another schematic diagram of the interface detection device according to an embodiment of the present disclosure;

[0016] Figure 7 Shows a flowchart of the interface detection device performing a detection process according to an embodiment of the present disclosure;

[0017] Figure 8 Shows a flowchart of the interface detection method according to an embodiment of the present disclosure;

[0018] Figure 9 Shows a flowchart of the interface detection method according to an embodiment of the present disclosure. Detailed implementation manners

[0019] To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. And, without conflict, the embodiments in the present disclosure and the features in the embodiments may be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0020] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The words such as "including" or "comprising" used in the present disclosure mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. The words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "inside", "outside", "above", "below", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0021] It should be noted that the sizes and shapes of the figures in the drawings do not reflect the true proportions, and the purpose is only to schematically illustrate the present disclosure. Also, the same or similar reference numerals throughout indicate the same or similar elements or elements having the same or similar functions.

[0022] Currently, more and more consumer electronic products mostly include components such as batteries, chargers, and microcontroller units (MCUs) with Type-C interfaces. These consumer electronic products include electronic devices such as mobile phones, tablets, laptops, speakers, and headphones.

[0023] The Type-C interface is a new USB interface standard with 24 pins. These 24 pins include: 4 pairs of TX / RX differential pins, 2 pairs of USB D+ / D- pins, a pair of SBU pins, 2 CC pins, 4 VBUS pins, and 4 ground pins. The Type-C interface can achieve a data transfer rate of up to 10 Gbps and support multiple functions such as power supply, video output, and peripheral connection. With its characteristics of high bandwidth, diverse functions, and a reversible plug, the application of the Type-C interface is becoming more and more extensive.

[0024] For these devices under test (DUTs) with Type-C interfaces, specialized test equipment and test schemes are required to detect the integrity of the functions of each pin in the Type-C interface. Among them, the DUT includes any terminal device integrated with a Type-C interface, such as a mobile phone, a tablet, a laptop, etc.

[0025] Traditionally, the test equipment dedicated to testing the Type-C interface of the DUT includes: a test chassis, a Type-C interface function test carrier board, a test result display, test cables, and test software, etc. The Type-C interface of the test equipment is connected to the Type-C interface of the DUT to test each pin of the Type-C interface of the DUT.

[0026] Currently, on the production line, it is necessary to test the Type-C interface to verify the integrity of its pin functions, signal paths, and interconnection with external devices. Traditionally, during the test process, usually, the power supply pins (Voltage Bus, VBUS) in multiple pairs of power pins in the interface detection device are commonly connected to the same power line, and the ground pins in multiple pairs of power pins are connected to the same ground line to directly measure the charging function of the Type-C interface. At the same time, multiple data pins may also be commonly connected to the same data line to test the communication function of the Type-C interface.

[0027] However, in such a test scheme, it is impossible to test the working status of each power supply pin or ground pin separately. This parallel connection method equivalentizes all power lines (or ground lines) into one line, and it is impossible to separately detect whether each line has a fault.

[0028] For some devices that need to provide a stable and relatively high voltage through the Type-C interface, more strict and comprehensive Type-C interface tests are required to separately control and measure the performance of each pin during the test process. Therefore, it is necessary to improve such a test scheme.

[0029] Accordingly, the present disclosure provides an interface detection device, characterized in that the interface detection device includes: a power line switching circuit, including: a first power line switch coupled to a first power line, the first power line switch being configured to conduct a path for supplying power to a first power pin pair at the interface of the device under test; a second power line switch coupled to a second power line, the second power line switch being configured to conduct a path for supplying power to a second power pin pair at the interface of the device under test; a data line switching circuit, including: a first data line switch pair coupled to a first data line pair, the first data line switch pair being configured to conduct a path for receiving a first detection result from a first data pin pair at the interface of the device under test, wherein the first detection result includes at least one of a detection result for the first power pin pair and a detection result for the second power pin pair; a second data line switch pair coupled to a second data line pair, the second data line switch pair being configured to conduct a path for receiving a second detection result from a second data pin pair at the interface of the device under test, wherein the second detection result includes at least one of a detection result for the first power pin pair and a detection result for the second power pin pair; and a system controller, the system controller being coupled to the power line switching circuit and the data line switching circuit, wherein the system controller is configured to: control the conduction and shutdown of the first power line switch, the second power line switch, the first data line switch pair, and the second data line switch pair.

[0030] In an embodiment of the present disclosure, due to the existence of the power line switching circuit and the data line switching circuit, the system controller can separately conduct any one of the four power lines in the device under test. Therefore, the interface detection device according to the embodiment of the present disclosure can detect the power supply function of each power pin pair of the interface one by one during the test process.

[0031] In addition, embodiments of the present disclosure can further achieve that as long as the second power pin pair works normally, the micro - control unit (MCU) and the power supply components inside the device under test can maintain the powered - on state, and avoid repeatedly restarting the MCU and the power supply components inside the device under test, by guiding the power supply path to the second power pin pair at the interface of the device under test while keeping the power supply path to the first power pin pair connected to the first power supply, and then disconnecting the power supply path to the first power pin pair after guiding the power supply path to the second power pin pair at the interface of the device under test.

[0032] Next, the present disclosure will be further described with reference to the respective drawings.

[0033] Figure 1 Fig. 7 shows an interface detection device 100 according to an embodiment of the present disclosure. Figure 2 Fig. 9 shows a detailed view of an interface pin assembly 1006 according to an embodiment of the present disclosure. Figure 3 Fig. 11 shows a detailed view of an interface 2002 according to an embodiment of the present disclosure.

[0034] As Figure 1 shown, the interface detection device 100 optionally includes one or more of a power line switching circuit 1002, a data line switching circuit 1004, an interface pin assembly 1006, a system controller 1008, an output circuit 1010, and an adapter 1012. The interface detection device 100 may also include more or fewer components, and the present disclosure is not limited thereto.

[0035] The power line switching circuit 1002 includes: a first power line switch 10024 coupled to a first power line 10020. The first power line switch 10024 is used to guide the power supply path to the first power pin pair Power A' at the interface 2002 of the device under test 200.

[0036] The power line switching circuit 1002 further includes: a second power line switch 10026 coupled to a second power line 10022. The second power line switch 10026 is used to guide the power supply path to the second power pin pair Power B' at the interface 2002 of the device under test 200.

[0037] Optionally, the first power line 10020 and the second power line 10022 can be VBUS (Voltage Bus) power lines for powering and charging the device under test. Optionally, the power line switching circuit 1002 may include 4 power lines (the first power line 10020, the second power line 10022, and a third power line and a fourth power line not shown), which are respectively controlled by independent power line switches.

[0038] For example, the first power supply line switch 10024 can be used to independently enable or disconnect the path for supplying power to the first power pin pair Power A' at the interface 2002 of the device under test 200. When the first power supply line switch 10024 is turned on, it can deliver the working voltage or charging current to the device under test; conversely, disconnecting the first power supply line switch 10024 will cut off the power output of the first power supply line 10020.

[0039] Optionally, the type of the interface 2002 of the device under test 200 is Type-C. The first power pin pair Power A' and the second power pin pair Power B' both include a power supply pin (VBUS) and a ground pin (GND). The first power pin pair Power A' and the second power pin pair Power B' are connected in parallel in the interface 2002 of the device under test 200.

[0040] Optionally, as Figure 3 shown, the interface 2002 of the device under test 200 includes four pairs of power pin pairs (Power A', Power B', Power C', and Power D'). These four pairs of power pin pairs include four power supply (VBUS) pins (A9', B9', A5', B5') and four ground (GND) pins (A12', B12', A8', B8'). The four VBUS pins (A9', B9', A5', B5') are connected in parallel to receive the working voltage and charging current from the connected external device. The four GND pins (A12', B12', A8', B8') are also connected in parallel to form a common ground reference. Optionally, all VBUS voltages and data signals are referenced relative to these GND pins. The GND pins are connected to the ground terminal of the interface detection device to form the other half of the current loop, ensuring the normal operation of power supply and data transmission.

[0041] Optionally, the device under test 200 includes a power supply component (charger) and a microcontroller MCU. Optionally, the power supply component obtains the current corresponding to 5V or a higher voltage from the interface detection device 100 through the first power supply line 10020 (or the second power supply line 10022, or a third power supply line not shown, or a fourth power supply line), and thus the power supply component is charged. The power supply component has a built-in power management circuit to monitor the battery voltage, current, remaining capacity and other power information in real time. These power information can be used as the detection results of the corresponding power pin pairs. The power supply component transmits the detection results corresponding to the power pin pairs to the micro control unit MCU, and the micro control unit MCU transmits them to the interface detection device through a data channel (for example, the first data line pair 10040 or the second data line pair 10042 detailed later).

[0042] Optionally, the data line switching circuit 1004 includes: a first data line switch pair 10044 coupled to the first data line pair 10040. The first data line switch pair 10044 is used to conduct a path for receiving a first detection result from a first data pin pair of the interface 2002 of the device under test 200 to USB A'. Wherein, the first detection result includes at least one of a detection result for the first power pin pair Power A' and a detection result for the second power pin pair Power B'.

[0043] Optionally, the first data line pair 10040 is composed of two parallel differential data lines D+ and D-, which are communication lines for transmitting data through the interface pin assembly 1006. Specifically, D+ and D- form a pair of differential data line pairs. When transmitting the data "1", the voltage of the D+ line is higher than the fixed voltage difference of the D- line. When transmitting "0", the voltage of the D- line is higher than the D+ line. The device under test 200 determines whether "1" or "0" is received by detecting the voltage difference between D+ and D-. D+ and D- transmit various data in this differential manner between the interface detection device 100 and the device under test 200, such as at least one of a detection result for the first power pin pair Power A' and a detection result for the second power pin pair Power B'. The differential data line pair D+ and D- using differential transmission can effectively suppress noise interference to improve the reliability of data transmission.

[0044] Optionally, the first data line switch pair 10044 includes two independent switches or switch circuits, which separately control and switch the connection states of the differential data line pair D+ and D- in the first data line pair 10040. For example, one switch circuit is connected to the D+ line, and the other switch circuit is connected to the D- line, and the D+ and D- two data lines can be enabled or disabled in any combination. When both switch circuits are turned on, D+ and D- are both connected, and data can be normally transmitted between the two lines in a differential manner; when either the D+ or D- line is disconnected, data cannot be effectively transmitted; when both lines are disconnected, the data path is blocked.

[0045] The data line switching circuit 1004 further includes: a second data line switch pair 10046 coupled to the second data line pair 10042. The second data line switch pair 10046 is used to conduct a path for receiving a second detection result from a second data pin pair of the interface 2002 of the device under test 200 to USB B'. Wherein, the second detection result includes at least one of a detection result for the first power pin pair Power A' and a detection result for the second power pin pair Power B'. The working principles of the second data line pair 10042 and the second data line switch pair 10046 are the same as those of the first data line pair 10040 and the first data line switch pair 10044, and will not be elaborated here.

[0046] As Figure 2 shown, the interface pin component 1006 includes: a first power test pin pair Power A and a second power test pin pair Power B.

[0047] The first power test pin pair Power A includes a power supply test pin A4 and a ground test pin A1. Among them, the type of the power supply test pin A4 is VBUS, and the type of the ground test pin is GND. The power supply test pin A4 is coupled to the first power line 10020. Among them, when the first power pin pair Power A' at the interface 2002 of the first power test pin pair Power A and the device under test 200 is connected, through the control of the first power line switch 10024, a path for supplying power to the first power pin pair Power A' at the interface 2002 of the device under test 200 is conducted.

[0048] The second power test pin pair Power B includes a power supply test pin A9 and a ground test pin A12. The power supply test pin A9 is coupled to the second power line 10022. Among them, when the second power pin pair Power B' at the interface 2002 of the second power test pin pair Power B and the device under test 200 is connected, through the control of the second power line switch 10026, a path for supplying power to the second power pin pair Power B' at the interface 2002 of the device under test 200 is conducted.

[0049] The interface pin component 1006 further includes: a first data test pin pair USB A and a second data test pin pair USBB. The first data test pin pair USB A is coupled to the first data line pair 10040. The second data test pin pair USB B is coupled to the second data line pair 10042.

[0050] The first data test pin pair USB A includes a pin A6 and a pin A7, which are respectively connected to the data line D+ and the data line D- in the first data line pair 10040. When the first data test pin pair USB A is connected or in contact with the first data pin pair USB A' or the second data pin pair USB B' at the interface 2002 of the device under test 200, through the control of the first data line switch pair 10044, a first detection result is received from the first data pin pair USB A' at the interface 2002 of the device under test 200. Of course, the present disclosure is not limited thereto.

[0051] The second data test pin pair for USB B includes pin B6 and pin B7, which are respectively connected to data line D+ and data line D- in the second data line pair 10042. When the first data pin pair for USB A' or the second data pin pair for USB B' at the interface 2002 of the device under test 200 is connected, the second detection result is received from the second data pin pair for USB B' at the interface 2002 of the device under test 200 under the control of the second data line switch pair 10046.

[0052] Optionally, the system controller 1008 is coupled to the power line switching circuit 1002 and the data line switching circuit 1004. Among them, the system controller 1008 is configured to control the conduction and cut-off of the first power line switch 10024, the second power line switch 10026, the first data line switch pair 10044, and the second data line switch pair 10046.

[0053] For example, the system controller 1008 may be configured to: control the first power line switch 10024 to conduct to establish a path for supplying power to the first power pin pair Power A' at the interface 2002 of the device under test 200, and control the first data line switch pair 10044 to conduct to receive the detection result for the first power pin pair Power A' via the first data line pair 10040.

[0054] For example, the system controller 1008 is further configured to: control the second power line switch 10026 to conduct to establish a path for supplying power to the second power pin pair Power B' at the interface 2002 of the device under test 200, and control the first data line switch pair 10044 or the second data line switch pair 10046 to conduct to receive the detection result for the second power pin pair Power B' via the first data line pair 10040 or the second data line pair 10042.

[0055] Specifically, as described above, the data transmitted by the first data line pair 10040 or the second data line pair 10042 is a differential voltage, and this differential voltage can be encoded into a bit stream of "1" or "0". Whether it is the detection result for the first power pin pair Power A' or the detection result for the second power pin pair Power B', they are both presented in the form of a bit stream. The system controller 1008 decodes and stores the received first detection result and second detection result.

[0056] Optionally, the output circuit 1010 is coupled to the system controller 1008, where the output circuit is configured to output at least one of the first detection result and the second detection result. Specifically, the output circuit 1010 can read at least one of the first detection result and the second detection result from the memory in the system controller 1008, and accordingly send the first detection result or the second detection result to a device for presenting the first detection result or the second detection result. The present disclosure is not limited thereto.

[0057] Optionally, the adapter 1012 is coupled to the power line switching circuit 1002 and is configured to supply power to the first power line 10020 and the second power line 10022.

[0058] Due to the existence of the power line switching circuit 1002 and the data line switching circuit 1004, the system controller 1008 can independently conduct any one of the four power lines in the device under test 200. Therefore, the interface detection device 100 according to the embodiment of the present disclosure can detect the power supply function of each power pin pair (Power A’, Power B’, Power C’, and Power D’) of the interface 2002 one by one during the test process.

[0059] In an embodiment of the present disclosure, the system controller 1008 can first conduct the power line corresponding to Power A (i.e., the first power line 10020), measure the power supply function of Power A’, receive the measurement result for Power A’, and then disconnect the power line corresponding to Power A (i.e., the first power line 10020). Then, conduct the power line corresponding to Power B (i.e., the second power line 10022), measure the power supply function of Power B’, receive the measurement result for Power B’, and then disconnect the power line corresponding to Power B. Measure the power supply functions of Power C’ and Power D’ in a similar manner in sequence. However, during such a test process, after each pair of power pins is detected, it is necessary to disconnect the power connection of the device under test 200 at the interface 2002 and may cause the micro control unit MCU and the power supply components inside the device under test 200 to lose power. When detecting another pair of power pins, it is necessary to power on the micro control unit MCU and the power supply components inside the device under test 200 again, and restart the micro control unit MCU and the power supply components. Therefore, it may be necessary to repeatedly restart the micro control unit MCU and the power supply components of the DUT four times to complete a full test of the interface 2002.

[0060] To this end, the system controller 1008 according to another embodiment of the present disclosure is further configured to: after receiving the detection result for the first power pin pair Power A' via the first data line pair 10040, control the second power line switch 10026 to conduct, so as to conduct the path for supplying power to the second power pin pair Power B' at the interface 2002 of the device under test 200 while maintaining the path for supplying power to the first power pin pair Power A'. Then, after controlling the second power line switch 10026 to conduct to conduct the path for supplying power to the second power pin pair Power B' at the interface 2002 of the device under test 200, control the first power line switch 10024 to disconnect to disconnect the path for supplying power to the first power pin pair Power A'. Next, after controlling the first power line switch 10024 to disconnect to disconnect the path for supplying power to the first power pin pair Power A', control the first data line switch pair 10044 or the second data line switch pair 10046 to conduct to receive the detection result for the second power pin pair Power B' via the first data line pair 10040 or the second data line pair 10042.

[0061] At this time, when the path for supplying power to the first power pin pair Power A' is conducted, or when the path for supplying power to the second power pin pair Power B' is conducted, the micro control unit MCU of the device under test 200 is in a powered-on state. Among them, the detection result of the first power pin pair Power A' is read by the micro control unit MCU from the power supply component of the device under test 200 and is used to indicate the status information of the power supply component of the device under test 200 after being charged through the first power pin pair Power A'. The detection result of the second power pin pair Power B' is read by the micro control unit MCU from the power supply component of the device under test 200 and is used to indicate the status information of the power supply component of the device under test 200 after being charged through the second power pin pair Power B'.

[0062] Optionally, the detection result of the second power pin pair Power B’ is read by the micro - control unit MCU of the device under test 200 from the power supply component of the device under test 200 after the first power pin pair Power A’ is disconnected for a preset time period. The duration of this preset time period is about 50 ms. Specifically, after about 50 ms of the preset time period, the electric quantity stored in the power supply component when the first power supply line 10020 charged the power supply component will be fully released. At this time, the electric quantity in the power supply component is the electric quantity charged by the second power supply line 10022 to the power supply component. This can avoid the influence of residual electric quantity on the subsequent test process. The duration of 50 ms is generally sufficient to allow the capacitors and resistors in the power supply component to discharge fully, ensuring the accuracy of test data. 50 ms is only an example, and the duration of the preset time period can be adjusted according to the actual situation.

[0063] In another embodiment according to the present disclosure, by keeping the path for supplying power to the first power pin pair Power A’ conducting, and then conducting the path for supplying power to the second power pin pair Power B’ at the interface 2002 of the device under test 200, and after the path for supplying power to the second power pin pair Power B’ at the interface 2002 of the device under test 200 is conducted, disconnecting the path for supplying power to the first power pin pair Power A’, it is achieved that as long as the second power pin pair Power B’ works normally, the micro - control unit MCU and the power supply component inside the device under test 200 can maintain the powered - on state, avoiding repeatedly restarting the micro - control unit MCU and the power supply component inside the device under test 200.

[0064] Similarly, in order to prevent the communication interruption between the device under test 200 and the interface detection device 100 caused by the disconnection of the data line during the whole test process, optionally, the system controller 1008 can also be configured to: control the first data - line switch pair 10044 and the second data - line switch pair 10046 to conduct the path for receiving data from or sending data to the second data pin pair USB B’ at the interface 2002 of the device under test 200 while maintaining the ability to receive data from or send data to the first data pin pair USB A’.

[0065] Alternatively, the system controller 1008 can also be configured to: after controlling the second data - line switch pair 10046 to conduct the path for receiving data from or sending data to the second data pin pair USB B’ at the interface 2002 of the device under test 200, control the first data - line switch pair 10044 to disconnect the path for receiving data from or sending data to the first data pin pair USB A’.

[0066] Although in the example of Figures 1 to 3 Power A’ and Power B’ are described as an example pair of power supply pins at the interface 2002 of the device under test 200, those skilled in the art can understand that the first pair of power supply pins and the second pair of power supply pins can refer to any pair of power supply pins at the interface 2002 of any device under test 200, for example, Power C’ or Power D’. At the same time, the first power supply line and the second power supply line can also refer to the power supply lines for supplying power to Power C’ or Power D’; the first power supply line switch and the second power supply line switch can also be used to control the conduction or cut-off of the power supply lines for supplying power to Power C’ or Power D’.

[0067] Next, reference is made to Figure 4 and Figure 5 to further illustrate the interface detection device 100 according to an embodiment of the present disclosure. Among them, Figure 4 shows another schematic diagram of the interface detection device 100 according to an embodiment of the present disclosure. Figure 5 shows a flowchart of the detection process executed by the interface detection device 100 according to an embodiment of the present disclosure.

[0068] As Figure 4 shown, the interface detection device 100 includes four power supply lines: a first power supply line 10020, a second power supply line 10022, a third power supply line 10028, and a fourth power supply line 10030. As described above, the conduction of the first power supply line 10020 is controlled by the first power supply line switch 10024; the conduction of the second power supply line 10022 is controlled by the second power supply line switch 10026. The conduction of the third power supply line 10028 is controlled by a third power supply line switch (not shown), and the conduction of the fourth power supply line 10030 is controlled by a fourth power supply line switch (not shown). Thus, each power supply line independently controls a power supply path.

[0069] In Figure 4 the power supply component 2004 and the micro control unit 2006 of the device under test 200 are further shown. The power supply component 2004 and the micro control unit 2006 are coupled.

[0070] The VBUS pins in the four pairs of power pins - Power A’, Power B’, Power C’, and Power D’ in the interface 2002 of the device under test 200 are respectively connected to the first power supply line 20020, the second power supply line 20022, the third power supply line 20024, and the fourth power supply line 20026. After the first power supply line 20020, the second power supply line 20022, the third power supply line 20024, and the fourth power supply line 20026 are connected in parallel, the charging current from the interface detection device 100 is transmitted to the power supply component 2004.

[0071] The interface 2002 of the device under test 200 includes two pairs of data pins: the first data pin pair USB A’ and the second data pin pair USB B’. The first data pin pair USB A’ includes Figure 3 pin A6’ and pin A7’ in, and are respectively connected to the data line D+ and the data line D- in the third data line pair 20060 of the device under test 200. The second data pin pair USB B’ includes Figure 3 pin B6’ and pin B7’ in, and are respectively connected to the data line D+ and the data line D- in the fourth data line pair 20062 of the device under test 200. The data line D+ in the third data line pair 20060 and the data line D+ in the fourth data line pair 20062 are connected in parallel. The data line D- in the third data line pair 20060 and the data line D- in the fourth data line pair 20062 are connected in parallel. Both the third data line pair 20060 and the fourth data line pair 20062 are coupled to the micro control unit 2006.

[0072] As Figure 5 shown, the process of the interface detection device 100 performing interface detection can be briefly described as follows: Conduct the path for supplying power to the first power pin pair Power A’ at the interface 2002 of the device under test 200, and receive the detection result for the first power pin pair Power A’ from the micro control unit 2006 of the device under test 200; Conduct the path for supplying power to the second power pin pair Power B’ (Power B’) at the interface 2002 of the device under test 200, and disconnect the path for supplying power to the first power pin pair Power A’; and receive the detection result for the second power pin pair Power B’ from the micro control unit 2006 of the device under test 200. Among them, when conducting the path for supplying power to the first power pin pair Power A’, and when conducting the path for supplying power to the second power pin pair Power B’, the micro control unit 2006 of the device under test 200 is in the powered-on state.

[0073] Specifically, the interface 2002 of the device under test 200 contacts the interface pin assembly 1006, and the entire test process starts.

[0074] In operation S502, the system controller 1008 is configured to turn on the first power supply line 10020 and the first data line pair 10040.

[0075] In operation S504, the system controller 1008 is configured to receive the detection result for the first power supply pin pair Power A'.

[0076] Specifically, assume that the first power supply pin pair Power A' can work properly. In operation S502, due to the turning on of the first power supply line 10020, the adapter 1012 supplies power to the power supply component 2004 of the device under test 200 via the first power supply line 10020 and the first power supply line 20020. The power supply component 2004 is charged and started to reach the powered-on state. At the same time, the microcontroller unit 2006 powered by the power supply component 2004 may also restart. In addition, the microcontroller unit 2006 may also be powered by the built-in power supply component (not shown) of the device under test 200 to restart or maintain the powered-on state.

[0077] The power supply component 2004 has a built-in power management circuit that monitors power information such as battery voltage, current, and remaining capacity in real time. This power information can be used as the detection result for the first power supply pin pair Power A'. The power supply component 2004 transmits the detection result corresponding to the first power supply pin pair Power A' to the microcontroller unit 2006. The microcontroller unit 2006 sends the detection result for the first power supply pin pair Power A' to the system controller 1008 via the third data line pair 20060 and the first data line pair 10040.

[0078] If the first power supply pin pair Power A' cannot work properly, neither operation S502 nor operation S504 can be executed. Therefore, if the system controller 1008 does not receive the detection result for the first power supply pin pair Power A' within the specified time, it outputs information about the failure of the interface 2002 of the device under test 200 via the output circuit 1010 and indicates that the reason for the failure of the interface 2002 is the failure of the first power supply pin pair Power A'.

[0079] In operation S506, the system controller 1008 is configured to first turn on the second power supply line 10022 and, after turning on the second power supply line 10022, disconnect the first power supply line 10020. At this time, the first data line pair 10040 remains turned on.

[0080] In operation S508, the system controller 1008 is configured to receive the detection result for the second power supply pin pair Power B'. At this time, the first data line pair 10040 remains turned on.

[0081] Specifically, assume that the second power pin pair Power B’ can work properly. In operation S506, since the second power line 10022 is first turned on, and after the second power line 10022 is turned on, the first power line 10020 is disconnected. During the whole process, the adapter 1012 can either supply power to the power supply component 2004 of the device under test 200 through the first power line 10020 and the first power supply line 20020, or supply power to the power supply component 2004 of the device under test 200 through the second power line 10022 and the second power supply line 20022. The power supply component 2004 always maintains the powered-on state. At the same time, the microcontroller unit 2006 powered by the power supply component 2004 can also maintain the powered-on state.

[0082] The built-in power management circuit of the power supply component 2004 can monitor power information such as battery voltage, current, and remaining capacity in real time. After the first power pin pair Power A’ is disconnected for a preset period of time, the power information stored in the power supply component 2004 can indicate the detection result of the second power pin pair Power B’. At this time, the microcontroller unit of the device under test 200 reads the detection result of the second power pin pair Power B’ from the power supply component 2004 of the device under test 200. Then, the microcontroller unit 2006 sends the detection result for the second power pin pair Power B’ to the system controller 1008 via the third data line pair 20060 and the first data line pair 10040.

[0083] If the second power pin pair Power B’ cannot work properly, operations S506 and S508 cannot be executed. Therefore, if the system controller 1008 does not receive the detection result for the second power pin pair Power B’ within the specified time, it outputs the information of the failure of the interface 2002 of the device under test 200 via the output circuit 1010, and indicates that the reason for the failure of the interface 2002 is the failure of the second power pin pair Power B’.

[0084] In operation S510, the system controller 1008 is configured to: first turn on the third power line 10028, and after the third power line 10028 is turned on, disconnect the second power line 10022. At this time, the first data line pair 10040 remains conductive.

[0085] In operation S512, the system controller 1008 is configured to: receive the detection result for the third power pin pair Power C’. At this time, the first data line pair 10040 remains conductive.

[0086] Specifically, assume that the third power supply pin pair Power C’ can work properly. In operation S510, since the third power supply line 10028 is first turned on, and after the third power supply line 10028 is turned on, the second power supply line 10022 is disconnected. The adapter 1012 can either supply power to the power supply component 2004 of the device under test 200 through the second power supply line 10022 and the second power supply line 20022, or supply power to the power supply component 2004 of the device under test 200 through the third power supply line 10028 and the third power supply line 20024 during the whole process. The power supply component 2004 always maintains the powered-on state. At the same time, the microcontroller unit 2006 powered by the power supply component 2004 can also maintain the powered-on state.

[0087] The built-in power management circuit of the power supply component 2004 can monitor power information such as battery voltage, current, and remaining capacity in real time. After the second power supply pin pair Power B’ is disconnected for a preset time period, the power information stored in the power supply component 2004 can indicate the detection result of the third power supply pin pair Power C’. At this time, the microcontroller unit of the device under test 200 reads the detection result of the third power supply pin pair Power C’ from the power supply component of the device under test 200. Then, the microcontroller unit 2006 sends the detection result for the third power supply pin pair Power C’ to the system controller 1008 via the third data line pair 20060 and the first data line pair 10040.

[0088] If the third power supply pin pair Power C’ cannot work properly, operations S510 and S512 cannot be executed. Therefore, if the system controller 1008 does not receive the detection result for the third power supply pin pair Power C’ within the specified time, it outputs the information of the failure of the interface 2002 of the device under test 200 via the output circuit 1010, and indicates that the reason for the failure of the interface 2002 is the failure of the third power supply pin pair Power C’.

[0089] In operation S514, the system controller 1008 is configured to: first turn on the fourth power supply line 10030, and after the fourth power supply line 10030 is turned on, disconnect the third power supply line 10028. The system controller 1008 is also configured to: first turn on the second data line pair 10042, and after the second data line pair 10042 is turned on, disconnect the first data line pair 10040.

[0090] In operation S516, the system controller 1008 is configured to: receive the detection result for the fourth power supply pin pair Power D’. At this time, the first data line pair 10040 is disconnected, while the second data line pair 10042 is turned on. This can ensure that as long as the second data line pair 10042 works properly, the communication between the device under test 200 and the interface detection device 100 is not interrupted.

[0091] Specifically, assume that the fourth power supply pin pair Power D’ can work properly. In operation S512, since the fourth power supply line 10030 is first turned on, and after the fourth power supply line 10030 is turned on, the third power supply line 10028 is disconnected. During the whole process, the adapter 1012 can either supply power to the power supply component 2004 of the device under test 200 through the third power supply line 10028 and the third power supply line 20024, or supply power to the power supply component 2004 of the device under test 200 through the fourth power supply line 10030 and the fourth power supply line 20026. The power supply component 2004 always maintains the powered-on state. At the same time, the microcontroller unit 2006 powered by the power supply component 2004 can also maintain the powered-on state.

[0092] The built-in power management circuit of the power supply component 2004 can monitor power information such as battery voltage, current, and remaining capacity in real time. After the third power supply pin pair Power C’ is disconnected for a preset period of time, the power information stored in the power supply component 2004 can indicate the detection result of the fourth power supply pin pair Power D’. At this time, the microcontroller unit of the device under test 200 reads the detection result of the fourth power supply pin pair Power D’ from the power supply component of the device under test 200. Then, the microcontroller unit 2006 sends the detection result for the fourth power supply pin pair Power D’ to the system controller 1008 via the fourth data line pair 20062 and the second data line pair 10042.

[0093] If the fourth power supply pin pair Power D’ cannot work properly, operations S514 and S516 cannot be executed. Therefore, if the system controller 1008 does not receive the detection result for the fourth power supply pin pair Power D’ within the specified time, it outputs the information of the fault of the interface 2002 of the device under test 200 via the output circuit 1010, and indicates that the reason for the fault of the interface 2002 is the fault of the fourth power supply pin pair Power D’.

[0094] Next, reference Figure 6 and Figure 7 will be used to further illustrate the interface detection device 100 according to an embodiment of the present disclosure. Among them, Figure 6 shows another schematic diagram of the interface detection device 100 according to an embodiment of the present disclosure. Figure 7 shows a flowchart of the detection process executed by the interface detection device 100 according to an embodiment of the present disclosure.

[0095] Figure 6 The shown interface detection device 100 is applicable to the test of the device under test 200 with a Type-C interface that complies with the PD (Power Delivery) transmission protocol.

[0096] Optionally, the device under test 200 supports the PD protocol. The device under test 200 further includes a PD chip 2008 and a data line switching component 2010. The PD chip 2008 integrates a PD protocol stack, which is used to control the working process of the entire PD system and interact with the controller of the PD adapter.

[0097] The PD chip 2008 is connected to the first configuration pin A5' in the interface 2002 through a third configuration line 20080, and is connected to the second configuration pin B5' in the interface 2002 through a fourth configuration line 20082. The PD chip 2008 can also be coupled to the data line switching component 2010. The working mechanism of the data line switching component 2010 is similar to that of the data line switching circuit 1004.

[0098] Optionally, the data line switching component 2010 includes: a third data line switch pair (not shown) coupled to the third data line pair 20060. The third data line switch pair is used to conduct the path for receiving any data from the first data pin pair USB A' at the interface 2002 of the device under test 200 or sending any data from the first data pin pair USB A'. Wherein, the data includes the first detection result and the second detection result mentioned above. At the same time, the data may also include a third detection result for the first configuration pin A5' or a fourth detection result for the second configuration pin B5'. Of course, the present disclosure is not limited thereto.

[0099] Similarly, the third data line pair 20060 is also composed of two parallel differential data lines D+ and D-, which are communication lines for the device under test 200 to transmit data through the interface 2002. Specifically, D+ and D- form a pair of differential data line pairs. When transmitting data "1", the voltage of the D+ line is higher than the fixed voltage difference of the D- line. When transmitting "0", the voltage of the D- line is higher than the D+ line. By detecting the voltage difference between D+ and D-, it is determined whether "1" or "0" is received. D+ and D- transmit various data between the interface detection device 100 and the device under test 200 in this differential manner. Optionally, the third data line switch pair includes two independent switches or switch circuits, which separately control and switch the connection states of the differential data line pairs D+ and D- in the third data line pair 20060. For example, one switch circuit is connected to the D+ line, and the other switch circuit is connected to the D- line, and the D+ and D- two data lines can be enabled or disabled arbitrarily in combination. When both switch circuits are turned on, D+ and D- are both connected, and data can be normally transmitted between the two lines in a differential manner; when either the D+ or D- line is disconnected, data cannot be effectively transmitted; when both lines are disconnected, the data path is blocked.

[0100] The data line switching component 2010 further includes: a fourth data line switch pair (not shown) coupled to the fourth data line pair 20062. The second data line switch pair is used to conduct the path for receiving any data from the second data pin pair USB B' at the interface 2002 of the device under test 200 or sending any data from the second data pin pair USB B'. The working principle of the fourth data line pair 20062 and the fourth data line switch pair is the same as that of the third data line pair 20060 and the third data line switch pair, and will not be elaborated here.

[0101] Specifically, Figure 6 Compared with the interface detection device 100 shown, Figure 4 the shown interface detection device 100 is increased with a configuration line switching circuit 1014. The configuration line switching circuit 1014 is coupled to the adapter 1012 and the system controller 1008. Of course, the configuration line switching circuit 1014 is also coupled to the interface pin assembly 1006.

[0102] Optionally, the configuration line switching circuit 1014 includes: a first configuration line switch (not shown) coupled to the first configuration line 10120. The first configuration line switch is used to conduct the path for transmitting configuration information to the first configuration pin A5' at the interface 2002 of the device under test 200. The configuration line switching circuit 1014 further includes: a second configuration line switch (not shown) coupled to the second configuration line 10122. The second configuration line switch is used to conduct the path for transmitting configuration information to the second configuration pin B5' at the interface 2002 of the device under test 200.

[0103] In addition, Figure 6 the adapter 1012 in the shown interface detection device 100 is a PD adapter. The PD adapter is built-in with a PD controller for implementing various functions of the PD protocol. The PD controller is a dedicated power management chip responsible for two-way communication with the device under test 200, negotiating the optimal charging voltage and current, and dynamically adjusting the power output. With the PD controller, the adapter 1012 can output voltages ranging from 5V to 20V according to different device requirements, providing a high-power supply voltage of up to 100W.

[0104] Optionally, the adapter 1012 may be configured to transmit first configuration information to the device under test 200 via a first configuration pin A5' at the interface 2002 of the device under test 200 under the control of a first configuration line switch, where the first configuration information indicates information related to the voltage value that the adapter can provide. Optionally, the adapter 1012 may also be configured to receive second configuration information from the device under test 200 via the first configuration pin A5' at the interface 2002 of the device under test 200 under the control of the first configuration line switch, where the second configuration information indicates the voltage value of the first power supply line 10020 determined by the device under test 200 or the voltage value of the second power supply line 10022 determined by the device under test 200. Of course, the second configuration information may also indicate the voltage value determined by the third power supply line 10028 or the fourth power supply line 10030 determined by the device under test 200. The present disclosure is not limited thereto.

[0105] Optionally, the interface pin assembly 1006 further includes: a first configuration test pin A5, coupled to the first configuration line 10120. Wherein, when the first configuration test pin A5 is connected to the first configuration pin A5' at the interface 2002 of the device under test 200, a path for transmitting configuration information to the first configuration pin A5' at the interface 2002 of the device under test 200 is enabled under the control of the first configuration line switch.

[0106] Optionally, the interface pin assembly 1006 further includes: a second configuration test pin B5, coupled to the second configuration line 10122. Wherein, when the second configuration test pin B5 is connected to the second configuration pin B5' at the interface 2002 of the device under test 200, a path for transmitting configuration information to the second configuration pin B5' at the interface 2002 of the device under test 200 is enabled under the control of the second configuration line switch.

[0107] Optionally, Figure 6 Before performing interface detection, the shown interface detection device 100 may also need to first detect whether the first configuration pin A5' or the second configuration pin B5' is faulty. This process can be briefly described as follows.

[0108] The system controller 1008 controls the first configuration line switch and the first data line switch pair 10044 to conduct. At this time, the PD chip 2008 sends a request to the first configuration test pin A5 through the third configuration line 20080 to obtain the capability data of the adapter 1012. This capability data includes various power configuration parameters supported by the adapter 1012, such as different combinations of bus voltages and currents. After receiving the request, the adapter 1012 returns its own capability data information (i.e., the first configuration information) to the PD chip 2008 through the first configuration line 10120 and the third configuration line 20080. After obtaining the capability data of the adapter, the PD chip 2008 will select a set of most suitable power configuration parameters according to the current system state and in combination with the parameter range supported by the adapter 1012, and send this request (i.e., the second configuration information) back to the adapter 1012. For example, the PD chip 2008 may request the adapter to output a standard setting of 15V / 3A or request the adapter 1012 to output the maximum power. After receiving the power configuration request from the PD chip 2008, the adapter 1012 will adjust the internal circuit as required, modify the voltage of the first power line 10020 to the corresponding set value, and also adjust the current limit. Once the configuration is ready, the adapter 1012 will return an acknowledgment response to the PD chip 2008, and then the energy transfer between the two can proceed smoothly according to the new specifications.

[0109] If the above negotiation process can be completed, it indicates that the first configuration pin A5' is working properly. At this time, the microcontroller unit 2006 will read various power configuration data stored in the PD chip as the detection result for the first configuration pin A5'. The microcontroller unit 2006 will send the detection result for the first configuration pin A5' to the system controller 1008 via the third data line pair 20060 and the first data line pair 10040.

[0110] Next, the system controller 1008 controls the first configuration line switch and the second configuration line switch to conduct, so as to conduct the path that can receive configuration information from the second configuration pin B5' at the interface 2002 of the device under test 200 or send configuration information to the second configuration pin B5' while maintaining the ability to receive configuration information from the first configuration pin A5' or send configuration information to the first configuration pin A5'.

[0111] After the system controller 1008 controls the second configuration line switch to conduct the path that can receive configuration information from the second configuration pin B5' at the interface 2002 of the device under test 200 or send configuration information to the second configuration pin B5', it controls the first configuration line switch to disconnect the path that can receive configuration information from the first configuration pin A5' or send configuration information to the first configuration pin A5'.

[0112] After the system controller 1008 controls the second configuration line switch to conduct the path that can receive configuration information from the second configuration pin B5' at the interface of the device under test or send configuration information to the second configuration pin B5', it controls the first configuration line switch to disconnect the path that can receive configuration information from the first configuration pin A5' or send configuration information to the first configuration pin A5'. At this time, the detection result of B5 of the second configuration pin can be determined by a similar process.

[0113] The specific test process is as Figure 7 shown. Specifically, the interface 22002 of the device under test 200 contacts the interface pin assembly 1006, and the entire test process starts.

[0114] In operation S702, the system controller 1008 is configured to conduct the first power supply line 10020, the first data line pair 10040, and the first configuration line 10120.

[0115] In operation S704, the system controller 1008 is configured to receive at least one of the detection result for the first power pin pair Power A' and the detection result for the first configuration pin A5'.

[0116] Specifically, assume that the first configuration pin A5' can work properly. In operation S702, due to the conduction of the first configuration line 10120 and the first data line pair 10040, the adapter 1012 can negotiate configuration information with the PD chip 2008. This process has been described in detail above, and the present disclosure will not repeat it here. If the first configuration pin A5' cannot work properly, the PD chip 2008 cannot be configured properly, and the power supply component 2004 cannot be charged either. Therefore, if the system controller 1008 does not receive the detection result for the first configuration pin A5' within the specified time, it outputs information about the failure of the interface 2002 of the device under test 200 via the output circuit 1010, and indicates that the reason for the failure of the interface 2002 is the failure of the first configuration pin A5'.

[0117] Assume that the first power pin pair Power A' can work properly. In operation S702, due to the conduction of the first power supply line 10020, the adapter 1012 supplies power to the power supply component 2004 of the device under test 200 via the first power supply line 10020 and the first power supply line 20020. The power supply component 2004 is charged and started to reach the powered-on state. At the same time, the microcontroller unit 2006 powered by the power supply component 2004 may also restart. In addition, the microcontroller unit 2006 may also be powered by the built-in power supply component (not shown) of the device under test 200 to restart or maintain the powered-on state.

[0118] The built-in power management circuit of the power supply component 2004 monitors the battery voltage, current, remaining capacity and other power information in real time. These power information can be used as the detection results of the first power pin pair Power A’. The power supply component 2004 transmits the detection results corresponding to the first power pin pair Power A’ to the micro-control unit 2006. The micro-control unit 2006 sends the detection results for the first power pin pair Power A’ to the system controller 1008 via the third data line pair 20060 and the first data line pair 10040.

[0119] In addition, if the first power pin pair Power A’ fails to work properly, neither operation S702 nor operation S704 can be executed. Therefore, if the system controller 1008 does not receive the detection results for the first power pin pair Power A’ within the specified time, it outputs the information of the interface 2002 failure of the device under test 200 via the output circuit 1010, and indicates that the reason for the interface 2002 failure is the failure of the first power pin pair Power A’.

[0120] In operation S706, the system controller 1008 is configured to: first turn on the second power line 10022, and after turning on the second power line 10022, disconnect the first power line 10020. At this time, the first data line pair 10040 remains conductive.

[0121] In operation S708, the system controller 1008 is configured to: receive the detection results for the first power pin pair Power B’. At this time, the first data line pair 10040 remains conductive.

[0122] Specifically, assume that the second power pin pair Power B’ can work properly. In operation S706, since the second power line 10022 is first turned on and the first power line 10020 is disconnected after turning on the second power line 10022, the adapter 1012 can either supply power to the power supply component 2004 of the device under test 200 through the first power line 10020 and the first power supply line 20020 during the whole process, or supply power to the power supply component 2004 of the device under test 200 through the second power line 10022 and the second power supply line 20022. The power supply component 2004 always maintains the powered-on state. At the same time, the micro-control unit 2006 powered by the power supply component 2004 can also maintain the powered-on state.

[0123] The built-in power management circuit of the power supply component 2004 can monitor power information such as battery voltage, current, and remaining capacity in real time. After the first power pin pair Power A’ is disconnected for a preset period of time, the power information stored in the power supply component 2004 can indicate the detection result of the second power pin pair Power B’. At this time, the micro control unit of the device under test 200 reads the detection result of the second power pin pair Power B’ from the power supply component of the device under test 200. Then, the micro control unit 2006 sends the detection result for the second power pin pair Power B’ to the system controller 1008 via the third data line pair 20060 and the first data line pair 10040.

[0124] If the second power pin pair Power B’ cannot work properly, operations S706 and S708 cannot be executed. Therefore, if the system controller 1008 does not receive the detection result for the second power pin pair Power B’ within the specified time, it outputs information about the failure of the interface 2002 of the device under test 200 via the output circuit 1010 and indicates that the reason for the failure of the interface 2002 is the failure of the second power pin pair Power B’.

[0125] In operation S710, the system controller 1008 is configured to: first turn on the third power supply line 10028, and after turning on the third power supply line 10028, disconnect the second power supply line 10022. At this time, the first data line pair 10040 remains conductive.

[0126] In operation S712, the system controller 1008 is configured to: receive the detection result for the third power pin pair Power C’. At this time, the first data line pair 10040 remains conductive.

[0127] Specifically, assume that the third power pin pair Power C’ can work properly. In operation S706, since the third power supply line 10028 is first turned on and the second power supply line 10022 is disconnected after turning on the third power supply line 10028, the adapter 1012 can either supply power to the power supply component 2004 of the device under test 200 through the second power supply line 10022 and the second power supply line 20022 during the whole process, or supply power to the power supply component 2004 of the device under test 200 through the third power supply line 10028 and the third power supply line 20024. The power supply component 2004 always maintains the powered-on state. At the same time, the micro control unit 2006 powered by the power supply component 2004 can also maintain the powered-on state.

[0128] The built-in power management circuit of the power supply component 2004 can monitor power information such as battery voltage, current, and remaining capacity in real time. After the second power supply pin pair Power B’ is disconnected for a preset time period, the power information stored in the power supply component 2004 can indicate the detection result of the third power supply pin pair Power C’. At this time, the micro-control unit of the device under test 200 reads the detection result of the third power supply pin pair Power C’ from the power supply component of the device under test 200. Then, the micro-control unit 2006 sends the detection result for the third power supply pin pair Power C’ to the system controller 1008 via the third data line pair 20060 and the first data line pair 10040.

[0129] If the third power supply pin pair Power C’ cannot work properly, operations S710 and S712 cannot be executed. Therefore, if the system controller 1008 does not receive the detection result for the third power supply pin pair Power C’ within the specified time, it outputs information about the failure of the interface 2002 of the device under test 200 via the output circuit 1010 and indicates that the reason for the failure of the interface 2002 is the failure of the third power supply pin pair Power C’.

[0130] In operation S714, the system controller 1008 is configured to: first conduct the fourth power supply line 10030, and after conducting the fourth power supply line 10030, disconnect the third power supply line 10028. The system controller 1008 is also configured to: first conduct the second data line pair 10042, and after conducting the second data line pair 10042, disconnect the first data line pair 10040. This can ensure that as long as the second data line pair 10042 works properly, the communication between the device under test 200 and the interface detection device 100 is not interrupted. The system controller 1008 is also configured to: first conduct the second configuration line 10122, and after conducting the second configuration line 10122, disconnect the first configuration line 10120. This can ensure that as long as the second configuration line 10122 works properly, the configuration information between the device under test 200 and the interface detection device 100 will not change, thus affecting the test of the device under test 200.

[0131] In operation S716, the system controller 1008 is configured to: receive the detection result for the fourth power supply pin pair Power D’ or the detection result for the second configuration pin B5’. At this time, the first data line pair 10040 is disconnected, while the second data line pair 10042 is conducted.

[0132] Specifically, assume that the fourth power supply pin pair Power D’ can work properly. In operation S712, since the fourth power supply line 10030 is first turned on, and after the fourth power supply line 10030 is turned on, the third power supply line 10028 is disconnected. During the whole process, the adapter 1012 can either supply power to the power supply component 2004 of the device under test 200 through the third power supply line 10028 and the third power supply line 20024, or supply power to the power supply component 2004 of the device under test 200 through the fourth power supply line 10030 and the fourth power supply line USB A’. The power supply component 2004 always maintains the powered-on state. At the same time, the microcontroller unit 2006 powered by the power supply component 2004 can also maintain the powered-on state.

[0133] The built-in power management circuit of the power supply component 2004 can monitor power information such as battery voltage, current, and remaining capacity in real time. After the third power supply pin pair Power C’ is disconnected for a preset period of time, the power information stored in the power supply component 2004 can indicate the detection result of the fourth power supply pin pair Power D’. At this time, the microcontroller unit of the device under test 200 reads the detection result of the fourth power supply pin pair Power D’ from the power supply component of the device under test 200. Then, the microcontroller unit 2006 sends the detection result for the fourth power supply pin pair Power D’ to the system controller 1008 via the fourth data line pair 20062 and the second data line pair 10042.

[0134] If the fourth power supply pin pair Power D’ cannot work properly, operations S714 and S716 cannot be executed. Therefore, if the system controller 1008 does not receive the detection result for the fourth power supply pin pair Power D’ within the specified time, it outputs the information of the failure of the interface 2002 of the device under test 200 via the output circuit 1010, and indicates that the reason for the failure of the interface 2002 is the failure of the fourth power supply pin pair Power D’.

[0135] Assume that the second configuration pin B5' can work properly. In operation S714, since the second configuration line 10122 is first conducted, and after the second configuration line 10122 is conducted, the first configuration line 10120 is disconnected, the adapter 1012 can either communicate with the PD chip 2008 through the first configuration line 10120 or communicate with the PD chip 2008 through the second configuration line 10122 throughout the process. Therefore, the voltage transient provided by the adapter 1012 due to the inability to communicate will not cause an error in the detection result. If the second configuration pin B5' cannot work properly, then the PD chip 2008 will malfunction. At this time, the micro control unit of the device under test 200 reads abnormal data from the PD chip 2008 and sends the abnormal data to the system controller 1008 as the detection result for the second configuration pin B5'.

[0136] Figure 8 FIG. shows a flowchart of an interface detection method 80 according to an embodiment of the present disclosure. The interface detection method 80 is executed by an interface detection device 100. Figure 9 FIG. shows a flowchart of an interface detection method 90 according to an embodiment of the present disclosure. The interface detection method 90 is executed by a device under test 200.

[0137] As Figure 8 shown, the interface detection method 80 includes operations S802 to S806.

[0138] In operation S802, the interface detection device 100 conducts the path for supplying power to the first power pin pair Power A' at the interface 2002 of the device under test 200, and receives the detection result for the first power pin pair Power A' from the micro control unit 2006 of the device under test 200.

[0139] In operation S804, the interface detection device 100 conducts the path for supplying power to the second power pin pair Power B' at the interface 2002 of the device under test 200 and disconnects the path for supplying power to the first power pin pair Power A'.

[0140] In operation S806, the interface detection device 100 receives the detection result for the second power pin pair Power B' from the micro control unit 2006 of the device under test 200.

[0141] As Figure 9 shown, the interface detection method 90 includes operations S902 to S910.

[0142] In operation S902, the device under test 200 conducts the path for supplying power from the first power pin pair PowerA' at the interface of the device under test 200 to the power supply component 2004 of the device under test 200.

[0143] In operation S904, with the path from the first power pin pair Power A' to the power supply component 2004 of the device under test 200 kept conducting, the path for supplying power from the second power pin pair Power B' at the interface of the device under test 200 to the power supply component 2004 of the device under test 200 is conducted.

[0144] In operation S906, after the path for supplying power from the second power pin pair Power B' at the interface of the device under test 200 to the power supply component 2004 of the device under test 200 is conducted, the path for supplying power from the first power pin pair Power A' at the interface 2002 of the device under test 200 to the power supply component 2004 of the device under test 200 is disconnected.

[0145] In operation S908, in response to a preset time period having elapsed since the moment when the first power pin pair Power A' was disconnected, the micro control unit 2006 of the device under test 200 reads the status information of the power supply component 2004 of the device under test 200 after being charged via the second power pin pair Power B', and the status information is used as the detection result of the second power pin pair Power B'.

[0146] In operation S910, the device under test 200 sends the detection result of the second power pin pair Power B'.

[0147] Details in Method 80 and Method 90 have been described in detail with reference to the attached Figures 1 - 7 and are not repeated herein in the present disclosure.

[0148] It should be noted that the flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code that contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, as well as combinations of blocks in the block diagram and / or flowchart, may be implemented by a dedicated hardware-based system for performing the specified functions or operations, or may be implemented by a combination of dedicated hardware and computer instructions.

[0149] In general, the various example embodiments of the present disclosure can be implemented in hardware or special-purpose circuits, software, firmware, logic, or any combination thereof. Some aspects can be implemented in hardware, while other aspects can be implemented in firmware or software that can be executed by a controller, microprocessor, or other computing device. When aspects of the embodiments of the present disclosure are illustrated or described as block diagrams, flowcharts, or using some other graphical representation, it will be understood that the blocks, devices, systems, techniques, or methods described herein can be implemented as non-limiting examples in hardware, software, firmware, special-purpose circuits or logic, general hardware or a controller or other computing device, or some combination thereof.

[0150] The example embodiments of the present disclosure described in detail above are merely illustrative and not restrictive. Those skilled in the art should understand that various modifications and combinations can be made to these embodiments or their features without departing from the principles and spirit of the present disclosure, and such modifications should fall within the scope of the present disclosure.

Claims

1. An interface detection device, characterized in that: The interface detection device comprises: A power line switching circuit, comprising: A first power line switch coupled to the first power line, the first power line switch being used to conduct a path for supplying power to a first power pin pair at an interface of the device under test; a second power line switch coupled to the second power line, the second power line switch being used to conduct a path for supplying power to a second power pin pair at the interface of the device under test; A data line switching circuit, comprising: a first data line switch pair coupled to the first data line pair, the first data line switch pair being used to conduct a path for receiving a first detection result from a first data pin pair at an interface of the device under test, wherein the first detection result includes at least one of a detection result for the first power pin pair and a detection result for the second power pin pair; a second data line switch pair coupled to the second data line pair, the second data line switch pair being used to conduct a path for receiving a second detection result from a second data pin pair at the interface of the device under test, wherein the second detection result includes at least one of a detection result for the first power pin pair and a detection result for the second power pin pair; and A system controller, the system controller is coupled to the power line switching circuit and the data line switching circuit, wherein the system controller is configured to: The first power line switch, the second power line switch, the first data line switch pair, and the second data line switch pair are controlled to be turned on and off.

2. The interface detection device according to claim 1, characterized in that: The interface detection device also includes: An adapter coupled to the power line switching circuit, wherein the adapter is configured to provide power to the first power line and the second power line.

3. The interface detection device according to claim 1, characterized in that: The interface detection device also includes: An output circuit is coupled to the system controller, wherein the output circuit is configured to output at least one of the first detection result and the second detection result.

4. The interface detection device according to claim 2, characterized in that: The detection result of the first power pin pair is read by the microcontroller unit of the device under test from the power component of the device under test, and is used to indicate the status information of the power component of the device under test after being charged by the first power pin pair; and The detection result of the second power pin pair is read by the microcontroller unit of the device under test from the power component of the device under test, and is used to indicate the status information of the power component of the device under test after being charged by the second power pin pair.

5. The interface detection device according to claim 4, characterized in that: The interface detection device further includes a configuration line switching circuit, which is configured to be coupled to the adapter and the system controller, wherein the configuration line switching circuit includes: a first configuration line switch coupled to the first configuration line, the first configuration line switch being configured to conduct a path for transmitting configuration information to a first configuration pin at an interface of the device under test; and A second configuration line switch coupled to the second configuration line, the second configuration line switch is used to conduct a path for transmitting configuration information to a second configuration pin at the interface of the device under test.

6. The interface detection device according to claim 1, characterized in that: The first power pin pair and the second power pin pair each include a power supply pin and a ground pin; and The first power pin pair and the second power pin pair are connected in parallel in the interface of the device under test.

7. The interface detection device according to claim 5, characterized in that: The interface detection device further includes an interface pin assembly, and the interface pin assembly includes: a first power test pin pair, wherein a power supply pin of the first power test pin pair is coupled to a first power line, wherein when the first power test pin pair is connected to the first power pin pair at the interface of the device under test, a path for supplying power to the first power pin pair at the interface of the device under test is opened through control of a switch of the first power line; and A second power supply test pin pair, wherein the power supply pin of the second power supply test pin pair is coupled to a second power supply line, wherein when the second power supply test pin pair is connected to the second power supply pin pair at the interface of the device under test, a path for supplying power to the second power supply pin pair at the interface of the device under test is opened through the control of the second power supply line switch.

8. The interface detection device according to claim 7, characterized in that: The interface pin assembly also includes: a first data test pin pair coupled to the first data line pair, wherein, when the first data test pin pair is connected to the first data pin pair at the interface of the device under test, the first detection result is received from the first data pin pair at the interface of the device under test via control of the first data line switch pair; and A second data test pin pair coupled to a second data line pair, wherein when the second data test pin pair is connected to a second data pin pair at an interface of the device under test, the second detection result is received from the second data pin pair at the interface of the device under test via control of the second data line switch pair.

9. The interface detection device according to claim 7, characterized in that: The interface pin assembly also includes: a first configuration test pin coupled to the first configuration line, wherein, when the first configuration test pin is connected to the first configuration pin at the interface of the device under test, a path for transmitting configuration information to the first configuration pin at the interface of the device under test is opened through control of a switch of the first configuration line; and A second configuration test pin coupled to the second configuration line, wherein when the second configuration test pin is connected to the second configuration pin at the interface of the device under test, a path for transmitting configuration information to the second configuration pin at the interface of the device under test is opened through control of the second configuration line switch.

10. The interface detection device according to claim 7, characterized in that: The type of the interface pin assembly is Type-C.

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