Stage circuit

Abstract

A stage circuit includes: an output unit connected to a first power input terminal and a second power input terminal, the output unit outputting an enabled output signal to a first output terminal and outputting an enabled carry signal to a second output terminal; a first driver connected to the first power input terminal, the second power input terminal, the clock input terminal, and the second input terminal; and a second driver connected to the first input terminal, the second input terminal, the first power input terminal, and the clock input terminal, the second driver controlling a voltage of the first node. The second driver includes: a first transistor connected between a first node and a clock input terminal, the first transistor including a gate electrode connected to a control node; and a control transistor and a first capacitor connected in series between the control node and the clock input terminal.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0135438, filed on October 11, 2023, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] Aspects of some embodiments of the present disclosure generally relate to a stage circuit and a display device including the stage circuit. Background art

[0004] With the development of the information society, consumer demands for display devices for displaying images have increased in various forms. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigation systems, and smart televisions.

[0005] A display device uses pixels to display an image. The display device may include an emission driver for driving the pixels and a plurality of scan drivers.

[0006] The above information disclosed in this background art section is only for enhancing the understanding of the background art, and thus the information discussed in this background art section does not necessarily constitute the prior art. Summary of the utility model

[0007] Aspects of some embodiments include a stage circuit that can minimize or reduce power consumption and a display device including the stage circuit.

[0008] According to some embodiments of the present disclosure, there is provided a stage circuit including: an output unit connected to a first power input terminal to which a first power supply is input and a second power input terminal to which a second power supply is input, the output unit outputting an enabled output signal to a first output terminal and an enabled carry signal to a second output terminal corresponding to the voltages of a first node and a second node; a first driver connected to the first power input terminal, the second power input terminal, a clock input terminal to which a clock signal is input, and a second input terminal to which a previous enabled output signal is input, the first driver controlling the voltages of the first node and the second node; and a second driver connected to a first input terminal, a second input terminal, the first power input terminal, and the clock input terminal to which a previous enabled carry signal is input, the second driver controlling the voltage of the first node, wherein the second driver includes: a first transistor connected between the first node and the clock input terminal, the first transistor including a gate electrode connected to a control node; and a control transistor and a first capacitor connected in series between the control node and the clock input terminal, the control transistor including a gate electrode connected to the first input terminal.

[0009] According to some embodiments, the enabled output signal can be set to a high level, and the enabled carry signal is set to a low level.

[0010] According to some embodiments, a control transistor can be connected between a control node and a first capacitor.

[0011] According to some embodiments, when the inhibited carry signal, which is a high-level voltage, is input to the first input terminal, the control transistor can be set to an off state.

[0012] According to some embodiments, a control transistor can be connected between the first capacitor and the clock input terminal.

[0013] According to some embodiments, when the inhibited carry signal, which is a high-level voltage, is input to the first input terminal, the control transistor can be set to an off state.

[0014] According to some embodiments, the second driver can further include: a second capacitor connected between the first power input terminal and the first node; and a second transistor connected between the first power input terminal and the control node, the second transistor including a gate electrode connected to the second input terminal.

[0015] According to some embodiments, the output unit can include: a first output transistor connected between the first power input terminal and the first output terminal, the first output transistor including a gate electrode connected to the first node; a second output transistor connected between the first output terminal and the second power input terminal, the second output transistor including a gate electrode connected to the second node; and a capacitor connected between the first output terminal and the second node. According to some embodiments, the second output terminal can be connected to the first node.

[0016] According to some embodiments, the first driver can include: a third transistor connected between the first power input terminal and the first node, the third transistor including a gate electrode connected to the third node; a fourth transistor connected between the third node and the second node, the fourth transistor including a gate electrode connected to the second power input terminal; and a fifth transistor connected between the second input terminal and the third node, the fifth transistor including a gate electrode connected to the clock input terminal.

[0017] According to some embodiments, the voltage of the first power supply can be set to a high-level voltage, and the voltage of the second power supply can be set to a low-level voltage.

[0018] According to some embodiments of the present disclosure, a stage circuit includes: an output unit configured to supply an output signal to a first output terminal and a carry signal to a second output terminal corresponding to voltages of a first node and a second node; a first driver configured to control voltages of the first node and the second node corresponding to a previous output signal and a clock signal; and a second driver configured to control the voltage of the first node corresponding to the previous output signal, the clock signal, and a previous carry signal, wherein the second driver includes: a first transistor connected between the first node and a clock input terminal to which the clock signal is input, the first transistor including a gate electrode connected to a control node; and a first capacitor and a control transistor connected in series between the control node and the clock input terminal, and wherein the control transistor is turned on when the previous carry signal is input to connect a first electrode of the first capacitor to the clock input terminal and a second electrode of the first capacitor to the control node, and is turned off when the previous carry signal is not input to set the first capacitor in a floating state.

[0019] According to some embodiments, the control transistor may be connected between the first capacitor and the control node.

[0020] According to some embodiments, the control transistor may be connected between the first capacitor and the clock input terminal.

[0021] According to some embodiments of the present disclosure, a display device is provided, including: a gate driver including a plurality of stage circuits for supplying a scan signal having a high level or an emission control signal having a high level, wherein at least one of the stage circuits includes: an output unit connected to a first power input terminal to which a first power supply is input and a second power input terminal to which a second power supply is input, the output unit outputting an enabled output signal to a first output terminal and an enabled carry signal to a second output terminal corresponding to voltages of a first node and a second node; a first driver connected to the first power input terminal, the second power input terminal, a clock input terminal to which a clock signal is input, and a second input terminal to which a previous enabled output signal is input, the first driver controlling voltages of the first node and the second node; and a second driver connected to a first input terminal, a second input terminal, the first power input terminal, and the clock input terminal to which a previous enabled carry signal is input, the second driver controlling the voltage of the first node, wherein the second driver includes: a first transistor connected between the first node and the clock input terminal, the first transistor including a gate electrode connected to a control node; and a control transistor and a first capacitor connected in series between the control node and the clock input terminal, the control transistor including a gate electrode connected to the first input terminal.

[0022] According to some embodiments, the enabled output signal may be set to a high level, and the enabled carry signal may be set to a low level. According to some embodiments, the enabled output signal may be a scan signal or a transmit control signal.

[0023] According to some embodiments, the control transistor may be connected between the control node and the first capacitor and may be set to an off state when the inhibited carry signal, which is a high-level voltage, is input to the first input terminal.

[0024] According to some embodiments, the control transistor may be connected between the first capacitor and the clock input terminal and may be set to an off state when the inhibited carry signal, which is a high-level voltage, is input to the first input terminal.

[0025] According to some embodiments, the second driver may further include: a second capacitor connected between the first power input terminal and the first node; and a second transistor connected between the first power input terminal and the control node, the second transistor including a gate electrode connected to the second input terminal.

[0026] According to some embodiments, the output unit may include: a first output transistor connected between the first power input terminal and the first output terminal, the first output transistor including a gate electrode connected to the first node; a second output transistor connected between the first output terminal and the second power input terminal, the second output transistor including a gate electrode connected to the second node; and a capacitor connected between the first output terminal and the second node. According to some embodiments, the second output terminal may be connected to the first node.

[0027] According to some embodiments, the first driver may include: a third transistor connected between the first power input terminal and the first node, the third transistor including a gate electrode connected to the third node; a fourth transistor connected between the third node and the second node, the fourth transistor including a gate electrode connected to the second power input terminal; and a fifth transistor connected between the second input terminal and the third node, the fifth transistor including a gate electrode connected to the clock input terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a diagram illustrating a display device according to some embodiments of the present disclosure.

[0029] Figure 2 is a diagram illustrating Figure 1 aspects of the scan driver and the transmit driver shown in

[0030] Figure 3 is a diagram illustrating Figure 1 aspects of the pixel shown in

[0031] Figure 4 is a waveform diagram illustrating aspects of a driving method of pixels shown in Figure 3 .

[0032] Figure 5 is a diagram illustrating a stage circuit according to some embodiments of the present disclosure.

[0033] Figure 6 is a diagram illustrating a gate driver according to some embodiments of the present disclosure.

[0034] Figure 7 is a diagram illustrating a stage circuit according to some embodiments of the present disclosure.

[0035] Figure 8 is a waveform diagram illustrating aspects of a driving method of a stage circuit shown in Figure 7 according to some embodiments.

[0036] Figure 9 Illustrates Figure 7 charging / discharging of a first capacitor in a stage circuit shown in

[0037] Figure 10 is a circuit diagram of a stage circuit according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0038] Aspects of some embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art.

[0039] In the drawings, sizes may be exaggerated for ease of illustration. It will be understood that when an element is referred to as being “between” two elements, the element may be the only element between the two elements, or there may be one or more intervening elements. The same reference numerals refer to the same elements throughout.

[0040] Aspects of some embodiments will now be described in more detail below with reference to the accompanying drawings so that those skilled in the art can easily practice the present disclosure. Embodiments according to the present disclosure can be implemented in various different forms and are not limited to the disclosed embodiments described in this specification.

[0041] Parts not relevant to the description will be omitted to clearly describe the present disclosure, and throughout the specification, the same or similar components will be denoted by the same reference numerals. Accordingly, the same reference numerals may be used to identify the same or similar elements in different drawings.

[0042] In addition, for better understanding and ease of description, the size and thickness of each component illustrated in the drawings are arbitrarily shown, but the present disclosure is not limited thereto. For clarity of presentation, the thicknesses of several parts and regions are exaggerated.

[0043] In the description, the expression "equal" may mean "substantially equal". That is, this may mean equal to the extent that can be understood by those skilled in the art. Other expressions may be those in which "substantially" is omitted.

[0044] Some embodiments are described from the perspective of functional blocks, units, and / or modules and illustrated in the drawings. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, or other electronic circuits. This can be formed by using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where the blocks, units, and / or modules are implemented by a microprocessor or other similar hardware, the blocks, units, and / or modules are programmed and controlled by using software to perform the various functions discussed in the present disclosure, and can optionally be driven by firmware and / or software. Additionally, each block, unit, and / or module can be implemented by dedicated hardware, or by a combination of dedicated hardware that performs some functions of the block, unit, and / or module and a processor (e.g., one or more programmed microprocessors and associated circuits) that performs other functions of the block, unit, and / or module. In some embodiments, the blocks, units, and / or modules can be physically divided into two or more discrete blocks, two or more units, and / or two or more modules without departing from the scope of the present disclosure. Furthermore, in some embodiments, the blocks, units, and / or modules can be physically combined into more complex blocks, more complex units, and / or more complex modules without departing from the scope of the present disclosure.

[0045] The term "connected" between two components can include both electrical connection and physical connection, but the present disclosure is not necessarily limited thereto. For example, the term "connected" used based on a circuit diagram may mean an electrical connection, and the "connected" used based on a cross-sectional view or a plan view may mean a physical connection.

[0046] It will be understood that although terms such as "first", "second", etc. may be used in the text to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, the "first" element discussed below may also be referred to as the "second" element without departing from the teachings of the present disclosure.

[0047] Meanwhile, the present disclosure is not limited to the embodiments disclosed below and can be implemented in various forms. Each of the embodiments disclosed below can be embodied independently, or combined with at least another embodiment before being embodied.

[0048] Figure 1 FIG. is a diagram illustrating a display device according to some embodiments of the present disclosure. Figure 2 is a diagram illustrating aspects of Figure 1 the scan driver and the emission driver shown in

[0049] Referring to Figure 1 , a display device 100 according to some embodiments of the present disclosure may include a pixel unit 110 (or panel), a timing controller 120, a scan driver 130, a data driver 140, an emission driver 150, and a power supply 160. The above components may be implemented as separate integrated circuits, and at least two of the above components may be integrated into one integrated circuit. The scan driver 130 and the emission driver 150 may be formed to be included in the pixel unit 110.

[0050] The pixel unit 110 may include pixels PX connected to a first scan line SL11, SL12, …, and SL1n, a second scan line SL21, SL22, …, and SL2n, a third scan line SL31, SL32, …, and SL3n, a fourth scan line SL41, SL42, …, and SL4n, data lines DL1, DL2, …, and DLm, emission control lines EL1, EL2, …, and ELo, and power lines PL1, PL2, PL3, and PL4 (n, m, and o are natural numbers other than zero).

[0051] According to some embodiments, a pixel PXij located on the i-th horizontal line (or pixel row) and the j-th vertical line (or pixel column) (see Figure 3 ) may be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th third scan line SL3i, the i-th fourth scan line SL4i, the k-th emission control line ELk, and the j-th data line DLj (i is an integer less than or equal to n, j is an integer less than or equal to m, and k is an integer less than or equal to o). Here, k is a number equal to or less than i. In an example, when each of the emission control lines EL1 to ELo is connected to a pixel PX located on one horizontal line, k may be a number equal to i. According to some embodiments, when each of the emission control lines EL1 to ELo is connected to pixels PX located on at least two horizontal lines, k may be a number less than i.

[0052] When the first scan signal is supplied to the first scan lines SL11 to SL1n, the pixels PX can be selected in units or groups of horizontal lines (e.g., the pixels PX connected to the same scan line can be classified as one horizontal line (or one pixel row)). The pixels PX selected by the first scan signal can be supplied with data signals from any one of the data lines (DL1 to DLm) connected thereto. The pixels PX supplied with the data signals can generate light having a luminance corresponding to the voltage of the data signals (e.g., set luminance or predetermined luminance).

[0053] The scan driver 130 can receive a scan driving signal SCS from the timing controller 120. At least one scan start signal and a clock signal necessary for driving the scan driver 130 can be included in the scan driving signal SCS. The scan driver 130 can generate a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal while shifting the scan start signal corresponding to the clock signal.

[0054] For this purpose, the scan driver 130 can include a first scan driver 132, a second scan driver 134, a third scan driver 136, and a fourth scan driver 138, as Figure 2 shown.

[0055] The first scan driver 132 can receive a first scan start signal FLM1 and generate a first scan signal while shifting the first scan start signal FLM1 corresponding to the clock signal. The first scan driver 132 can sequentially supply the first scan signal to the first scan lines SL11 to SL1n.

[0056] The second scan driver 134 can receive a second scan start signal FLM2 and generate a second scan signal while shifting the second scan start signal FLM2 corresponding to the clock signal. The second scan driver 134 can sequentially supply the second scan signal to the second scan lines SL21 to SL2n.

[0057] The third scan driver 136 can receive a third scan start signal FLM3 and generate a third scan signal while shifting the third scan start signal FLM3 corresponding to the clock signal. The third scan driver 136 can sequentially supply the third scan signal to the third scan lines SL31 to SL3n.

[0058] The fourth scan driver 138 can receive a fourth scan start signal FLM4 and generate a fourth scan signal while shifting the fourth scan start signal FLM4 corresponding to the clock signal. The fourth scan driver 138 can sequentially supply the fourth scan signal to the fourth scan lines SL41 to SL4n.

[0059] InFigure 2 In Figure 2 , each of the illustrated scan drivers 132, 134, 136, and 138 receives a scan start signal (any one of FLM1, FLM2, FLM3, and FLM4). However, embodiments according to the present disclosure are not limited thereto. In an example, at least one of the scan drivers 132, 134, 136, or 138 may receive two or more scan start signals.

[0060] The first scan signal, the second scan signal, the third scan signal, and the fourth scan signal may be set to a gate-on voltage such that the transistors included in the pixel PX may be turned on. In an example, a scan signal having a low level may be supplied to a P-type transistor, and a scan signal having a high level may be supplied to an N-type transistor. The transistors supplied with the first scan signal, the second scan signal, the third scan signal, or the fourth scan signal may be turned on corresponding to the first scan signal, the second scan signal, the third scan signal, or the fourth scan signal.

[0061] After that, supplying the first scan signal, the second scan signal, the third scan signal, or the fourth scan signal may mean that a gate-on voltage is supplied to the first scan line SL1, the second scan line SL2, the third scan line SL3, or the fourth scan line SL4. In addition, not supplying the first scan signal, the second scan signal, the third scan signal, or the fourth scan signal may mean that a gate-off voltage is supplied to the first scan line SL1, the second scan line SL2, the third scan line SL3, or the fourth scan line SL4.

[0062] In Figure 2 In Figure 2 , the illustrated first scan driver 132, second scan driver 134, third scan driver 136, and fourth scan driver 138 are respectively connected to the first scan line SL1, the second scan line SL2, the third scan line SL3, and the fourth scan line SL4. However, embodiments of the present disclosure are not limited thereto. In an example, at least two of the first scan line SL1, the second scan line SL2, the third scan line SL3, and the fourth scan line SL4 (at least two of SL1, SL2, SL3, and SL4) may be driven by one scan driver.

[0063] The data driver 140 may receive the output data Dout and the data driving signal DCS from the timing controller 120. The data driving signal DCS may include a sampling signal and / or a timing signal necessary for driving the data driver 140. The data driver 140 may generate a data signal based on the data driving signal DCS and the output data Dout. In an example, the data driver 140 may generate an analog data signal based on the gray scale of the output data Dout. The data driver 140 may supply the data signal to the data lines DL1 to DLm in synchronization with the first scan signal.

[0064] The emission driver 150 may receive an emission drive signal ECS from the timing controller 120. The emission start signal and the clock signal necessary to drive the emission driver 150 may be included in the emission drive signal ECS. The emission driver 150 may generate an emission control signal while shifting the emission start signal corresponding to the clock signal.

[0065] In an example, as Figure 2 shown, the emission driver 150 may receive an emission start signal EFLM and generate an emission control signal while shifting the emission start signal EFLM corresponding to the clock signal. The emission driver 150 may sequentially supply the emission control signal to the emission control lines EL1 to ELo.

[0066] In Figure 2 it, the emission driver 150 is illustrated as receiving one emission start signal EFLM. However, embodiments of the present disclosure are not limited thereto. According to some embodiments, the emission driver 150 may receive two or more emission start signals.

[0067] The emission control signal may be set to a gate cut-off voltage so that the transistors included in the pixel PX may be cut off. In an example, the emission control signal having a high level may be supplied to the P-type transistor, and the emission control signal having a low level may be supplied to the N-type transistor. The transistor supplied with the emission control signal may be cut off corresponding to the emission control signal. After that, the supply of the emission control signal may mean that the gate cut-off voltage is supplied to the emission control line EL. In addition, the non-supply of the emission control signal may mean that the gate conduction voltage is supplied to the emission control line EL.

[0068] The timing controller 120 may receive input data Din and a control signal CS from the host system through an interface. In an example, the timing controller 120 may receive the input data Din and the control signal CS from at least one of a graphics processing unit (GPU), a central processing unit (CPU), or an application processor (AP) included in the host system. Various signals including a clock signal may be included in the control signal CS.

[0069] The timing controller 120 may generate a scan drive signal SCS, a data drive signal DCS, and an emission drive signal ECS based on the control signal CS. The scan drive signal SCS, the data drive signal DCS, and the emission drive signal ECS may be respectively supplied to the scan driver 130, the data driver 140, and the emission driver 150.

[0070] The timing controller 120 may rearrange the input data Din to fit the specifications of the display device 100. In addition, the timing controller 120 may generate the output data Dout by correcting the input data Din and supply the output data Dout to the data driver 140. According to some embodiments, the timing controller 120 may correct the input data Din corresponding to the optical measurement results measured during the processing.

[0071] The power supply 160 may generate various power supplies required to drive the display device 100. In an example, the power supply 160 may generate a first driving power supply VDD, a second driving power supply VSS, a first initialization power supply Vint1, and a second initialization power supply Vint2.

[0072] The first driving power supply VDD may be a power supply that supplies a driving current to the pixel PX. The second driving power supply VSS may be a power supply to which the driving current from the pixel PX is supplied. During a period when the pixel PX is set to be in an emission state, the first driving power supply VDD may be set to a voltage higher than the voltage of the second driving power supply VSS.

[0073] The first initialization power supply Vint1 may be a voltage for initializing the gate electrode of the driving transistor (the first transistor M21 shown in Figure 3 ) included in each of the pixels PX. The first initialization power supply Vint1 may be set to a voltage value lower than the voltage value of the data signal. The second initialization power supply Vint2 may be a voltage for initializing the first electrode (or anode electrode) of the light-emitting element LD (see Figure 3 ) included in each of the pixels PX. When the voltage of the second initialization power supply Vint2 is supplied to the first electrode of the light-emitting element LD, the second initialization power supply Vint2 may have a voltage value that turns off the light-emitting element LD.

[0074] The first driving power supply VDD generated by the power supply 160 may be supplied to the first power line PL1, the second driving power supply VSS generated by the power supply 160 may be supplied to the second power line PL2, the first initialization power supply Vint1 generated by the power supply 160 may be supplied to the third power line PL3, and the second initialization power supply Vint2 generated by the power supply 160 may be supplied to the fourth power line PL4. The first power line PL1, the second power line PL2, the third power line PL3, and the fourth power line PL4 may be commonly connected to the pixel PX, but embodiments of the present disclosure are not limited thereto.

[0075] According to some embodiments, the first power line PL1 may be configured with multiple power lines, and the multiple power lines may be connected to different pixels PX. According to some embodiments, the second power line PL2 may be configured with multiple power lines, and the multiple power lines may be connected to different pixels PX. According to some embodiments, the third power line PL3 may be configured with multiple power lines, and the multiple power lines may be connected to different pixels PX. According to some embodiments, the fourth power line PL4 may be configured with multiple power lines, and the multiple power lines may be connected to different pixels PX. That is, according to some embodiments of the present disclosure, the pixel PX may be connected to any one of the multiple power lines of the first power line PL1, any one of the multiple power lines of the second power line PL2, any one of the multiple power lines of the third power line PL3, and any one of the multiple power lines of the fourth power line PL4.

[0076] Figure 3 is a diagram illustrating Figure 1 an aspect of the pixel shown in. In Figure 3 it, a pixel located on the i-th horizontal line and the j-th vertical line will be illustrated.

[0077] Referring to Figure 3 , according to some embodiments of the present disclosure, the pixel PXij may be connected to corresponding signal lines SL1i, SL2i, SL3i, SL4i, ELk, and DLj. For example, the pixel PXij may be connected to the i-th first scan line SL1i (hereinafter also referred to as the first scan line SL1i), the i-th second scan line SL2i (hereinafter also referred to as the second scan line SL2i), the i-th third scan line SL3i (hereinafter also referred to as the third scan line SL3i), the i-th fourth scan line SL4i (hereinafter also referred to as the fourth scan line SL4i), the k-th emission control line ELk, and the j-th data line DLj. According to some embodiments, the pixel PXij may be further connected to the first power line PL1, the second power line PL2, the third power line PL3, and the fourth power line PL4.

[0078] The i-th third scan line SL3i may be the (i - 1)-th second scan line SL2i - 1. The i-th fourth scan line SL4i may be the (i - 1)-th first scan line SL1i - 1. The signals actually required to drive the pixel PXij may be set as the first scan signal GW, the second scan signal GC, and the emission control signal EM. That is, the i-th third scan line SL3i may be driven by the second scan signal of the previous pixel row, and the i-th fourth scan line SL4i may be driven by the first scan signal of the previous pixel row.

[0079] According to some embodiments of the present disclosure, the pixel PXij may include a light-emitting element LD and a pixel circuit for controlling the amount of current supplied to the light-emitting element LD.

[0080] The light-emitting element LD can be connected between the first power line PL1 and the second power line PL2. In the example, the first electrode (or anode electrode) of the light-emitting element LD can be electrically connected to the first power line PL1 via the sixth transistor M26, the third node N23, the first transistor M21, the second node N22, and the fifth transistor M25, and the second electrode (or cathode electrode) of the light-emitting element LD can be electrically connected to the second power line PL2. The light-emitting element LD can generate light having a luminance (e.g., a set luminance or a predetermined luminance) corresponding to the amount of current supplied from the first power line PL1 to the second power line PL2 via the pixel circuit.

[0081] The light-emitting element LD can be selected as an organic light-emitting diode. In addition, the light-emitting element LD can be selected as an inorganic light-emitting diode such as a micro light-emitting diode (LED) or a quantum dot light-emitting diode. In addition, the light-emitting element LD can be an element composed of a combination of an organic material and an inorganic material. In Figure 3 the figure, the illustrated pixel PXij includes a single light-emitting element LD. However, according to some embodiments, the pixel PXij can include a plurality of light-emitting elements LD, and the plurality of light-emitting elements LD can be connected in series, in parallel, or in series / parallel with each other.

[0082] The pixel circuit can include a first transistor M21, a second transistor M22, a third transistor M23, a fourth transistor M24, a fifth transistor M25, a sixth transistor M26, a seventh transistor M27, and a storage capacitor Cst.

[0083] The first electrode of the first transistor M21 (or driving transistor) can be connected to the second node N22, and the second electrode of the first transistor M21 can be connected to the third node N23. In addition, the gate electrode of the first transistor M21 can be connected to the first node N21. The first transistor M21 can control the amount of current supplied from the first driving power supply VDD to the second driving power supply VSS via the light-emitting element LD corresponding to the voltage of the first node N21.

[0084] The second transistor M22 can be connected between the data line DLj and the second node N22. In addition, the gate electrode of the second transistor M22 can be electrically connected to the first scan line SL1i. When the first scan signal GW is supplied to the first scan line SL1i, the second transistor M22 can be turned on to electrically connect the data line DLj and the second node N22 to each other.

[0085] The first electrode of the third transistor M23 may be connected to the first node N21, and the second electrode of the third transistor M23 may be electrically connected to the third power line PL3. In addition, the gate electrode of the third transistor M23 may be electrically connected to the third scan line SL3i. When the third scan signal GI is supplied to the third scan line SL3i, the third transistor M23 may be turned on to supply the voltage of the first initialization power supply Vint1 to the first node N21. The first initialization power supply Vint1 may be set to a voltage value lower than the voltage value of the data signal supplied to the data line DLj.

[0086] The fourth transistor M24 may be connected between the first node N21 and the third node N23. In addition, the gate electrode of the fourth transistor M24 may be electrically connected to the second scan line SL2i. When the second scan signal GC is supplied to the second scan line SL2i, the fourth transistor M24 may be turned on to electrically connect the first node N21 and the third node N23 to each other. That is, when the fourth transistor M24 is turned on, the first transistor M21 may be diode-connected.

[0087] The first electrode of the fifth transistor M25 may be electrically connected to the first power line PL1, and the second electrode of the fifth transistor M25 may be connected to the second node N22. In addition, the gate electrode of the fifth transistor M25 may be electrically connected to the emission control line ELk. The fifth transistor M25 may be turned off when the emission control signal EM is supplied to the emission control line ELk, and may be turned on when the emission control signal EM is not supplied.

[0088] The sixth transistor M26 may be connected between the third node N23 and the first electrode of the light-emitting element LD. In addition, the gate electrode of the sixth transistor M26 may be electrically connected to the emission control line ELk. The sixth transistor M26 may be turned off when the emission control signal EM is supplied to the emission control line ELk, and may be turned on when the emission control signal EM is not supplied.

[0089] The first electrode of the seventh transistor M27 may be connected to the first electrode of the light-emitting element LD, and the second electrode of the seventh transistor M27 may be electrically connected to the fourth power line PL4. In addition, the gate electrode of the seventh transistor M27 may be electrically connected to the fourth scan line SL4i. When the fourth scan signal GB is supplied to the fourth scan line SL4i, the seventh transistor M27 may be turned on to supply the voltage of the second initialization power supply Vint2 to the first electrode of the light-emitting element LD.

[0090] When the voltage of the second initialization power supply Vint2 is supplied to the first electrode of the light-emitting element LD, the parasitic capacitor of the light-emitting element LD can be discharged. As the residual voltage charged in the parasitic capacitor of the light-emitting element LD is discharged (or removed), accidental minute emission can be prevented. Therefore, the black display ability of the pixel PXij can be improved.

[0091] The storage capacitor Cst can be connected between the first power line PL1 and the first node N21. The storage capacitor Cst can store the voltage applied to the first node N21.

[0092] According to some embodiments, the first transistor M21, the second transistor M22, the fifth transistor M25, the sixth transistor M26, and the seventh transistor M27 can be implemented with polysilicon semiconductor transistors. For example, the first transistor M21, the second transistor M22, the fifth transistor M25, the sixth transistor M26, and the seventh transistor M27 can include a polysilicon semiconductor layer formed as an active layer (channel) by a low-temperature polysilicon (LTPS) process. In addition, the first transistor M21, the second transistor M22, the fifth transistor M25, the sixth transistor M26, and the seventh transistor M27 can be implemented with P-type polysilicon semiconductor transistors (e.g., PMOS transistors). Therefore, the gate turn-on voltage for turning on the first transistor M21, the second transistor M22, the fifth transistor M25, the sixth transistor M26, and the seventh transistor M27 can have a low level. Because polysilicon semiconductor transistors have the advantage of high response speed, polysilicon semiconductor transistors can be applied to switching elements that require fast switching.

[0093] According to some embodiments, the third transistor M23 and the fourth transistor M24 can be formed of oxide semiconductor transistors. For example, the third transistor M23 and the fourth transistor M24 can be implemented with N-type oxide semiconductor transistors (e.g., NMOS transistors) and include an oxide semiconductor layer as an active layer. Therefore, the gate turn-on voltage for turning on the third transistor M23 and the fourth transistor M24 can have a high level.

[0094] The oxide semiconductor transistor can be formed by a low-temperature process and has a charge mobility lower than that of the polysilicon semiconductor transistor. That is, the oxide semiconductor transistor has excellent off-state current characteristics. Therefore, when the third transistor M23 and the fourth transistor M24 are implemented with oxide semiconductor transistors, the leakage current according to low-frequency driving can be minimized or reduced, and thus, the display quality can be relatively improved.

[0095] Figure 4 is a waveform diagram illustrating aspects of a driving method of the pixel shown in Figure 3 as shown in some embodiments.

[0096] Reference Figure 4 , a frame period may include a non-transmission period P_NE, and the non-transmission period P_NE may include an initialization period P_INT, a compensation period P_C, and a writing period P_W. The writing period P_W may be included in the compensation period P_C.

[0097] During the non-transmission period P_NE, the emission control signal EM may have a high level. The fifth transistor M25 and the sixth transistor M26 may be turned off in response to the emission control signal EM having a high level, and the pixel PXij may not emit light.

[0098] During the initialization period P_INT, the third scan signal GI may have a high level. The third transistor M23 may be turned on in response to the third scan signal GI having a high level, and the voltage of the first initialization power supply Vint1 of the third power line PL3 may be supplied to the first node N21.

[0099] After that, during the compensation period P_C, the second scan signal GC may have a high level. The fourth transistor M24 may be turned on in response to the second scan signal GC having a high level, and the first transistor M21 may be diode-connected.

[0100] During the writing period P_W, the first scan signal GW may have a low level. The second transistor M22 may be turned on in response to the first scan signal GW having a low level, and the data signal may be supplied from the j-th data line DLj to the second node N22. In addition, since the fourth transistor M24 is in an on state in response to the second scan signal GC having a high level, the data signal may be transmitted from the second node N22 to the first node N21 via the first transistor M21 and the fourth transistor M24. Since the form in which the first transistor M21 is diode-connected is maintained through the turned-on fourth transistor M24, the first node N21 may have the data signal obtained by compensating for the threshold voltage of the first transistor M21.

[0101] Before the writing period P_W, the fourth scan signal GB may have a low level. The seventh transistor M27 may be turned on in response to the fourth scan signal GB having a low level, and the voltage of the second initialization power supply Vint2 may be supplied to the first electrode of the light-emitting element LD.

[0102] Thereafter, the non-emission period P_NE may end, and the emission control signal EM may have a low level. The fifth transistor M25 and the sixth transistor M26 may turn on in response to the emission control signal EM having a low level. When the fifth transistor M25 and the sixth transistor M26 are turned on, a current flow path from the first power line PL1 through the fifth transistor M25, the first transistor M21, the sixth transistor M26, and the light-emitting element LD to the second power line PL2 is formed. According to the operation of the first transistor M21, a drive current corresponding to the voltage of the first node N21 may flow through the light-emitting element LD, and the light-emitting element LD may emit light with a brightness corresponding to the drive current.

[0103] Figure 5 is a diagram illustrating a stage circuit according to some embodiments of the present disclosure. The stage circuit according to some embodiments of the present disclosure may be included in the second scan driver 134 and / or the third scan driver 136 that supply a scan signal having a high level. The stage circuit according to some embodiments of the present disclosure may be included in the emission driver 150 that supplies an emission control signal having a high level. In Figure 5 will describe the stage circuit STi located on the i-th horizontal line.

[0104] Reference Figure 5 , the stage circuit STi according to some embodiments of the present disclosure may include a first input terminal IN1, a second input terminal IN2, a first power input terminal VIN1, a second power input terminal VIN2, a clock input terminal CK, a first output terminal Gout, and a second output terminal Cout.

[0105] The first input terminal IN1 may receive an enabled carry signal CRi-1 input from a previous stage circuit (or receive a first start signal FLMa (see Figure 8 )). The first start signal FLMa or the enabled carry signal CRi-1 of the previous stage circuit may be set to a gate-on voltage, such as a low-level voltage, so that the transistors included in the stage circuit STi may turn on.

[0106] The second input terminal IN2 may receive an enabled output signal OSi-1 input from a previous stage circuit (or receive a second start signal FLMb (see Figure 8 )). The second start signal FLMb or the enabled output signal OSi-1 of the previous stage circuit may be set to a gate-off voltage, such as a high-level voltage, so that the transistors included in the stage circuit STi may turn off.

[0107] The clock input terminal CK may receive a first clock signal CLK1 (or a second clock signal CLK2 (see Figure 8))。In the example, the clock input terminal CK included in the odd-numbered (or even-numbered) stage circuit can receive the first clock signal CLK1, and the clock input terminal CK included in the even-numbered (or odd-numbered) stage circuit can receive the second clock signal CLK2. That is, the first clock signal CLK1 and the second clock signal CLK2 can be alternately input to the stage circuit for each horizontal line. The first clock signal CLK1 and the second clock signal CLK2 can be signals having the same period and phases inverted from each other.

[0108] The first power input terminal VIN1 can receive the voltage of the first power supply VGH. The voltage of the first power supply VGH can be set to a gate cut-off voltage, such as a high-level voltage, so that the transistors included in the stage circuit STi can be cut off. The second power input terminal VIN2 can receive the voltage of the second power supply VGL. The voltage of the second power supply VGL can be set to a gate conduction voltage, such as a low-level voltage, so that the transistors included in the stage circuit STi can be turned on.

[0109] The first output terminal Gout can output an enabled output signal OSi. The enabled output signal OSi can be set to a high-level voltage and is supplied as the second scan signal GC, the third scan signal GI, or the emission control signal EM to the pixel PX. The second output terminal Cout can output an enabled carry signal CRi. The enabled carry signal CRi can be set to a low-level voltage and is supplied to the subsequent stage circuit.

[0110] Figure 6 is a diagram illustrating a gate driver according to some embodiments of the present disclosure. Figure 6 The gate driver shown in can be at least one of the second scan driver 134, the third scan driver 136, and the emission driver 150.

[0111] Reference Figure 6 , the gate driver according to some embodiments of the present disclosure can include stage circuits ST1, ST2, …, STn-1, and STn positioned for each horizontal line.

[0112] The first stage circuit ST1 can receive the first start signal FLMa input through the first input terminal IN1 and receive the second start signal FLMb input through the second input terminal IN2.

[0113] Each of the other stage circuits ST2 to STn except for the first stage circuit ST1 can be supplied with the enabled carry signal CR of the preceding stage circuit through the first input terminal IN1 and can be supplied with the enabled output signal OS of the preceding stage circuit through the second input terminal IN2.

[0114] The first clock signal CLK1 can be supplied to the clock input terminal CK of each of the odd-numbered stage circuits ST1, …, and STn-1, and the second clock signal CLK2 can be supplied to the clock input terminal CK of each of the even-numbered stage circuits ST2, …, and STn.

[0115] The stage circuits ST1 to STn can be driven as a shift register, and while shifting the first start signal FLMa and the second start signal FLMb corresponding to the clock signals CLK1 and CLK2, sequentially output the enabled output signals OS1 to OSn and the enabled carry signals CR1 to CRn.

[0116] Figure 7 is a diagram showing a stage circuit according to some embodiments of the present disclosure. In Figure 7 it, the i-th stage circuit STi will be shown. The stage circuits ST1 to STn can be implemented as circuits substantially the same as the i-th stage circuit STi.

[0117] Reference Figure 7 , the stage circuit STi can include an output unit (or output circuit or output component) 202, a first driver 204, and a second driver 206.

[0118] The output unit 202 can receive the voltage of the first power supply VGH input from the first power input terminal VIN1, and receive the voltage of the second power supply VGL input from the second power input terminal VIN2. The output unit 202 can output the enabled output signal OSi to the first output terminal Gout and the enabled carry signal CRi to the second output terminal Cout corresponding to the voltages of the first node N1 and the second node N2.

[0119] To this end, the output unit 202 can include a first output transistor MO1, a second output transistor MO2, and a capacitor CO.

[0120] The first output transistor MO1 can be connected between the first power input terminal VIN1 and the first output terminal Gout. In addition, the gate electrode of the first output transistor MO1 can be connected to the first node N1. The first output transistor MO1 can control the electrical connection between the first power input terminal VIN1 and the first output terminal Gout while being turned on or off corresponding to the voltage of the first node N1. When the first power input terminal VIN1 and the first output terminal Gout are electrically connected to each other, the voltage of the first power supply VGH can be output to the first output terminal Gout. The voltage of the first power supply VGH supplied to the first output terminal Gout can be supplied to the scan line and / or the emission control line as the enabled output signal OSi (or the supply of the output signal OSi).

[0121] The second output transistor MO2 may be connected between the second power input terminal VIN2 and the first output terminal Gout. In addition, the gate electrode of the second output transistor MO2 may be connected to the second node N2. The second output transistor MO2 may control the electrical connection between the second power input terminal VIN2 and the first output terminal Gout while conducting or cutting off corresponding to the voltage of the second node N2. When the second power input terminal VIN2 and the first output terminal Gout are electrically connected to each other, the voltage of the second power supply VGL may be output to the first output terminal Gout. The voltage of the second power supply VGL supplied to the first output terminal Gout may be supplied to the scan line and / or the emission control line as a prohibited output signal OSi (or a suspension of the supply of the output signal OSi).

[0122] The capacitor CO may be connected between the first output terminal Gout and the second node N2. The capacitor CO may store the voltage between the first output terminal Gout and the second node N2.

[0123] The second output terminal Cout may be connected to the first node N1. The second output terminal Cout may supply the voltage of the first node N1 to the subsequent circuit as a carry signal CRi. When the first node N1 has a low-level voltage, an enabled carry signal CRi (or the supply of the carry signal CRi) may be supplied. When the first node N1 has a high-level voltage, a prohibited carry signal CRi (or a suspension of the supply of the carry signal CRi) may be supplied.

[0124] The first driver 204 may control the voltages of the first node N1 and the second node N2 corresponding to the voltage of the first power supply VGH supplied from the first power input terminal VIN1, the voltage of the second power supply VGL supplied from the second power input terminal VIN2, the previous output signal OSi-1 supplied to the second input terminal IN2, and the first clock signal CLK1 supplied to the clock input terminal CK.

[0125] For this purpose, the first driver 204 may include a third transistor M3, a fourth transistor M4, and a fifth transistor M5.

[0126] The third transistor M3 may be connected between the first power input terminal VIN1 and the first node N1. In addition, the gate electrode of the third transistor M3 may be connected to the third node N3. The third transistor M3 may control the electrical connection between the first node N1 and the first power input terminal VIN1 while conducting or cutting off corresponding to the voltage of the third node N3.

[0127] The fourth transistor M4 can be connected between the second node N2 and the third node N3. In addition, the gate electrode of the fourth transistor M4 can be connected to the second power input terminal VIN2. The on-state of the fourth transistor M4 can be maintained by the voltage of the second power supply VGL supplied from the second power input terminal VIN2. The second node N2 and the third node N3 can be maintained in an electrically connected state.

[0128] The fourth transistor M4 can prevent the voltage of the third node N3 from dropping below the voltage of the second power supply VGL corresponding to the change in the voltage of the second node N2. Similarly, the fourth transistor M4 can prevent the voltage of the second node N2 from dropping below the voltage of the second power supply VGL corresponding to the change in the voltage of the third node N3.

[0129] The fifth transistor M5 can be connected between the second input terminal IN2 and the third node N3. In addition, the gate electrode of the fifth transistor M5 can be connected to the clock input terminal CK. The fifth transistor M5 can control the electrical connection between the second input terminal IN2 and the third node N3 while conducting or cutting off corresponding to the first clock signal CLK1 supplied to the clock input terminal CK.

[0130] In the example, when the first clock signal CLK1 with a low level is supplied, the fifth transistor M5 can conduct to electrically connect the second input terminal IN2 and the third node N3 to each other. In the example, when the first clock signal CLK with a high level is supplied, the fifth transistor M5 can cut off to electrically isolate the second input terminal IN2 and the third node N3 from each other.

[0131] The second driver 206 can control the voltage of the first node N1 corresponding to the voltage of the first power supply VGH supplied from the first power input terminal VIN1, the previous carry signal CRi-1 supplied to the first input terminal IN1, the previous output signal OSi-1 supplied to the second input terminal IN2, and the first clock signal CLK1 supplied to the clock input terminal CK.

[0132] For this purpose, the second driver 206 can include a first transistor M1, a second transistor M2, a control transistor MC, a first capacitor C1, and a second capacitor C2.

[0133] The first transistor M1 can be connected between the first node N1 and the clock input terminal CK. In addition, the gate electrode of the first transistor M1 can be connected to the control node NC. The first transistor M1 can control the electrical connection between the clock input terminal CK and the first node N1 while conducting or cutting off corresponding to the voltage of the control node NC.

[0134] The second transistor M2 may be connected between the control node NC and the first power input terminal VIN1. In addition, the gate electrode of the second transistor M2 may be connected to the second input terminal IN2. The second transistor M2 may be turned off when a previous enabled output signal OSi-1 is supplied to the second input terminal IN2, and may be turned on when a previous disabled output signal OSi-1 is supplied to the second input terminal IN2.

[0135] The control transistor MC and the first capacitor C1 may be connected in series between the control node NC and the clock input terminal CK.

[0136] The control transistor MC may be connected between the control node NC and the second electrode of the first capacitor C1. In addition, the gate electrode of the control transistor MC may be connected to the first input terminal IN1. The control transistor MC may be turned on when a previous enabled carry signal CRi-1 is supplied to the first input terminal IN1, and may be turned off when a previous disabled carry signal CRi-1 is supplied to the first input terminal IN1.

[0137] The first electrode of the first capacitor C1 may be connected to the clock input terminal CK, and the second electrode of the first capacitor C1 may be connected to the control transistor MC. The first capacitor C1 may transfer the voltage of the first clock signal CLK1 input to the clock input terminal CK to the control node NC while being driven as a coupling capacitor.

[0138] The second capacitor C2 may be connected between the first power input terminal VIN1 and the first node N1. The second capacitor C2 may store the voltage of the first node N1.

[0139] Figure 8 is a waveform diagram showing aspects of a driving method of the Figure 7 stage circuit shown in accordance with some embodiments.

[0140] Referring Figure 8 , at a first time t1, a previous enabled carry signal CRi-1 may be input to the first input terminal IN1, and a previous enabled output signal OSi-1 may be input to the second input terminal IN2. When the stage STi is the first stage, a first start signal FLMa may be input to the first input terminal IN1, and a second start signal FLMb may be input to the second input terminal IN2. The previous enabled carry signal CRi-1 (or the first start signal FLMa) may be set to a low level, and the previous enabled output signal OSi-1 (or the second start signal FLMb) may be set to a high level.

[0141] When the prior enabled carry signal CRi-1 is input to the first input terminal IN1, the control transistor MC can be turned on. When the control transistor MC is turned on, the second electrode of the first capacitor C1 can be electrically connected to the control node NC.

[0142] When the prior enabled output signal OSi-1 is supplied to the second input terminal IN2, the second transistor M2 can be turned off. When the second transistor M2 is turned off, the first power input terminal VIN1 and the control node NC can be electrically isolated from each other.

[0143] At the second time t2, the first clock signal CLK1 having a low level can be supplied to the clock input terminal CK. The voltage of the clock input terminal CK can change from a high level to a low level, and the voltage of the control node NC can be reduced by the coupling of the first capacitor C1. When the voltage of the control node NC is reduced, the first transistor M1 can be turned on.

[0144] When the first transistor M1 is turned on, the first clock signal CLK1 having a low level can be supplied to the first node N1, and thus, the first node N1 can be set to a low-level voltage. The second capacitor C2 can store the low-level voltage. The low-level voltage supplied to the first node N1 can be supplied to the second output terminal Cout. The low-level voltage supplied to the second output terminal Cout can be supplied as an enabled carry signal CRi to the subsequent circuit.

[0145] When a low-level voltage is supplied to the first node N1, the first output transistor MO1 can be turned on. When the first output transistor MO1 is turned on, the voltage of the first power supply VGH can be supplied to the first output terminal Cout. The voltage of the first power supply VGH (i.e., a high-level voltage) supplied to the first output terminal Gout can be supplied as an enabled output signal OSi to the subsequent circuit, the scan line, and / or the emission control line.

[0146] At the second time t2, when the first clock signal CLK1 having a low level is supplied to the clock input terminal CK, the fifth transistor M5 can be turned on. When the fifth transistor M5 is turned on, the second input terminal IN2 and the third node N3 can be electrically connected to each other, and thus, the third node N3 can be supplied with the prior enabled output signal OSi-1. When the prior enabled output signal OSi-1 is supplied to the third node N3, the third node N3 can be set to a high-level voltage, and thus, the second node N2 can also be set to a high-level voltage.

[0147] When the voltage of the third node N3 is set to a high level, the third transistor M3 can be turned off. When the third transistor M3 is turned off, the first node N1 can stably maintain a low-level voltage. When a high-level voltage is supplied to the second node N2, the second output transistor MO2 can be turned off. When the second output transistor MO2 is turned off, the first output terminal Gout can stably maintain the voltage of the first power supply VGH.

[0148] At the third time t3, a first clock signal CLK1 having a high level can be supplied to the clock input terminal CK. When the voltage of the clock input terminal CK changes from a low level to a high level, the voltage of the control node NC can increase through the coupling of the first capacitor C1, and thus, the first transistor M1 can be turned off. When the first transistor M1 is turned off, the low-level voltage of the first node N1 can be stably maintained through the second capacitor C2.

[0149] At the fourth time t4, a prior inhibited carry signal CRi-1 can be input to the first input terminal IN1, and a prior inhibited output signal OSi-1 can be input to the second input terminal IN2.

[0150] When the prior inhibited carry signal CRi-1 is input to the first input terminal IN1, the control transistor MC can be turned off. When the control transistor MC is turned off, the second electrode of the first capacitor C1 can be electrically isolated from the control node NC. The second electrode of the first capacitor C1 can be set to a floating state.

[0151] When the prior inhibited output signal OSi-1 is supplied to the second input terminal IN2, the second transistor M2 can be turned on. When the second transistor M2 is turned on, the voltage of the first power supply VGH can be supplied to the control node NC. When the voltage of the first power supply VGH is supplied to the control node NC, the first transistor M1 can be turned off. When the first transistor M1 is turned off, the electrical connection between the first node N1 and the clock input terminal CK can be blocked.

[0152] At the fifth time t5, a first clock signal CLK1 having a low level can be supplied to the clock input terminal CK. When the first clock signal CLK1 having a low level is supplied to the clock input terminal CK, the fifth transistor M5 can be turned on.

[0153] When the fifth transistor M5 is turned on, the second input terminal IN2 and the third node N3 can be electrically connected to each other, and thus, the third node N3 can be supplied with the voltage of the prior inhibited output signal OSi-1 (i.e., a low-level voltage). When the voltage of the third node N3 is set to a low level, the voltage of the second node N2 can also be set to a low level.

[0154] When the third node N3 is set to a low-level voltage, the third transistor M3 can be turned on. When the third transistor M3 is turned on, the voltage of the first power supply VGH can be supplied to the first node N1. The voltage of the first power supply VGH supplied to the first node N1 can be supplied to the second output terminal Cout. The voltage of the first power supply VGH supplied to the second output terminal Cout can be supplied as a prohibited carry signal CRi to the subsequent circuit.

[0155] When the voltage of the first power supply VGH is supplied to the first node N1, the first output transistor MO1 can be turned off. When the first output transistor MO1 is turned off, the electrical connection between the first power input terminal VIN1 and the first output terminal Gout can be blocked.

[0156] When a low-level voltage is supplied to the second node N2, the second output transistor MO2 can be turned on. When the second output transistor MO2 is turned on, the voltage of the second power supply VGL can be supplied to the first output terminal Gout. The voltage of the second power supply VGL supplied to the first output terminal Gout can be supplied as a prohibited output signal OSi to the subsequent stage, scan line, and / or emission control line.

[0157] At the same time, since the control transistor MC is set to the cut-off state after the fourth time t4, that is, since the second electrode of the first capacitor C1 is set to the floating state, even when the voltage of the first clock signal CLK1 changes, the voltage of the control node NC does not change.

[0158] In addition, since the second electrode of the first capacitor C1 is set to the floating state, regardless of the change in the voltage of the first clock signal CLK1, the first capacitor C1 is not charged / discharged, and thus, power consumption can be reduced.

[0159] This will be described in detail. When the control transistor MC is removed, the second electrode of the first capacitor C1 can be supplied with the voltage of the first power supply VGH after the fourth time t4. The first capacitor C1 can be continuously charged / discharged corresponding to the change in the voltage of the first clock signal CLK1, and thus, power consumption may increase.

[0160] On the other hand, as in the embodiment of the present disclosure, when the second electrode of the first capacitor C1 is set to the floating state using the control transistor MC, the first capacitor C1 is not unnecessarily charged / discharged, and thus, power consumption can be reduced.

[0161] Figure 9 Illustration Figure 7 Charging / discharging of the first capacitor in the stage circuit shown in Figure 9In this case, the X-axis represents time [ms], the Y-axis of the first clock signal CLK1 represents voltage [V], and the Y-axis of each of the comparative example and the embodiment represents current [μA]. In Figure 9 the embodiment indicates Figure 7 the stage circuit STi shown in Figure 7 and the comparative example indicates the case where the control transistor MC is removed in

[0162] Reference Figure 9 In the case of the comparative example, during the driving period of the stage circuit STi, the first capacitor is continuously charged / discharged, and thus, power consumption may be required. In contrast, according to some embodiments of the present disclosure, the first capacitor C1 is charged / discharged only during the period in which the enabled output signal OSi is supplied in the stage circuit STi, and is not charged / discharged during other periods. That is, in the case of the embodiment of the present disclosure, the power consumption caused by the charging / discharging of the first capacitor C1 can be minimized or reduced. According to some embodiments of the present disclosure, compared with the comparative example, the power consumption caused by the switching of the first clock signal CLK1 can be reduced by about 82%.

[0163] Figure 10 is a circuit diagram illustrating a stage circuit according to some embodiments of the present disclosure. In Figure 10 the i-th stage circuit STia will be described. In Figure 10 the components that are the same as those shown in Figure 7 are denoted by the same reference numerals, and repeated descriptions will be omitted.

[0164] Reference Figure 10 According to some embodiments of the present disclosure, the stage circuit STia may include an output unit 202, a first driver 204, and a second driver 206a.

[0165] The second driver 206a may control the voltage of the first node N1 corresponding to the voltage of the first power supply VGH supplied from the first power input terminal VIN1, the previous carry signal CRi-1 supplied to the first input terminal IN1, the previous output signal OSi-1 supplied to the second input terminal IN2, and the first clock signal CLK1 supplied to the clock input terminal CK.

[0166] To this end, the second driver 206a may include a first transistor M1, a second transistor M2, a control transistor MCa, a first capacitor C1a, and a second capacitor C2.

[0167] The control transistor MCa and the first capacitor C1a may be connected in series between the control node NC and the clock input terminal CK.

[0168] The second electrode of the first capacitor C1a may be connected to the control node NC. The control transistor MCa may be connected between the first electrode of the first capacitor C1a and the clock input terminal CK. Further, the gate electrode of the control transistor MCa may be connected to the first input terminal IN1. The control transistor MCa may be turned on when a prior enabled carry signal CRi-1 is supplied to the first input terminal, and may be turned off otherwise.

[0169] When the control transistor MCa is turned off, the first electrode of the first capacitor C1a may be set to a floating state. That is, when the control transistor MCa is turned off, the clock input terminal CK and the first capacitor C1a may be electrically isolated from each other. Then, the first capacitor C1a is not charged / discharged by the first clock signal CLK1, and thus, power consumption may be reduced.

[0170] In a stage circuit according to some embodiments of the present disclosure and a display device including the stage circuit, charging / discharging of a capacitor may be minimized or reduced, thereby relatively reducing power consumption.

[0171] An electronic or electrical device and / or any other related device or component according to embodiments of the utility model described herein may be implemented using any suitable hardware, firmware (e.g., application specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, various components of these devices may be formed on an integrated circuit (IC) chip or on separate IC chips. Further, various components of these devices may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. Further, various components of these devices may be processes or threads running on one or more processors in one or more computing devices, the processes or threads executing computer program instructions and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in a memory, which may be implemented using a standard memory device such as, for example, random access memory (RAM) in a computing device. The computer program instructions may also be stored in other non-transitory computer-readable media such as, for example, a CD-ROM or a flash drive. Further, those skilled in the art should recognize that the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed across one or more other computing devices, without departing from the spirit and scope of the exemplary embodiments of the present utility model

[0172] Example embodiments have been disclosed herein, and, although specific terms are employed, they are used and interpreted in a generic and descriptive sense only and not for purposes of limitation. In some instances, as will be apparent to those of ordinary skill in the art as of the filing date of this application, features, characteristics and / or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics and / or elements described in connection with other embodiments, unless otherwise specifically indicated. Accordingly, those of ordinary skill in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the disclosure as set forth in the claims and their equivalents.

Claims

1. A stage circuit, comprising: an output unit connected to a first power input terminal to which a first power source is input and a second power input terminal to which a second power source is input, the output unit being configured to output an enabled output signal to the first output terminal and an enabled carry signal to the second output terminal corresponding to a voltage of the first node and a voltage of the second node; a first driver connected to the first power input terminal, the second power input terminal, a clock input terminal configured to receive a clock signal, and a second input terminal configured to receive a prior enabled output signal, the first driver being configured to control the voltage of the first node and the voltage of the second node; as well as a second driver connected to a first input terminal configured to receive a previously enabled carry signal, the second input terminal, the first power input terminal, and the clock input terminal, the second driver being configured to control the voltage of the first node, Wherein, the second driver comprises: a first transistor connected between the first node and the clock input terminal, the first transistor including a gate electrode connected to a control node; and A control transistor and a first capacitor are connected in series between the control node and the clock input terminal, and the control transistor includes a gate electrode connected to the first input terminal.

2. The stage circuit according to claim 1, wherein: The enabled output signal is set to a high level, and the enabled carry signal is set to a low level.

3. The stage circuit according to claim 2, wherein: The control transistor is connected between the control node and the first capacitor.

4. The stage circuit according to claim 3, wherein: The control transistor is configured to be set in an off state based on a carry signal that is disabled as a high-level voltage being input to the first input terminal.

5. The stage circuit according to claim 2, wherein: The control transistor is connected between the first capacitor and the clock input terminal.

6. The stage circuit according to claim 5, wherein: The control transistor is configured to be set in an off state based on a carry signal that is disabled as a high-level voltage being input to the first input terminal.

7. The stage circuit according to any one of claims 1 to 6, wherein: The second driver further comprises: a second capacitor connected between the first power input terminal and the first node; and A second transistor is connected between the first power input terminal and the control node, the second transistor including a gate electrode connected to the second input terminal.

8. The stage circuit according to any one of claims 1 to 6, wherein: The output unit comprises: a first output transistor connected between the first power input terminal and the first output terminal, the first output transistor including a gate electrode connected to the first node; a second output transistor connected between the first output terminal and the second power input terminal, the second output transistor including a gate electrode connected to the second node; and a capacitor connected between the first output terminal and the second node, and Wherein, the second output terminal is connected to the first node.

9. The stage circuit according to any one of claims 1 to 6, wherein: The first driver comprises: a third transistor connected between the first power input terminal and the first node, the third transistor including a gate electrode connected to a third node; a fourth transistor connected between the third node and the second node, the fourth transistor including a gate electrode connected to the second power input terminal; and A fifth transistor is connected between the second input terminal and the third node, and includes a gate electrode connected to the clock input terminal.

10. A stage circuit comprising: an output unit configured to supply an output signal to the first output terminal and a carry signal to the second output terminal corresponding to a voltage of the first node and a voltage of the second node; a first driver configured to control the voltage of the first node and the voltage of the second node corresponding to a previous output signal and a clock signal; as well as a second driver configured to control the voltage of the first node corresponding to the previous output signal, the clock signal, and the previous carry signal, Wherein, the second driver comprises: a first transistor connected between the first node and a clock input terminal configured to receive the clock signal, the first transistor including a gate electrode connected to a control node; and a first capacitor and a control transistor connected in series between the control node and the clock input terminal, and The control transistor is configured to be turned on based on the prior carry signal being input to connect the first electrode of the first capacitor to the clock input terminal and the second electrode of the first capacitor to the control node, and is configured to be turned off based on the prior carry signal not being input to set the first capacitor to be in a floating state.

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