Package structure
By setting grooves in the encapsulation layer of the encapsulation structure, the problem of warping in the encapsulation structure is solved, and the packaging yield and device reliability are improved.
Patent Information
- Application Number
- CN202520926403.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-13
- Publication Date
- 2025-06-27
- Estimated Expiration
- 2035-05-13
AI Technical Summary
In semiconductor packaging technology, there is a warping problem in the packaging structure, which leads to poor device and affects the packaging yield.
A package structure is designed including an adapter plate, a chip assembly, conductive terminals and an encapsulation layer, in which grooves are provided to form discontinuous areas to block thermal expansion and thereby improve packaging warping.
By providing grooves in the encapsulation layer, warping of the packaging structure is improved, defects such as bridging caused by warping are avoided or reduced, and packaging yield and device reliability are improved.
Smart Images
Figure CN223038939U_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present disclosure relate to the field of semiconductor packaging technology, and particularly to a packaging structure. Background Art
[0002] In semiconductor packaging technology, a chip can be packaged to achieve protection, physical and / or electrical connection, etc. of the chip. Multiple chips can be integrated together through packaging technology; for example, a system-on-chip and a memory chip can be integrated together, and high-performance computing can be achieved. However, in a packaging structure, there may be a warping problem, which may cause device defects and affect the packaging yield. How to improve the warping of the packaging structure is an important research topic in this field. Summary of the Utility Model
[0003] At least one embodiment of the present disclosure provides a packaging structure having a chip component area, a peripheral area, and a plurality of terminal areas, and including: an interposer having opposite first and second sides; a chip component disposed in the chip component area on the first side of the interposer, electrically connected to the interposer, and including a plurality of chips disposed at intervals; a plurality of conductive terminals disposed in the plurality of terminal areas on the second side of the interposer; and an encapsulation layer disposed on the first side of the interposer and surrounding and encapsulating the plurality of chips of the chip component, wherein the encapsulation layer has a groove extending from a surface of the encapsulation layer remote from the interposer into the encapsulation layer, the groove being located outside the chip component area and within the peripheral area.
[0004] In the packaging structure provided by at least one embodiment of the present disclosure, a positive projection of a chip gap area between adjacent chips among the plurality of chips on the interposer is offset from a positive projection of the groove on the interposer.
[0005] In the packaging structure provided by at least one embodiment of the present disclosure, the encapsulation layer includes a first encapsulation portion covering and contacting a chip edge of the chip component, and the groove is located on a side of the first encapsulation portion remote from the chip component in a horizontal direction parallel to a main surface of the interposer and is spaced apart from the chip edge.
[0006] In the packaging structure provided by at least one embodiment of the present disclosure, the encapsulation layer further includes a second encapsulation portion located on a side of the groove remote from the first encapsulation portion in the horizontal direction, and opposite sidewalls of the groove are defined by opposite surfaces of the first encapsulation portion and the second encapsulation portion.
[0007] In the packaging structure provided by at least one embodiment of the present disclosure, a spacing distance between the groove and the chip edge in the horizontal direction is between 20 micrometers and 730 micrometers.
[0008] In the encapsulation structure provided according to at least one embodiment of the present disclosure, in a direction perpendicular to the main surface of the interposer, the depth of the groove is less than the thickness of the encapsulation layer.
[0009] In the encapsulation structure provided according to at least one embodiment of the present disclosure, the depth of the groove is less than or equal to 1 / 2 of the thickness of the encapsulation layer.
[0010] In the encapsulation structure provided according to at least one embodiment of the present disclosure, the chip component is electrically connected to the interposer through a plurality of conductive bumps, and the encapsulation structure further includes: an underfill layer, filling the space between the chip component and the interposer and surrounding the plurality of conductive bumps, wherein the underfill layer is covered by the encapsulation layer and is spaced apart from the groove.
[0011] In the encapsulation structure provided according to at least one embodiment of the present disclosure, the plurality of terminal regions include a first terminal region and a second terminal region, and the density of the plurality of conductive terminals in the first terminal region is greater than the density of the plurality of conductive terminals in the second terminal region; in a direction parallel to the main surface of the interposer, a first distance between the groove and the first terminal region is less than a second distance between the groove and the second terminal region; or the facing area between the groove and the first terminal region is greater than the facing area between the groove and the second terminal region.
[0012] In the encapsulation structure provided according to at least one embodiment of the present disclosure, the first terminal region and the second terminal region are arranged side by side in a first direction parallel to the main surface of the interposer, and both the first distance and the second distance are distances in the first direction.
[0013] In the encapsulation structure provided according to at least one embodiment of the present disclosure, the chip component includes a first chip, and the first chip has a first chip edge. The first terminal region and the groove are respectively located on opposite sides of the first chip edge in the first direction in the chip component region and the peripheral region, and the second terminal region is located on a side of the first terminal region away from the first chip edge in the first direction.
[0014] In the encapsulation structure provided according to at least one embodiment of the present disclosure, the first terminal region and the second terminal region are arranged side by side in a second direction parallel to the main surface of the interposer, the groove is located on one side of the first terminal region and the second terminal region in a first direction intersecting the second direction, and the facing area between the groove and the first terminal region in the first direction is greater than the facing area between the groove and the second terminal region in the first direction.
[0015] In the encapsulation structure provided according to at least one embodiment of the present disclosure, the first terminal region includes two opposite edges in the second direction, and the positive projections of the two edges on a reference plane perpendicular to the first direction overlap with the positive projection of the groove on the reference plane.
[0016] In the encapsulation structure provided according to at least one embodiment of the present disclosure, in the second direction, the first terminal region has a first length, the groove has a second length, and the second length is greater than or equal to the first length.
[0017] In the encapsulation structure provided according to at least one embodiment of the present disclosure, the chip assembly includes a first chip and a second chip. The positive projection of the first terminal region on the main surface of the adapter board overlaps with the positive projection of the first chip on the main surface of the adapter board, and the positive projection of the second terminal region on the main surface of the adapter board overlaps with the positive projection of the first chip or the second chip on the main surface of the adapter board.
[0018] In the encapsulation structure provided according to at least one embodiment of the present disclosure, the first chip is a logic chip and the second chip is a memory chip.
[0019] In the encapsulation structure provided according to at least one embodiment of the present disclosure, the plurality of terminal regions further includes an additional terminal region. The additional terminal region is located in the peripheral region, and a plurality of additional terminals are provided on the second side of the adapter board in the additional terminal region; and the positive projection of the groove on the main surface of the adapter board overlaps with the positive projection of the additional terminal region on the main surface of the adapter board.
[0020] In the encapsulation structure provided according to at least one embodiment of the present disclosure, the plurality of additional terminals includes dummy terminals.
[0021] In the encapsulation structure provided according to at least one embodiment of the present disclosure, it further includes: an additional filling layer filled in the groove of the encapsulation layer, and the coefficient of thermal expansion of the additional filling layer is less than the coefficient of thermal expansion of the encapsulation layer.
[0022] In the encapsulation structure provided according to at least one embodiment of the present disclosure, it further includes: an encapsulation substrate provided on a side of the adapter board away from the chip assembly and electrically connected to the adapter board through the plurality of conductive terminals.
[0023] In the encapsulation structure provided according to at least one embodiment of the present disclosure, it further includes: a heat dissipation member provided on a side of the chip assembly and the encapsulation layer away from the adapter board; and a thermal interface material layer provided between the heat dissipation member and the chip assembly, and a part of the thermal interface material layer fills the groove.
[0024] According to the packaging structure provided by at least one embodiment of the present disclosure, packaging warpage can be improved to avoid or reduce the risk of defects such as bridging of conductive terminals due to warpage, thereby improving the packaging yield and device reliability. Description of the Drawings
[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.
[0026] Figure 1 Schematic cross-sectional view showing a packaging structure according to some embodiments of the present disclosure.
[0027] Figure 2 Schematic plan view showing a packaging structure according to some embodiments of the present disclosure.
[0028] Figure 3 Schematic cross-sectional view showing a packaging structure according to some other embodiments of the present disclosure.
[0029] Figure 4 Schematic cross-sectional view showing a packaging structure according to some further embodiments of the present disclosure.
[0030] Figure 5 Schematic plan view showing a packaging structure according to some further embodiments of the present disclosure.
[0031] Figure 6 Schematic cross-sectional view showing a packaging structure according to some other embodiments of the present disclosure.
[0032] Figures 7 to 13 Schematic cross-sectional view showing the structure of each step in the manufacturing method of a packaging structure according to some embodiments of the present disclosure. Detailed Description of the Embodiments
[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.
[0034] Unless otherwise defined, the technical terms or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The terms "first", "second" and similar words used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Words such as "comprising" or "including" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
[0035] Chip on Wafer on Substrate (CoWoS) packaging is an advanced packaging technology that enables high-density wiring connections between multiple chips and high-speed data transmission. CoWoS packaging is a 2.5D chip packaging widely used in fields such as artificial intelligence (AI). The packaging structure includes a Chip on Wafer (CoW) module and a packaging substrate. The CoW module typically includes components such as chip assemblies, underfill layers, molding compounds, silicon interposers, and conductive terminals.
[0036] In the manufacturing process of CoWoS packaging, first, the packaging process of the CoW module is completed, and then flip chip ball grid array (FCBGA) assembly is carried out to mount the CoW module onto the packaging substrate to form a CoWoS packaging structure. For example, the CoW module can be mounted onto the packaging substrate through a soldering process.
[0037] However, during the process of soldering the CoW module to the packaging substrate, warping of the CoW module and / or the packaging substrate may occur due to high temperatures. For example, in the CoW module, there is a mismatch in the coefficient of thermal expansion between different materials such as molding compounds and chips, silicon interposers, etc., resulting in different degrees of thermal expansion of different materials at high temperatures, which in turn leads to warping of the CoW module. Moreover, with the continuous development of chip packaging technology, such as the increasing computing power of artificial intelligence chips, the size of the CoW module is getting larger. The larger the size of the CoW module, the greater its warping may be at high temperatures, and the warping in each area may be irregular, and the warping of the module may not match the warping of the substrate. When mounting the CoW module onto the packaging substrate, defects such as bridging between conductive terminals may occur due to the above warping problems, thereby affecting the packaging yield.
[0038] In this regard, embodiments of the present disclosure provide a packaging structure, which can improve packaging warpage, thereby avoiding or reducing defects such as bridging of conductive terminals due to warpage, and improving the packaging yield.
[0039] For example, embodiments of the present disclosure provide a packaging structure having a chip component area, a peripheral area, and a plurality of terminal areas, and including: an interposer having opposite first and second sides; a chip component disposed in the chip component area on the first side of the interposer and electrically connected to the interposer, and including a plurality of chips disposed at intervals; a plurality of conductive terminals disposed in the plurality of terminal areas on the second side of the interposer; and an encapsulation layer disposed on the first side of the interposer and surrounding and encapsulating the plurality of chips of the chip component, wherein the encapsulation layer has a groove extending from a surface of the encapsulation layer away from the interposer side into the encapsulation layer, the groove is located outside the chip component area and within the peripheral area.
[0040] In embodiments of the present disclosure, by providing a groove in the encapsulation layer, a discontinuous area can be formed in the encapsulation layer, so that there is a region with thermal expansion blocking in the encapsulation layer under heating conditions, thereby improving packaging warpage and avoiding or reducing the risk of defects such as bridging of conductive terminals due to packaging warpage.
[0041] Figure 1 Schematic cross-sectional views showing a packaging structure according to some embodiments of the present disclosure. Figure 2 Schematic plan views showing a packaging structure according to some embodiments of the present disclosure. For example, Figure 1 is a cross-sectional view taken along line I-I' of Figure 2 the
[0042] Referring to Figure 1 and Figure 2 In some embodiments, the packaging structure 500 includes a chip component 100, an encapsulation layer 130, an interposer 200, and conductive terminals 210. The chip component 100 and the conductive terminals 210 are disposed on opposite sides of the interposer 200 in a direction z (or a vertical direction) perpendicular to the main surface of the interposer. The packaging structure 500 has a chip component area CR, a peripheral area PR, and a plurality of terminal areas. The chip component area CR includes the area where the chip component 100 is disposed and the area overlapping with this area in the direction z; the peripheral area PR is the area outside the chip component area CR, and for example, can surround the chip component area CR in a direction x parallel to the main surface of the interposer; the terminal area includes the area where the conductive terminals 210 are disposed and the area overlapping with this area in the direction z. Each terminal area can be overlapped with one or more of the chip component area CR and the peripheral area PR. For example, most of the terminal areas are overlapped with the chip component area CR, and some terminal areas can also be overlapped with the peripheral area PR. Figure 1The direction x therein may also be referred to as the horizontal direction and includes Figure 2 the first direction D1 and the second direction D2 shown.
[0043] For example, the adapter board 200 has opposite first and second sides 200a and 200b in the direction z. The chip component 100 is disposed on the first side 200a of the adapter board 200, located within the chip component area CR, and is electrically connected to the adapter board 200. The chip component 100 may include one or more chips, for example, a plurality of chips arranged at intervals. For example, the plurality of chips may include one or more first chips 101 and one or more second chips 102. It should be understood that the number and arrangement of chips shown in the figure are only illustrative, and the present disclosure is not limited thereto.
[0044] In some embodiments, the chip component area CR includes a plurality of chip regions respectively for setting a plurality of chips and includes a chip gap area 105 between the plurality of chip regions. For example, the orthographic projections of the plurality of chips in the chip component 100 on the main surface of the adapter board and the chip gap area between adjacent chips among the plurality of chips on the main surface of the adapter board are all located within the chip component area CR. For example, the contour of the chip component area CR may be defined by the connection lines of the outer sidewalls of the plurality of chips in the chip component. The outer sidewall of a chip refers to the sidewall of the chip that does not approach or face other chips, and the inner sidewall of a chip refers to the sidewall of the chip that approaches or faces other chips. For example, the chip gap area between the plurality of chips in the chip component is the area located between the inner sidewalls of adjacent chips.
[0045] In some embodiments, the encapsulation layer 130 is disposed on the first side 200a of the adapter board 200 and surrounds the plurality of chips of the encapsulated chip component 100. For example, the encapsulation layer 130 may at least encapsulate the sidewalls of the plurality of chips (including the inner and outer sidewalls of each chip). For example, the surface of the encapsulation layer 130 away from the adapter board 200 may be substantially flush with the surface of the plurality of chips in the chip component 100 away from the adapter board 200 in the direction x parallel to the main surface of the adapter board. In some other examples, the encapsulation layer 130 may also encapsulate the surface of the chip component away from the adapter board.
[0046] For example, the encapsulation layer 130 may be disposed in the peripheral area PR and surround the outer sidewalls of the plurality of chips in the chip component 100; the encapsulation layer 130 may also be disposed in the chip component area CR, fill the chip gap area 105 between the plurality of chips, and encapsulate the inner sidewalls of the plurality of chips.
[0047] Continue to refer to Figure 1 and Figure 2, in some embodiments, the encapsulation layer 130 has one or more grooves 131 that extend from the surface of the encapsulation layer 130 on the side away from the adapter board 200 into the encapsulation layer 130. The grooves 131 are located outside the chip assembly area CR and within the peripheral area PR. For example, the grooves 131 are disposed in an area outside the outer sidewall of the chip assembly, and are spaced apart from the multiple chips and chip gaps in the chip assembly. In other words, the orthographic projection of the groove 131 on the main surface of the adapter board is located in an area outside the orthographic projection of the chip assembly 100 on the main surface of the adapter board.
[0048] In some embodiments, the orthographic projection of the chip gap area between adjacent chips among the multiple chips on the adapter board is offset from the orthographic projection of the groove on the adapter board.
[0049] For example, in the chip assembly 100, the orthographic projections of the chip gap area 105 between the adjacent first chip 101 and second chip 102, the chip gap area between adjacent first chips, and the chip gap area between adjacent second chips on the adapter board 200 are all offset from the orthographic projection of the groove 131 on the adapter board 200. That is to say, the groove 131 of the encapsulation layer 130 is not disposed in the chip gap area 105, that is, not between adjacent chips.
[0050] In some embodiments, the groove 131 is spaced apart from the chip edge of the chip assembly 100, and the chip edge may also be referred to as the outer sidewall of the chip assembly and includes the outer sidewalls of multiple chips. That is, the groove 131 does not expose the outer sidewall of the chip assembly 100. For example, as Figure 1 shown, the encapsulation layer 130 includes a first encapsulation portion 130a that covers and contacts the chip edge of the chip assembly 100, and the groove 131 is located on the side of the first encapsulation portion 130a away from the chip assembly 100 in the horizontal direction x (for example, the first direction D1) and is spaced apart from the chip edge. In this way, the chip edge can be effectively encapsulated by the encapsulation layer 130, so that the encapsulation layer 130 provides effective protection for the chip assembly 100, and damage to the chips during the formation of the groove can be avoided.
[0051] For example, the encapsulation layer 130 further includes a second encapsulation portion 130b that is located on the side of the groove 131 away from the first encapsulation portion 130a in the horizontal direction x (for example, the first direction D1), that is, the groove 131 is located between the first encapsulation portion 130a and the second encapsulation portion 130b. For example, the opposite sidewalls of the groove 131 may be defined by the opposite surfaces of the first encapsulation portion 130a and the second encapsulation portion 130b. In some embodiments, in the first direction, no other chips are disposed on the side of the second encapsulation portion 130b away from the groove 131.
[0052] In some embodiments, the encapsulation layer 130 further includes a third encapsulation portion 130c, which is located on the side of the groove 131 close to the adapter board 200 and connects the first encapsulation portion 130a and the second encapsulation portion 130b. That is to say, the groove is provided in the upper part of the encapsulation layer and does not completely disconnect the encapsulation layer, and the lower part of the encapsulation layer can still be continuous. By providing the groove 131 to form a discontinuous area in a part of the encapsulation layer, for example, the first encapsulation portion and the second encapsulation portion are spaced apart from each other by the groove, so that a thermal expansion blocking area can be generated in the encapsulation layer, which can further facilitate the improvement of the warpage of the packaging structure. In addition, the groove is only provided in the upper part of the encapsulation layer. For example, the first encapsulation portion and the second encapsulation portion are connected to each other through the third encapsulation portion, so as to ensure the structural stability of the encapsulation layer and the overall packaging.
[0053] In some embodiments, in the direction parallel to the main surface of the adapter board (for example, the horizontal direction x), the spacing distance s1 between the groove 131 and the chip edge is set to be more than 20 micrometers (μm) or more than 50 micrometers, for example, in the range of 20 micrometers to 730 micrometers, 20 micrometers to 700 micrometers, 50 micrometers to 700 micrometers or 50 micrometers to 730 micrometers. Setting the spacing distance s1 within the above range can avoid damaging the chip due to the formation of the groove, and at the same time ensure that the distance between the groove and the higher density terminal area is within an appropriate range, thereby reducing warpage.
[0054] In some embodiments, in the direction z perpendicular to the main surface of the adapter board 200, the depth h1 of the groove 131 is less than the thickness h2 of the encapsulation layer 130; for example, the depth h1 of the groove 131 can be less than or equal to 2 / 3 of the thickness h2 of the encapsulation layer 130, or the depth h1 of the groove 131 can be less than or equal to 1 / 2 of the thickness h2 of the encapsulation layer 130. Setting the groove depth within the above range can form a discontinuous area in the encapsulation layer to improve warpage while ensuring the structural stability of the encapsulation layer and the overall packaging structure.
[0055] In some embodiments, the width w1 of the groove 131 can be set in the range of 20 μm to 500 μm, for example, in the range of 25 μm to 200 μm. Setting the groove size within the above range enables the groove to have a sufficient size to improve warpage. In some embodiments, the width range of the groove is not limited to this and can be appropriately adjusted according to product design and requirements. The width of the groove refers to the width in the arrangement direction of the corresponding terminal area in the groove and the chip component, for example, in Figure 1 and 2 the example of is the width in the first direction D1.
[0056] In some embodiments, the chip component is electrically connected to the interposer through a plurality of conductive bumps, and the encapsulation structure further includes: an underfill layer that fills the space between the chip component and the interposer and surrounds the plurality of conductive bumps, wherein a portion of the underfill layer is covered by the encapsulant layer, and the groove is spaced apart from the underfill layer.
[0057] Reference Figure 1 , for example, a plurality of conductive bumps 110 are provided between the chip component 100 and the interposer 200, and one or more chips in the chip component 100 can be electrically connected to the interposer 200 through the corresponding conductive bumps 110. For example, the conductive bumps 110 may include conductive materials such as metal and / or solder, and may be or include micro-bumps.
[0058] For example, the encapsulation structure 500 may further include an underfill layer 120 that fills the space between the chip component 100 and the interposer 200 and surrounds and protects the plurality of conductive bumps 110. In some embodiments, the underfill layer 120 is covered by the encapsulant layer 130 and is spaced apart from the groove 131, that is, the groove 131 does not expose the underfill layer 120. For example, the underfill layer 120 may further extend to cover the sidewalls (including the inner sidewall and / or the outer sidewall) of the chip component 100, and the extended portion of the underfill layer 120 may extend beyond the chip component region CR and into the peripheral region PR. In some embodiments, the groove 131 of the encapsulant layer 130 does not expose the underfill layer 120, so that the sidewalls of the extended portion of the underfill layer 120 located in the peripheral region can be covered (e.g., completely covered) by the encapsulant layer 130, thus ensuring the structural stability of the overall encapsulation structure.
[0059] In some embodiments, the chip gap region 105 between the plurality of chips in the chip component may be filled with at least one of the underfill layer 120 and the encapsulant layer 130, for example, substantially completely filled. For example, in Figure 1 the example shown, the underfill layer 120 fills a portion of the chip gap region 105, and the encapsulant layer 130 fills another portion of the chip gap region 105 and covers the underfill layer 120 in the chip gap region; in other examples, the chip gap region 105 may be substantially completely filled with the underfill layer 120; for example, the surface of the underfill layer 120 away from the interposer may be substantially flush with the surfaces of the chip component and the encapsulant layer away from the interposer in a direction parallel to the main surface of the interposer. In this article, the chip gap region is completely filled means that there is no groove in the chip gap region, that is, there is no groove extending downward from the surface in the encapsulant layer and / or the underfill layer located therein, but may include acceptable small air holes or holes and the like that may be formed due to the underfill process and / or the encapsulation process in the underfill layer and / or the encapsulant layer filled therein.
[0060] Continue to refer to Figure 1 and Figure 2 In some embodiments, a plurality of conductive terminals 210 are disposed on the second side 200b of the adapter board 200 and can be electrically connected to a plurality of chips in the chip assembly 100 through the adapter board 200. For example, the conductive terminals 210 may include solder balls, such as may be or include Controlled Collapsed Chip Connection (C4) bumps. For example, the adapter board 200 has a plurality of terminal regions, and one or more conductive terminals may be disposed in each terminal region. The terminal region includes the region on the adapter board where the conductive terminals are disposed and includes the region overlapping with this region in the direction z perpendicular to the main surface of the adapter board. For example, the terminal region may be overlapped with the chip assembly region CR, or may also be overlapped with a part of the peripheral region PR. For example, the orthographic projection of the plurality of conductive terminals 210 on the main surface of the adapter board overlaps with the orthographic projection of the chip assembly 100 on the main surface of the adapter board, or may also overlap with the orthographic projection of the encapsulation layer located in the peripheral region on the main surface of the adapter board. It should be understood that in Figure 2 the top view, the conductive terminals 210 are not visible, so they are shown in dashed lines. In addition, for the simplicity of the drawings, Figure 2 only the conductive terminals in some terminal regions are shown, and the conductive terminals in all regions are not shown.
[0061] In some embodiments, in different terminal regions, the density of the conductive terminals may be different. The spacing (or center distance) between adjacent conductive terminals in the region with a lower density of conductive terminals is relatively large, while the spacing (or center distance) between adjacent conductive terminals in the region with a higher density of conductive terminals is relatively small. For the terminal region with a higher density of conductive terminals, when the package structure warps, the possibility of bridging and other defects between the conductive terminals in this region due to warping is relatively large. Therefore, such a terminal region may be referred to as a high-risk region.
[0062] In some embodiments, the grooves of the encapsulation layer may be mainly disposed near such high-risk regions to improve the warping around the high-risk regions, thereby avoiding bridging and other defects of the conductive terminals in this region. For example, in some embodiments, a higher density of conductive terminals may be disposed in the region near the chip edge, and the grooves of the encapsulation layer may be disposed at a position near the chip edge to improve the warping of this region, thereby reducing bridging and other defects of the conductive terminals in this region due to warping.
[0063] In some embodiments, the plurality of terminal regions include a first terminal region and a second terminal region, and the density of the plurality of conductive terminals in the first terminal region is greater than the density of the plurality of conductive terminals in the second terminal region; in a direction parallel to the main surface of the adapter board, a first distance between the groove and the first terminal region is less than a second distance between the groove and the second terminal region; or a facing area between the groove and the first terminal region is greater than a facing area between the groove and the second terminal region.
[0064] Reference Figure 2 , for example, the adapter board 200 has a first terminal region BR1 and a second terminal region BR2, and the density of the plurality of conductive terminals in the first terminal region BR1 is greater than the density of the plurality of conductive terminals in the second terminal region BR2. For example, the first terminal region may also be referred to as a high-density terminal region, and the second terminal region may also be referred to as a low-density terminal region. The first terminal region BR1 and the second terminal region BR2 may correspond to the same chip, or may also correspond to different chips. At least one of the first terminal region and the second terminal region may be provided in the region corresponding to each chip. It should be understood that the first terminal region and the second terminal region are only named to distinguish the relative high and low terminal densities of these regions. For example, the first terminal region generally refers to a region with a higher terminal density, and the second terminal region generally refers to a region with a lower terminal density; however, the types of conductive terminals in these regions are not limited; for example, the types of conductive terminals in the first terminal region and the second terminal region may be the same or different, the types of conductive terminals in different first terminal regions may be the same or different, and the types of conductive terminals in different second terminal regions may be the same or different. The terminal densities of different first terminal regions may be the same or different, and the terminal densities of different second terminal regions may be the same or different.
[0065] For example, the plurality of conductive terminals 210 include a plurality of first conductive terminals 210a and a plurality of second conductive terminals 210b. The plurality of first conductive terminals 210a are located in the first terminal region BR1, and the plurality of second conductive terminals 210b are located in the second terminal region BR2. In some embodiments, the density of the plurality of conductive terminals in the first terminal region BR1 being greater than the density of the plurality of conductive terminals in the second terminal region BR2 may include at least one of the following cases: the spacing between adjacent first conductive terminals 210a in the first terminal region BR1 is less than the spacing between adjacent second conductive terminals 210b in the second terminal region BR2; the pitch between adjacent first conductive terminals 210a in the first terminal region BR1 is less than the pitch between adjacent second conductive terminals 210b in the second terminal region BR2. In some examples, in the first terminal region BR1, the pitch between adjacent first conductive terminals is less than or equal to 150 micrometers. The spacing refers to the distance between the relative edges of adjacent conductive terminals; the pitch refers to the distance between the centers of adjacent conductive terminals, and is approximately equal to the sum of the spacing between adjacent conductive terminals and the width of the conductive terminal.
[0066] That is to say, the first terminal region BR1 is a high-risk region compared with the second terminal region BR2, and there may be a high risk of defects such as bridging of the first conductive terminal 210a due to package warping.
[0067] In some embodiments, the groove 131 of the encapsulation layer 130 is correspondingly arranged in the first terminal region BR1 to improve the warping of this region, thereby reducing the risk of defects such as bridging of the first conductive terminal in this region.
[0068] For example, the first terminal region and the second terminal region are arranged side by side in a first direction parallel to the main surface of the adapter board, and the first distance between the groove of the encapsulation layer and the first terminal region in the first direction is less than the second distance between the groove and the second terminal region in the first direction. For example, the groove can be arranged on one side of the first terminal region in the first direction.
[0069] For example, the first chip has a first chip edge, the first terminal region and the groove are respectively located on opposite sides of the first chip edge in the first direction within the chip component region and the peripheral region, and the second terminal region is located on the side of the first terminal region away from the first chip edge in the first direction.
[0070] For example, as Figure 2 shown, the groove 131 can be arranged near the first terminal region BR1 or directly opposite the first terminal region. For example, taking the first terminal region BR1 and the second terminal region BR2 corresponding to the first chip 101 in the upper left corner of the figure as an example, in the direction parallel to the main surface of the adapter board, the first distance d1 between the groove 131 and the first terminal region BR1 is less than the second distance d2 between the groove 131 and the second terminal region BR2. For example, the first terminal region BR1 and the second terminal region BR2 are arranged side by side in the first direction D1, and both the first distance d1 and the second distance d2 are distances in the first direction D1. For example, the groove 131 can be arranged on one side of the first terminal region BR1 in the first direction D1 and close to the first terminal region.
[0071] For example, the orthographic projections of the first terminal region BR1 and the second terminal region BR2 on the main surface of the adapter board overlap with the orthographic projection of the first chip 101 in the chip component on the main surface of the adapter board; for example, the orthographic projections of the first terminal region BR1 and the second terminal region BR2 can be located within the orthographic projection of the first chip 101. However, the present disclosure is not limited thereto. The first terminal region and the second terminal region can also correspond to other chips respectively, or can also overlap with the chip gap region.
[0072] For example, the first chip 101 has a first chip edge E1. The first terminal region BR1 and the groove 131 are both disposed near the first chip edge E1, and the second terminal region BR2 is disposed at a position relatively far from the first chip edge E1. For example, in a direction parallel to the main surface of the adapter board, the distance between the first terminal region BR1 and the first chip edge E1 is less than the distance between the second terminal region BR2 and the first chip edge E1, and the groove 131 is disposed near the first chip edge E1. For example, the first terminal region BR1 and the groove 131 are respectively disposed in the chip component region CR and the peripheral region PR, and are disposed on opposite sides of the first chip edge E1 in the first direction D1, while the second terminal region BR2 is located on the side of the first terminal region BR1 away from the first chip edge E1 in the first direction D1.
[0073] In some other embodiments, the first terminal region and the second terminal region are arranged side by side in a second direction parallel to the main surface of the adapter board. The groove is located on one side of the first terminal region and the second terminal region in a first direction intersecting the second direction, and the overlapping area of the groove and the first terminal region in the first direction is larger than the overlapping area of the groove and the second terminal region in the first direction.
[0074] For example, the first terminal region includes two opposite edges in the second direction, and the orthographic projections of the two edges on a reference plane perpendicular to the first direction overlap with the orthographic projection of the groove on the reference plane.
[0075] For example, in the second direction, the first terminal region has a first length, the groove has a second length, and the second length is greater than or equal to the first length.
[0076] For example, the orthographic projection of the first terminal region on the main surface of the adapter board overlaps with the orthographic projection of the first chip on the main surface of the adapter board, and the orthographic projection of the second terminal region on the main surface of the adapter board overlaps with the orthographic projection of the first chip or the second chip on the main surface of the adapter board. For example, the first chip is a logic chip, and the second chip is a memory chip.
[0077] Reference Figure 2, for example, the first terminal region BR1 and the second terminal region BR2 (for example, the two uppermost terminal regions in the figure) are arranged side by side in a second direction D2 parallel to the main surface of the adapter board, and the groove 131 is located on one side of the first terminal region BR1 and the second terminal region BR2 in a first direction D1 parallel to the main surface of the adapter board; for example, the first direction D1 and the second direction D2 intersect with each other, for example, are substantially perpendicular to each other. In some embodiments, the facing area of the groove 131 in the first direction D1 with the first terminal region BR1 is larger than the facing area of the groove 131 in the first direction D1 with the second terminal region BR2. Here, the facing area of the groove in a certain direction with the terminal region refers to the area where the groove overlaps with the terminal region in this direction, that is, the area of the overlapping part of the positive projection of the groove on the reference plane perpendicular to this direction and the positive projection of the terminal region on this reference plane.
[0078] For example, the first terminal region BR1 includes two opposite edges in the second direction D2, for example, a first edge e1 and a second edge e2, and both of the two edges overlap with the groove 131 in the first direction D1. For example, the positive projections of the first edge e1 and the second edge e2 on the reference plane perpendicular to the first direction D1 both overlap with the positive projection of the groove 131 on the reference plane.
[0079] For example, in the second direction D2, the first terminal region BR1 has a first length L1, and the groove 131 has a second length L2, and the second length L2 is greater than or equal to the first length L1.
[0080] In this embodiment, the first terminal region BR1 and the second terminal region BR2 can be set corresponding to the same or different chips. For example, the positive projection of the first terminal region BR1 on the main surface of the adapter board at least partially overlaps with the positive projection of the first chip 101 on the main surface of the adapter board, for example, can be located within the positive projection of the first chip 101; the positive projection of the second terminal region BR2 on the main surface of the adapter board at least partially overlaps with the positive projection of the first chip 101 or the second chip 102 on the main surface of the adapter board. For example, as Figure 2 shown, the positive projection of the second terminal region BR2 can be located within the positive projection of the second chip 102. In some other examples, a second terminal region arranged side by side with the first terminal region in the second direction can also be provided in the region corresponding to the first chip 101.
[0081] Through the above settings, the groove 131 can be made to improve the warping of the first terminal region with a relatively high terminal density and its surrounding area as much as possible, thereby reducing the occurrence of defects such as bridging of the first conductive terminals in this region due to warping.
[0082] In some embodiments, one or more first chips 101 may be or include logic chips, such as may also be referred to as main chips; one or more second chips 102 may be or include memory chips, such as may also be referred to as additional chips. In some embodiments, the first terminal region with a higher terminal density may be mainly disposed in the region corresponding to the main chip, but the present disclosure is not limited thereto.
[0083] It should be understood that Figure 2 only some terminal regions are schematically shown for illustrative purposes, and not all terminal regions are shown. The number and arrangement manner of the terminal regions in the package structure are not limited thereto.
[0084] In some embodiments, a terminal region may also be provided in the peripheral region. If a first terminal region with a higher terminal density is provided in the peripheral region, the orthographic projection of a plurality of first conductive terminals in the first terminal region on the main surface of the adapter board may overlap with the orthographic projection of the groove on the main surface of the adapter board. At this time, the first distance between the groove and the first terminal region may be zero.
[0085] In some embodiments, as Figure 2 shown in the enlarged view of region A in, a plurality of terminal regions may further include an additional terminal region BR overlapping with the peripheral region PR. For example, the additional terminal region BR may be located within the peripheral region PR, and a plurality of conductive terminals 210 may further include a plurality of additional conductive terminals 210c disposed in the additional terminal region BR on the second side of the adapter board. For example, the orthographic projection of the groove 131 on the main surface of the adapter board may overlap with the orthographic projection of the additional terminal region BR on the main surface of the adapter board.
[0086] In some embodiments, the additional conductive terminals 210c may include dummy terminals and may be used to provide structural support for the adapter board. For example, the dummy terminals may be electrically floating.
[0087] Figure 3 Fig. shows a schematic cross-sectional view of a package structure according to other embodiments of the present disclosure.
[0088] In some embodiments, the package structure further includes an additional filling layer filled in the groove of the encapsulation layer, and the coefficient of thermal expansion of the additional filling layer is less than the coefficient of thermal expansion of the encapsulation layer.
[0089] Reference Figure 3, for example, the encapsulation structure 500 further includes an additional filling layer 132 filled in the groove 131 of the encapsulation layer 130, and the coefficient of thermal expansion of the additional filling layer 132 is less than that of the encapsulation layer 130. For example, the coefficient of thermal expansion of the encapsulation layer 130 is greater than that of the chip component 100, and the coefficient of thermal expansion of the additional filling layer 132 can be within the range between the coefficient of thermal expansion of the chip component 100 and that of the encapsulation layer 130. Providing an additional filling layer with a coefficient of thermal expansion less than that of the encapsulation layer can also be beneficial for improving encapsulation warpage.
[0090] In some embodiments, the surface of the additional filling layer 132 on the side away from the interposer may be substantially flush with the surface of the encapsulation layer 130 on the side away from the interposer in a direction parallel to the main surface of the interposer, but the present disclosure is not limited thereto.
[0091] Figure 4 Schematic cross-sectional view showing an encapsulation structure according to some other embodiments of the present disclosure. Figure 5 Schematic plan view showing an encapsulation structure according to some other embodiments of the present disclosure.
[0092] In some other embodiments, the encapsulation structure further includes an encapsulation substrate disposed on the side of the interposer away from the chip component and electrically connected to the interposer through a plurality of conductive terminals.
[0093] For example, Figure 1 the illustrated encapsulation structure may also be referred to as a CoW package, and the CoW package may be further mounted on an encapsulation substrate. Refer to Figure 4 and Figure 5 , for example, the encapsulation structure 500 further includes an encapsulation substrate 300 disposed on the side of the interposer 200 away from the chip component 100 and electrically connected to the interposer 200 through a plurality of conductive terminals 210.
[0094] In some embodiments, the encapsulation structure 500 may further include a strengthening structure 301, an additional device 302, and a conductive connection member 310. The strengthening structure 301 and the CoW package are disposed on the same side of the encapsulation substrate 300. For example, the strengthening structure 301 is disposed on the edge of the encapsulation substrate 300 and can be attached to the encapsulation substrate 300 through an adhesive layer. The CoW package may be located in an area surrounded by the strengthening structure 301 in a direction parallel to the main surface of the encapsulation substrate. The strengthening structure 301 can be beneficial for controlling and reducing the warpage of the encapsulation substrate and the overall encapsulation structure. In some embodiments, as Figure 4 and Figure 5 shown, the strengthening structure 301 can be a strengthening ring; in alternative embodiments, the strengthening structure 301 can also adopt a strengthening cover, that is, it may further include a cover portion on the side of the chip component away from the interposer.
[0095] For example, one or more additional devices 302 may be provided on one side or opposite sides of the encapsulation substrate 300; the additional device 302 may include a capacitor or the like. For example, the conductive connection member 310 is disposed on a side of the encapsulation substrate 300 away from the adapter board 200, and can be used to further connect the encapsulation structure 500 to other encapsulation components, such as a printed circuit board. For example, the conductive connection member 310 may be or include a ball grid array (BGA).
[0096] Figure 6 Shows an encapsulation structure according to some other embodiments of the present disclosure.
[0097] Reference Figure 6 , for example, the encapsulation structure 500 may further include a heat dissipation member 160, the heat dissipation member 160 is disposed on a side of the chip component 100 and the encapsulation layer 130 away from the adapter board 200, and can be attached to the chip component 100 through the thermal interface material layer 150. For example, the thermal interface material layer 150 is disposed between the heat dissipation member 160 and the chip component 100, or may also be disposed between the heat dissipation member 160 and the encapsulation layer 130; a part of the thermal interface material layer 150 may be filled into the groove 131; for example, the said part of the thermal interface material layer 150 may be surrounded by the encapsulation layer 130.
[0098] Figures 7 to 13 Shows a schematic cross-sectional view of the structure of each step in the manufacturing method of the encapsulation structure according to some embodiments of the present disclosure.
[0099] Reference Figure 7 , in some embodiments, the chip component 100 is mounted (e.g., flip-chip mounted) to the first side 200a of the adapter board 200. The chip component 100 may include a plurality of chips spaced apart on the adapter board 200. For example, the plurality of chips may be bonded to the adapter board 200 through the conductive bumps 110.
[0100] For example, each chip in the chip component 100 may include a chip substrate, a device layer, and conductive connectors, etc.; the chip substrate is a semiconductor substrate, and may be or include a silicon substrate, or may also include other semiconductor materials such as germanium; the device layer is disposed on one side of the chip substrate, and may include active devices (e.g., transistors), passive devices (e.g., capacitors, inductors, etc.) or a combination thereof and a chip interconnect structure, and each device can be connected through the chip interconnect structure; the conductive connector is located on the side of the device layer away from the substrate and can be electrically connected to various devices on the chip substrate through the chip interconnect structure; the conductive connector serves as an external connection point of the chip for providing an electrical connection between the chip and other components (e.g., an interposer). The side of the chip close to the device layer (e.g., the side with the conductive connector) can be referred to as the front side or the active side of the chip, and the side where the substrate of the chip is located (i.e., the side opposite to the front side) can be referred to as the back side. For example, each chip can be flip-chip mounted on the interposer such that its front side faces the interposer.
[0101] For example, multiple chips in the chip component may include chips of the same type or different types. The number and type of chips can be selected according to product requirements; for example, the multiple chips of the chip component 100 may include one or more of a system on chip (SoC), a digital signal processor (DSP) chip, a graphic processing unit (GPU), an application specific integrated circuit (ASIC) chip, a memory chip such as a high bandwidth memory (HBM) chip, a central processing unit (CPU), a tensor processing unit (TPU), a neural network processing unit (NPU), a deep learning processing unit (DPU), an accelerated processing unit (APU), a general-purpose computing on graphics processing unit (GPGPU), and a chiplet.
[0102] In some embodiments, the chip assembly 100 includes a first chip 101 and a second chip 102. The first chip 101 may be a logic chip, such as a SoC. The second chip 102 may be a memory chip, such as an HBM.
[0103] For example, the interposer 200 may be a silicon-based interposer and includes a substrate 201, an interconnect structure 202, and substrate vias 203. The substrate 201 may be or include a semiconductor substrate such as a silicon substrate. Substrate vias (TSVs) 203 are provided in the substrate 201 to provide electrical connections between conductive members on opposite sides of the substrate. For example, the interconnect structure 202 includes an inorganic dielectric structure and a conductive structure (not shown). The inorganic dielectric structure may be a single-layer or multi-layer structure and may include inorganic dielectric materials such as silicon oxide and silicon nitride. The conductive structure is embedded in the inorganic dielectric structure and may include one or more layers of conductive traces and conductive vias. The conductive structure is electrically connected to the substrate vias and is used to provide electrical connections between multiple chips in the chip assembly and between the chip assembly and the conductive terminals.
[0104] After the chip assembly 100 is bonded to the interposer 200, an underfill layer 120 may be formed through an underfill process, which may include a dispensing process. The underfill layer 120 fills the space between each chip and the interposer 200 and surrounds and protects the conductive bumps 110. In some embodiments, the underfill layer 120 may further extend to cover the sidewalls of the multiple chips, for example, may fill the chip gap region 105 between the multiple chips. The underfill layer may include an organic material such as epoxy resin.
[0105] In some embodiments, a plurality of conductive terminals 210 are formed on the second side 200b of the interposer 200.
[0106] Continuing to refer to Figure 7 , a carrier 60 is provided. The carrier 60 may be a glass carrier or the like that can provide support for structures to be placed above it and will be removed in subsequent processes, so it may also be referred to as a temporary carrier.
[0107] The structure including the interposer 200, the chip assembly 100, and the conductive terminals 210 is placed on the carrier 60. For example, the structure may be mounted on the carrier 60 through an adhesive layer 61. The adhesive layer 61 may be or include a temporary bonding and debonding (TBDB) layer and can be used to bond the above structure including the interposer to the carrier in this step and can be used to detach the interposer and the structures above it from the carrier 60 in subsequent steps. In some embodiments, after being attached to the carrier 60, the conductive terminals 210 may be embedded in the adhesive layer 61.
[0108] Reference Figure 8 On the first side 200a of the adapter board 200, an encapsulation layer 130 is formed to encapsulate the chip component 100 and the underfill layer 120. For example, the encapsulation layer 130 may include a molding compound, such as an epoxy molding compound (EMC), and may be formed by a molding process. The encapsulation layer 130 may include a matrix material and a filler; the matrix material may include organic materials such as epoxy resin; the filler is dispersed in the organic material and may include semiconductor materials, inorganic insulating materials, etc., for example, may include silicon, alumina, etc. For example, in this step, the encapsulation layer 130 encapsulates the sidewalls of the chip component and the underfill layer, and the height of the encapsulation layer 130 relative to the main surface of the adapter board in a direction perpendicular to the adapter board is greater than the height of the chip component 100 relative to the main surface of the adapter board, so that the surface of the chip component 100 on the side away from the adapter board is also encapsulated by the encapsulation layer 130.
[0109] Reference Figure 8 And Figure 9 A planarization process is performed to remove the portion of the encapsulation layer 130 located above the chip component and expose the surface of the chip component 100 on the side away from the adapter board. The planarization process may include a grinding process, such as a chemical mechanical polishing (CMP) process.
[0110] Reference Figure 10 And Figure 11 A grooving process is performed to form a groove 131 in the encapsulation layer 130. For example, the grooving process may be or include a laser grooving process, and a laser source 70 may be used to irradiate a laser beam onto the area of the encapsulation layer where the groove is to be formed to remove a portion of the encapsulation layer and form the groove 131. In some embodiments, the size of the chip gap region between adjacent chips in the chip component may be set to be relatively small, which may be beneficial to reducing the interconnection distance between chips; in order to avoid damaging the chips during the grooving process, the groove may not be provided in the chip gap region. For example, the groove 131 is provided in a peripheral region outside the chip component region, and the groove 131 is spaced a certain distance from the chip edge, thereby avoiding damaging the chips during the grooving process.
[0111] Reference Figure 11 And Figure 12, the carrier board 60 and the adhesive layer 61 are removed, and the second side of the adapter board 200 and the conductive terminals 210 are exposed. For example, the adhesive layer 61 can be irradiated with laser or ultraviolet (UV) light, etc., so that the adhesive layer 61 loses its adhesiveness under light irradiation, so that the adhesive layer 61 and the carrier board 60 can be detached from the overlying structures such as the adapter board 200. Refer to Figure 12 , a packaging structure (or called CoW packaging) including the adapter board 200, the chip component 100, and the encapsulation layer 130 is formed.
[0112] Refer to Figure 13 , the Figure 12 shown CoW packaging is mounted on the packaging substrate 300; for example, the CoW packaging can be bonded to the packaging substrate 300 through the conductive terminals 210; the bonding process can include a soldering process. In some embodiments, during the process of bonding the CoW packaging to the packaging substrate 300, thermal expansion of various materials may occur due to high temperature. Since grooves are provided in the encapsulation layer 130, discontinuous regions are formed in the encapsulation layer, thereby blocking the thermal expansion of the encapsulation material in some regions. For example, the thermal expansion difference between the encapsulation layer and other materials can be reduced, which is beneficial to improving the packaging warpage caused by the mismatch of the thermal expansion coefficients of various materials, and further avoiding defects such as bridging of the conductive terminals due to packaging warpage; in some embodiments, since the grooves are provided near the dense terminal area with high risk, the warpage is controllable in the risk area. For example, the warpage in this area can be significantly improved and / or the warpage in this area can be more adapted to the substrate warpage, thereby avoiding or reducing the risk of defects such as bridging of the conductive terminals in this area, reducing the yield loss caused by bridging, and further improving the packaging yield.
[0113] In some embodiments, after the CoW packaging is mounted on the packaging substrate 300, a bottom filling material layer 220 can be formed through a bottom filling process to fill the space between the adapter board 200 and the packaging substrate 300 and surround the plurality of conductive terminals 210.
[0114] In some embodiments, components such as a strengthening structure 301, an additional device 302, and a conductive connection member 310 can be provided on the packaging substrate 300.
[0115] It should be understood that the number and shape of the grooves in the encapsulation layer shown in the figure are only illustrative, and the present disclosure is not limited thereto. For example, the number and shape of the grooves can be adjusted according to chip design and requirements.
[0116] In various embodiments of the present disclosure, by forming grooves in the encapsulation layer, the packaging warpage can be improved, thereby avoiding defects such as bridging of the conductive terminals due to warpage, and further improving the packaging yield and device reliability.
[0117] The following points need to be explained:
[0118] (1)In the accompanying drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.
[0119] (2)Without conflict, the features in the same embodiment and different embodiments of the present disclosure can be combined with each other.
[0120] The above are only the specific implementation manners of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims
1. A packaging structure, characterized in that: It has a chip component area, a peripheral area and a plurality of terminal areas, and includes: an adapter plate having opposing first and second sides; A chip assembly is disposed in the chip assembly area on the first side of the adapter board, is electrically connected to the adapter board, and includes a plurality of chips disposed at intervals; a plurality of conductive terminals, disposed in the plurality of terminal areas on the second side of the adapter board; and an encapsulation layer, disposed on the first side of the adapter plate and surrounding and encapsulating the plurality of chips of the chip assembly, The encapsulation layer has a groove extending from a surface of the encapsulation layer away from the transfer board to the encapsulation layer, and the groove is located outside the chip component area and within the peripheral area.
2. The packaging structure according to claim 1, characterized in that: An orthographic projection of a chip gap area between adjacent chips among the plurality of chips on the transfer board is staggered from an orthographic projection of the groove on the transfer board.
3. The packaging structure according to claim 1, characterized in that: The encapsulation layer includes a first encapsulation portion covering and contacting a chip edge of the chip assembly, and the groove is located on a side of the first encapsulation portion away from the chip assembly in a horizontal direction parallel to the main surface of the adapter plate and is spaced apart from the chip edge.
4. The packaging structure according to claim 3, characterized in that: The encapsulation layer further includes a second encapsulation portion located at a side of the groove away from the first encapsulation portion in the horizontal direction, and opposite side walls of the groove are defined by opposite surfaces of the first encapsulation portion and the second encapsulation portion.
5. The packaging structure according to claim 3, characterized in that: The distance between the groove and the edge of the chip in the horizontal direction is 20 micrometers to 730 micrometers. 6 . The packaging structure according to claim 1 , wherein in a direction perpendicular to a main surface of the interposer, a depth of the groove is smaller than a thickness of the encapsulation layer.
7. The packaging structure according to claim 6, characterized in that: The depth of the groove is less than or equal to 2 / 3 of the thickness of the encapsulation layer.
8. The packaging structure according to claim 1, characterized in that: The chip component is electrically connected to the adapter board through a plurality of conductive bumps, and the packaging structure further includes: a bottom filling layer, which fills the space between the chip component and the adapter board and surrounds the plurality of conductive bumps, wherein the bottom filling layer is covered by the encapsulation layer and is spaced apart from the groove.
9. The packaging structure according to claim 1, characterized in that: The plurality of terminal areas include a first terminal area and a second terminal area, wherein the density of the plurality of conductive terminals in the first terminal area is greater than the density of the plurality of conductive terminals in the second terminal area; In a direction parallel to the main surface of the adapter board, a first distance between the groove and the first terminal area is smaller than a second distance between the groove and the second terminal area; or an area facing the groove and the first terminal area is larger than an area facing the groove and the second terminal area.
10. The packaging structure according to claim 9, characterized in that: The first terminal area and the second terminal area are arranged side by side in a first direction parallel to the main surface of the adapter board, and the first distance and the second distance are both distances in the first direction.
11. The packaging structure according to claim 10, characterized in that: The chip component includes a first chip, and the first chip has a first chip edge, the first terminal area and the groove are located on opposite sides of the first chip edge in the chip component area and the peripheral area in the first direction, respectively, and the second terminal area is located on a side of the first terminal area away from the first chip edge in the first direction.
12. The packaging structure according to claim 9, characterized in that: The first terminal area and the second terminal area are arranged side by side in a second direction parallel to the main surface of the adapter board, the groove is located on one side of the first terminal area and the second terminal area in a first direction intersecting with the second direction, and the area of the groove facing the first terminal area in the first direction is larger than the area of the groove facing the second terminal area in the first direction.
13. The packaging structure according to claim 12, characterized in that: The first terminal area includes two edges opposite to each other in the second direction, and orthographic projections of the two edges on a reference plane perpendicular to the first direction overlap with an orthographic projection of the groove on the reference plane.
14. The packaging structure according to claim 13, characterized in that: In the second direction, the first terminal area has a first length, the groove has a second length, and the second length is greater than or equal to the first length.
15. The packaging structure according to any one of claims 12 to 14, characterized in that: The chip assembly includes a first chip and a second chip, the orthographic projection of the first terminal area on the main surface of the adapter board overlaps with the orthographic projection of the first chip on the main surface of the adapter board, and the orthographic projection of the second terminal area on the main surface of the adapter board overlaps with the orthographic projection of the first chip or the second chip on the main surface of the adapter board.
16. The packaging structure according to claim 15, characterized in that: The first chip is a logic chip, and the second chip is a memory chip.
17. The packaging structure according to any one of claims 1 to 14, characterized in that: The plurality of terminal areas further include an additional terminal area, the additional terminal area is located in the peripheral area, and a plurality of additional terminals are arranged in the additional terminal area on the second side of the adapter board; and An orthographic projection of the groove on the main surface of the transfer board overlaps with an orthographic projection of the additional terminal area on the main surface of the transfer board.
18. The packaging structure according to claim 17, characterized in that: The plurality of additional terminals include dummy terminals.
19. The packaging structure according to any one of claims 1 to 14, characterized in that: Also includes: An additional filling layer is filled in the groove of the encapsulation layer, and the thermal expansion coefficient of the additional filling layer is smaller than the thermal expansion coefficient of the encapsulation layer.
20. The packaging structure according to any one of claims 1 to 14, characterized in that: Also includes: The packaging substrate is arranged on a side of the adapter board away from the chip assembly and is electrically connected to the adapter board through the multiple conductive terminals.
21. The packaging structure according to any one of claims 1 to 14, characterized in that: Also includes: A heat dissipation component, disposed on a side of the chip assembly and the encapsulation layer away from the adapter plate; as well as The thermal interface material layer is arranged between the heat dissipation component and the chip assembly, and a portion of the thermal interface material layer is filled into the groove.