Semiconductor package

Abstract

The embodiment of the utility model provides a semiconductor packaging piece which comprises a first intermediary, a first semiconductor tube core on the first intermediary, a second intermediary on the first semiconductor tube core and a second semiconductor tube core on the second intermediary. The second interposer may be between the first semiconductor die and the second semiconductor die. The first semiconductor die may be bonded to the first interposer by a metal-to-metal bond and a dielectric-to-dielectric bond. The second semiconductor die may be bonded to the second interposer by a metal-to-metal bond and a dielectric-to-dielectric bond. Bonding mechanisms between the integrated circuit die and the interposer allow for a greater density of conductive features that electrically connect the integrated circuit die to the interposer. The interposer may reduce die-to-die routing distances between the integrated circuit dies, improving signal integrity, power integrity, and overall performance of the semiconductor package during operation.

Description

Technical Field

[0001] An embodiment of the present utility model relates to a semiconductor package, and particularly to a semiconductor package including a plurality of interposers. Background Art

[0002] The formation of an integrated circuit includes forming integrated circuit devices on a semiconductor wafer and then dicing the semiconductor wafer into device dies. The device dies can be bonded to a packaging component such as an interposer, a packaging substrate, a printed circuit board, etc. To protect the device dies and the bonding structure that bonds the device dies to the packaging component, an encapsulant such as a molding compound, an underfill, or the like can be used to encapsulate the device dies. Summary of the Utility Model

[0003] An embodiment of the present utility model provides a semiconductor package including: a first interposer, a first semiconductor die including a first substrate and a first bonding layer on a first side of the first substrate, a second interposer on a second side of the first substrate, and a second semiconductor die including a second substrate and a second bonding layer on a first side of the second substrate. A plurality of first bonding pads are disposed in the first bonding layer, and wherein the first bonding layer and the first bonding pads are bonded to the first interposer by metal-to-metal bonding and dielectric-to-dielectric bonding. The second side of the first substrate is opposite to the first side of the first substrate. A plurality of second bonding pads are disposed in the second bonding layer, wherein the second bonding layer and the second bonding pads are bonded to the second interposer by metal-to-metal bonding and dielectric-to-dielectric bonding, and wherein the second interposer is between the first semiconductor die and the second semiconductor die.

[0004] An embodiment of the present utility model provides a semiconductor package, comprising: a package substrate, a first interposer, a first semiconductor die, a first encapsulant along a sidewall of the first semiconductor die, a second interposer, a second semiconductor die, a second encapsulant along a sidewall of the second semiconductor die, and a carrier on the second semiconductor die and the second encapsulant. A first side of the first interposer is bonded to the package substrate. The first semiconductor die is bonded to a second side of the first interposer, and the second side of the first interposer is opposite to the first side of the first interposer, wherein the first semiconductor die is bonded to the first interposer by metal-to-metal bonding and dielectric-to-dielectric bonding. A first side of the second interposer is in contact with the first semiconductor die and the first encapsulant, and the first semiconductor die is between the first interposer and the second interposer. The second semiconductor die is bonded to a second side of the second interposer, and the second side of the second interposer is opposite to the first side of the second interposer, wherein the second semiconductor die is bonded to the second interposer by metal-to-metal bonding and dielectric-to-dielectric bonding.

[0005] Based on the above, the bonding mechanism between the integrated circuit die and the interposer allows for a greater density of electrical connection of the integrated circuit die to the conductive features of the interposer. In addition, the interposer can reduce the die-to-die wiring distance between the integrated circuit dies. Therefore, the signal integrity, power integrity, and overall performance of the semiconductor package during operation can be improved.

[0006] To make the above features and advantages of the embodiments of the present utility model more obvious and understandable, the following specific embodiments are given and described in detail in conjunction with the accompanying drawings. Description of the Drawings

[0007] Figure 1 、 2 Figures 3, 4, 5, 6, 7, 8, 9, and 10 show cross-sectional views of intermediate stages of manufacturing a semiconductor package according to some embodiments.

[0008] Figure 11 and Figure 12 show cross-sectional views of various semiconductor packages according to some embodiments.

[0009] Description of the Reference Numerals

[0010] 10: First carrier; 50: Bottom interposer; 52, 56, 60, 61, 152, 156, 160, 161: Dielectric layers; 54, 58, 62, 154, 158, 162: Conductive features; 100: Bottom integrated circuit die; 102, 202: Semiconductor substrates; 104, 204: Interconnection structures; 105: Via; 106, 206, 212, 252: Bonding layers; 108, 208: Die connectors; 110: Bottom gap fill layer; 112: Through hole; 120: Bridge die; 150: Top interposer; 200: Top integrated circuit die; 210: Top gap fill layer; 250: Second carrier; 254, 308: Electrical connectors; 256: Integrated passive components; 258: Tape; 260: Frame; 262: Saw street; 280: Wafer structure; 280': Integrated circuit package component; 300: Package substrate; 304, 306: Bonding pads; 310: Underfill; 400, 402, 404: Semiconductor packages; P1, P2: Pitch; T1, T2, T3: Thickness. Detailed description of the embodiments

[0011] The following disclosure provides numerous different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the scope of the present disclosure. For example, in the following description, the formation of a first feature "on" or "above" a second feature may include embodiments where the first feature and the second feature are formed in direct contact, and may also include embodiments where additional features are formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, the present disclosure may reuse component numbers and / or letters in various examples. Such reuse is for the purpose of simplifying and clearly describing the present disclosure and is not intended to define the relationship between various embodiments and / or configurations.

[0012] Furthermore, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one component or feature shown in the figures to another (other) component or feature. In addition to the orientation depicted in the figures, the spatially relative terms also encompass different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used may be interpreted in the same manner.

[0013] Provided is a semiconductor package and a method of forming the same, the semiconductor package having a plurality of interposers and one or more dies on each interposer. According to some embodiments, one or more bottom integrated circuit dies are bonded and electrically connected to a bottom interposer by dielectric-to-dielectric and metal-to-metal bonding. A top interposer is disposed on the bottom integrated circuit dies and is electrically connected to the bottom integrated circuit dies, and one or more top integrated circuit dies are bonded and electrically connected to the top interposer by dielectric-to-dielectric and metal-to-metal bonding. The bonding mechanism between the integrated circuit dies and the interposer may allow for a greater density of conductive features for electrically connecting the integrated circuit dies to the interposer. In addition, the interposer may reduce the die-to-die routing distance between the integrated circuit dies. Accordingly, the signal integrity, power integrity, and overall performance of the semiconductor package during operation may be improved.

[0014] Figure 1 Shown is a bottom interposer 50, which may be a build-up interposer formed on a first carrier 10. The bottom interposer 50 may be bonded to integrated circuit dies in a subsequent process. Accordingly, the integrated circuit dies may be electrically connected to each other through the bottom interposer 50. The first carrier 10 may be a semiconductor carrier, a glass carrier, a ceramic carrier, etc. The first carrier 10 may have a circular top view shape and may have the size of a silicon wafer. The bottom interposer 50 may include one or more dielectric layers and corresponding conductive features in the one or more dielectric layers. In Figure 1 the illustrated embodiment, the bottom interposer 50 includes a dielectric layer 52, a dielectric layer 56 on the dielectric layer 52, a dielectric layer 60 on the dielectric layer 56, and a dielectric layer 61 on the dielectric layer 60. The bottom interposer 50 further includes conductive features 54 in the dielectric layer 52 and the dielectric layer 56, conductive features 58 in the dielectric layer 56 and the dielectric layer 60, and conductive features 62 in the dielectric layer 60 and the dielectric layer 61. Figure 1 The bottom interposer 50 shown as having four dielectric layers is an example. In some embodiments, the bottom interposer 50 has fewer or more than four dielectric layers.

[0015] The conductive features 54 and the conductive features 58 may be redistribution lines and may include via portions and line portions. The via portion of the conductive feature 58 may be in direct contact with and electrically connected to the line portion of the conductive feature 54. The conductive features 62 may be bonding pads. Some of the conductive features 62 may include via portions and pad portions. The via portion of the conductive feature 62 may be in direct contact with and electrically connected to the line portion of the conductive feature 58. Some of the conductive features 62 may include pad portions without via portions and may be dummy bonding pads that are electrically isolated from the circuit of the bottom interposer 50.

[0016] The dielectric layer 61 can be a bonding layer and the pad portion of the conductive feature 62 can be a bonding pad, which can be bonded to an integrated circuit die in a subsequent process. Suitable materials for the dielectric layer 61 and the conductive feature 62 can be selected to be bonded to an integrated circuit die in a subsequent process. In some embodiments, the dielectric layers of the bottom interposer 50 include the same or similar dielectric materials, such as inorganic dielectric materials (e.g., silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, or the like). In some embodiments, the conductive features of the bottom interposer 50 include the same or similar conductive materials, such as aluminum, nickel, copper, titanium, tungsten, etc.

[0017] Each dielectric layer in the bottom interposer 50 can be formed by a suitable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. Each layer in the conductive features of the bottom interposer 50 can be formed by a damascene process, such as a single damascene process, a dual damascene process, etc. After the conductive feature 62 is formed in the dielectric layer 61 and the dielectric layer 60, a planarization process can be performed on the top surface of the conductive feature 62 and the dielectric layer 61. Thus, the top surfaces of the conductive feature 62 and the dielectric layer 61 are generally coplanar or flush within the process variation range. The planarization process can be chemical-mechanical polish (CMP), grinding process, etching back process, a combination thereof, etc. The pad portion of the conductive feature 62 can be used for bonding with an integrated circuit die in a subsequent process and can have a pitch P1 of less than about 10 μm. A small value of the pitch P1 can correspond to a high density of the conductive feature 62, which can improve the signal integrity, power integrity, and overall performance of the entire semiconductor package during operation.

[0018] In Figure 2In this case, the bottom integrated circuit die 100 is bonded to the bottom interposer 50. Each bottom integrated circuit die 100 can be a logic die (such as a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (such as a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a high bandwidth memory (HBM) die, etc.), a power management die (such as a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (such as a digital signal processing (DSP) die), a front-end die (such as an analog front-end (AFE) die), a deep trench capacitor (DTS) die, the like, or a combination thereof).

[0019] Each bottom integrated circuit die 100 may have a semiconductor substrate 102, such as the active layer of a doped or undoped silicon or semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 102 may include other semiconductor materials, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or a combination thereof. Other materials (such as multi-layer or gradient materials) may also be used for the semiconductor substrate 102. The semiconductor substrate 102 may have an active surface (such as Figure 2 the downward-facing surface in this case) and a non-active surface (such as Figure 2 the upward-facing surface in this case) that can be referred to as the back side. The front side of the semiconductor substrate 102 may correspond to the active side or the front side of the bottom integrated circuit die 100.

[0020] A device (not shown separately) may be disposed at the active surface of the semiconductor substrate 102. The device may be an active device (e.g., a transistor, a diode, etc.), a capacitor, a resistor, etc. The interconnect structure 104 may be disposed over the active surface of the semiconductor substrate 102. The interconnect structure 104 may be interconnected with the device to form an integrated circuit. The interconnect structure 104 may include a metallization pattern (not shown separately) in a dielectric layer (not shown separately). The dielectric layer may be a low dielectric constant dielectric layer. The metallization pattern may include metal lines and vias, which may be formed in the dielectric layer by a damascene process (e.g., a single damascene process, a dual damascene process, etc.). The metallization pattern may be formed of a suitable conductive material (e.g., copper, tungsten, aluminum, silver, gold, combinations thereof, etc.). The metallization pattern may be electrically connected to the device. The via hole 105 may be disposed in the semiconductor substrate 102. The via hole 105 may be electrically connected to the metallization pattern of the interconnect structure 104. The semiconductor substrate 102 may be thinned in a subsequent process to expose the via hole 105 at the non-active surface of the semiconductor substrate 102. After the thinning process, the via hole 105 may be a through-substrate via (TSV), e.g., a through-silicon via.

[0021] The bonding layer 106 may be disposed on the interconnect structure 104 at the front side of each bottom integrated circuit die 100. The bonding layer 106 may be formed of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride, etc. In some embodiments, the bonding layer 106 of the bottom integrated circuit die 100 and the dielectric layer 61 of the bottom interposer 50 include the same material. The bonding layer 106 may be formed by a suitable deposition process, such as CVD, ALD, etc. One or more passivation layers (not shown separately) may be disposed between the bonding layer 106 and the interconnect structure 104. The die connector 108 may extend through the bonding layer 106. The die connector 108 may include a conductive pillar, a pad, or the like for external connection thereto. In some embodiments, the die connector 108 includes a bonding pad at the front side of the bottom integrated circuit die 100 and a via hole connecting the bonding pad to the metallization pattern of the interconnect structure 104. The die connector 108 (including the bonding pad and the via hole) may be formed by a damascene process, such as a single damascene process, a dual damascene process, etc. The die connector 108 may be formed of a conductive material, such as aluminum, nickel, copper, titanium, tungsten, etc. In some embodiments, the die connector 108 and the conductive feature 62 contain the same material.

[0022] The bottom integrated circuit die 100 can be placed by utilizing a pick-and-place process or the like, and then the bottom integrated circuit die 100 can be bonded to the bottom interposer 50 by bonding the bottom integrated circuit die 100 to the dielectric layer 61 and some conductive features 62. The bonding layer 106 of the bottom integrated circuit die 100 can be directly bonded to the dielectric layer 61 by dielectric-to-dielectric bonding, and the die connectors 108 of the bottom integrated circuit die 100 can be directly bonded to the corresponding conductive features 62 by metal-to-metal bonding.

[0023] The bonding can include pre-bonding and annealing. During pre-bonding, a small pressure can be applied to press the bottom integrated circuit die 100 against the bottom interposer 50. The pre-bonding can be performed at a low temperature (e.g., room temperature). After pre-bonding, the bonding layer 106 can be bonded to the dielectric layer 61. Then, the bonding strength can be increased in a subsequent annealing step at a higher temperature. After annealing, a direct bond, such as a dielectric-to-dielectric bond, can be formed between the bonding layer 106 and the dielectric layer 61. The die connectors 108 can be bonded to the conductive features 62 in a one-to-one manner. After pre-bonding, the die connectors 108 can be in direct contact with the conductive features 62, or can expand during annealing to be in direct contact with the conductive features 62. In addition, during annealing, the material of the die connectors 108 can be mixed or bonded with the material of the conductive features 62, thereby forming a metal-to-metal bond.

[0024] In Figure 3 it, a bottom gap-fill layer 110 is formed on the bottom interposer 50 around the bottom integrated circuit die 100, vias 112 are formed on the bottom interposer 50 and pass through the bottom gap-fill layer 110, and the semiconductor substrate 102 of the bottom integrated circuit die 100 is thinned to expose the vias 105. The bottom gap-fill layer 110 can also be referred to as an encapsulant. The bottom gap-fill layer 110 can be along the sidewalls of the bottom integrated circuit die 100. The bottom gap-fill layer 110 can be formed of a dielectric material. In some embodiments, the dielectric material of the bottom gap-fill layer 110 includes an inorganic dielectric material, such as a silicon-based dielectric material (e.g., silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or the like), which can be formed by suitable deposition processes such as CVD, ALD, etc. In some embodiments, the dielectric material of the bottom gap-fill layer 110 includes an organic dielectric material, such as a polymer-based dielectric material (e.g., molding compound, epoxy resin, resin, or the like), which can be formed by suitable molding processes such as compression molding, transfer molding, etc. Initially, the bottom gap-fill layer 110 can cover the backside of the bottom integrated circuit die 100. A first thinning process can be performed to remove the excess bottom gap-fill layer 110 and a portion of the semiconductor substrate 102 to expose the vias 105. The first thinning process can be a CMP process, a grinding process, an etch-back process, a combination thereof, etc.

[0025] The vias 112 are formed through the bottom gap-fill layer 110 to make direct contact and electrical connection with some of the conductive features 62 of the bottom interposer 50 that are not covered by the bottom integrated circuit die 100. The vias 112 can be formed of one or more layers of a conductive material (such as aluminum, nickel, copper, titanium, tungsten, etc.) and can be formed by a damascene process (such as a single damascene process, a dual damascene process, etc.), and can include various barrier layers, liner layers, etc. An embodiment is provided where the bottom gap-fill layer 110 is formed before the vias 112. In other embodiments, the bottom gap-fill layer 110 is formed after the vias 112. A second thinning process can be performed to planarize the surface of the bottom gap-fill layer 110, the surface of the vias 112, and the back side of the bottom integrated circuit die 100. The second thinning process can be CMP, a grinding process, an etch-back process, a combination thereof, etc. After the second thinning process, the surfaces of the bottom gap-fill layer 110, the vias 112, the semiconductor substrate 102, and the vias 105 are substantially coplanar or flush within the process variation range. An embodiment is provided where a portion of the semiconductor substrate 102 is removed during the first thinning process to expose the vias 105. In other embodiments, a portion of the semiconductor substrate 102 is removed during the second thinning process to expose the vias 105. The bottom gap-fill layer 110 and the bottom integrated circuit die 100 can have the same thickness T1 in the range of about 15 μm to about 30 μm.

[0026] In Figure 4 this, a top interposer 150 (which can be an interposer build-up) is formed on the bottom integrated circuit die 100, the vias 112, and the bottom gap-fill layer 110. The bottom side of the top interposer 150 can be electrically connected to the bottom integrated circuit die 100 and the vias 112. The top side of the top interposer 150 can be bonded to other integrated circuit dies in a subsequent process. Thus, the integrated circuit dies on both sides of the top interposer 150 are electrically connected to each other through the top interposer 150, and the top interposer 150 and the bottom interposer 50 are electrically connected through the bottom integrated circuit die 100 and the vias 112. The top interposer 150 can include one or more dielectric layers and corresponding conductive features in the one or more dielectric layers. In Figure 4 the illustrated embodiment, the top interposer 150 includes a dielectric layer 152, a dielectric layer 156 on the dielectric layer 152, a dielectric layer 160 on the dielectric layer 156, and a dielectric layer 161 on the dielectric layer 160. The top interposer 150 also includes conductive features 154 in the dielectric layer 152 and the dielectric layer 156, conductive features 158 in the dielectric layer 156 and the dielectric layer 160, and conductive features 162 in the dielectric layer 160 and the dielectric layer 161. Figure 4The top interposer 150 shown having four dielectric layers is an example. In some embodiments, the top interposer 150 has fewer or more than four dielectric layers.

[0027] The conductive features 154 and 158 can be redistribution lines and can include via portions and line portions. The via portion of the conductive feature 154 can be in direct contact with and electrically connected to the via 112 and the via 105 of the bottom integrated circuit die 100. The via portion of the conductive feature 158 can be in direct contact with and electrically connected to the line portion of the conductive feature 154. The conductive feature 162 can be a bonding pad. Some of the conductive features 162 can include a via portion and a pad portion. The via portion of the conductive feature 162 can be in direct contact with and electrically connected to the line portion of the conductive feature 158. Some of the conductive features 162 can include a pad portion without a via portion and can be dummy bonding pads that can be electrically isolated from the circuitry of the top interposer 150.

[0028] The dielectric layer 161 can be a bonding layer and the pad portion of the conductive feature 162 can be a bonding pad that can be bonded to an integrated circuit die in a subsequent process. The materials of the dielectric layer 161 and the conductive feature 162 can be selected to be suitable for bonding to an integrated circuit die in a subsequent process. The dielectric layers of the top interposer 150 can include the same or similar materials as described above for the dielectric layers of the bottom interposer 50 and can be formed by the same or similar methods. The conductive features of the top interposer 150 can include the same or similar materials as described above for the conductive features of the bottom interposer 50 and can be formed by the same or similar methods.

[0029] After forming the conductive features 162 in the dielectric layer 161 and the dielectric layer 160, a planarization process can be performed on the top surfaces of the conductive features 162 and the dielectric layer 161. Thus, the top surfaces of the conductive features 162 and the dielectric layer 161 are generally coplanar or flush within the process variation range. The planarization process can be CMP, a grinding process, an etch-back process, a combination thereof, etc. The pad portion of the conductive feature 162 can be used to bond to an integrated circuit die in a subsequent process and can have a pitch P2 of less than about 10 μm. The small value of the pitch P2 can correspond to a high density of the conductive features 162, which can improve the signal integrity, power integrity, and overall performance of the entire semiconductor package during operation.

[0030] In Figure 5 the top integrated circuit die 200 is bonded to the top interposer 150. In Figure 5In the illustrated embodiment, a layout is provided as an example in which two top integrated circuit dies 200 can overlap two bottom integrated circuit dies 100. Other layouts with different numbers of top integrated circuit dies 200 and bottom integrated circuit dies 100 can be envisioned. Each top integrated circuit die 200 can be a logic die (such as a CPU, GPU, SoC, AP, microcontroller, etc.), a memory die (such as a DRAM die, SRAM die, HBM die, etc.), a power management die (such as a PMIC die), an RF die, a sensor die, a MEMS die, a signal processing die (such as a DSP die), a front-end die (such as an AFE die), a DTS die, etc. or a combination thereof. The materials and manufacturing methods of the features in the top integrated circuit die 200 can be found by reference to the similar features in the bottom integrated circuit die 100. Each top integrated circuit die 200 can include a semiconductor substrate 202, which can have an active surface (such as the surface facing down in Figure 5 ), which can be referred to as the front side, and a non-active surface (such as the surface facing up in Figure 5 ), which can be referred to as the back side. The front side of the semiconductor substrate 202 can correspond to the active side or the front side of the top integrated circuit die 200. Devices (not shown separately) can be disposed at the active surface of the semiconductor substrate 202. The devices can be active devices (such as transistors, diodes, etc.), capacitors, resistors, etc. An interconnect structure 204 can be disposed on the active surface of the semiconductor substrate 202.

[0031] A bonding layer 206 can be disposed on the interconnect structure 204 at the front side of the top integrated circuit die 200. One or more passivation layers (not shown separately) can be disposed between the bonding layer 206 and the interconnect structure 204. In some embodiments, the bonding layer 206 and the dielectric layer 161 include the same material. Die connectors 208 can extend through the bonding layer 206 and can be electrically connected to the metallization pattern of the interconnect structure 204. In some embodiments, the die connectors 208 and the conductive features 162 include the same material.

[0032] The top integrated circuit die 200 can be bonded to the top interposer 150 by placing the top integrated circuit die 200 using a pick-and-place process or the like and then bonding the top integrated circuit die 200 to the top interposer 150. The bonding layer 206 of the top integrated circuit die 200 can be directly bonded to the dielectric layer 161 by dielectric-to-dielectric bonding, and the die connectors 208 of the top integrated circuit die 200 can be directly bonded to the corresponding conductive features 162 by metal-to-metal bonding. The bonding process of the top integrated circuit die 200 and the top interposer 150 can be the same as or similar to the bonding process of the bottom integrated circuit die 100 and the bottom interposer 50 described above. The bottom interposer 50 and the top interposer 150 can enable communication between the bottom integrated circuit die 100 and the top integrated circuit die 200 and reduce the die-to-die wiring distance between the bottom integrated circuit die 100 and the top integrated circuit die 200, thereby improving the signal integrity, power integrity, and overall performance of the entire semiconductor package during operation.

[0033] In Figure 6 it, a top gap-fill layer 210 is formed on the top interposer 150 surrounding the top integrated circuit die 200. The top gap-fill layer 210 can also be referred to as an encapsulant. The top gap-fill layer 210 can be along the sidewalls of the top integrated circuit die 200. The top gap-fill layer 210 can include the same or similar materials formed and can be formed by the same or similar methods as described above for the bottom gap-fill layer 110. In some embodiments, the dielectric material of the top gap-fill layer 210 includes an inorganic dielectric material, such as a silicon-based dielectric material (e.g., silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, or the like), which can be formed by suitable deposition processes such as CVD, ALD, etc. In some embodiments, the dielectric material of the top gap-fill layer 210 includes an organic dielectric material, such as a polymer-based dielectric material (e.g., a molding compound, an epoxy resin, a resin, or the like), which can be formed by suitable molding processes such as compression molding, transfer molding, etc.

[0034] In some embodiments, both the top gap-fill layer 210 and the bottom gap-fill layer 110 include an inorganic dielectric material, such as an oxide. In some embodiments, the top gap-fill layer 210 includes an inorganic dielectric material (e.g., an oxide) and the bottom gap-fill layer 110 includes an organic dielectric material (e.g., a molding compound). In some embodiments, the top gap-fill layer 210 includes an organic dielectric material (e.g., a molding compound) and the bottom gap-fill layer 110 includes an inorganic dielectric material (e.g., an oxide). In some embodiments, both the top gap-fill layer 210 and the bottom gap-fill layer 110 include an organic dielectric material, such as a molding compound.

[0035] Initially, the top gap fill layer 210 may cover the back side of the top integrated circuit die 200. A thinning process may be performed to remove the excess top gap fill layer 210 and a portion of the semiconductor substrate 102. The thinning process can be a CMP process, a grinding process, an etch-back process, a combination thereof, etc. Thus, the surfaces of the top gap fill layer 210 and the top integrated circuit die 200 are substantially coplanar or flush within the process variation range. The top gap fill layer 210 and the top integrated circuit die 200 may have the same thickness T2 in the range of about 20 μm to about 500 μm. In some embodiments, the thickness T2 of the top integrated circuit die 200 is greater than the thickness T1 of the bottom integrated circuit die 100, which may result in improved heat dissipation of the entire semiconductor package during operation.

[0036] In Figure 7 this, the second carrier 250 is bonded to the top integrated circuit die 200 and the top gap fill layer 210. The second carrier 250 can be a semiconductor carrier, a glass carrier, a ceramic carrier, etc. The second carrier 250 may have the same or similar size as the first carrier 10. The second carrier 250 may be bonded to the top integrated circuit die 200 and the top gap fill layer 210 using the bonding layer 212 and the bonding layer 252. In some embodiments, the bonding layer 212 and the bonding layer 252 may each include a dielectric material, such as silicon dioxide or the like, and may be formed by suitable deposition processes such as CVD, ALD, etc. In such embodiments, the bonding process between the bonding layer 212 and the bonding layer 252 may be the same or similar to the bonding process between the dielectric layer 161 and the bonding layer 206 described with respect to Figure 5 this. In some embodiments, the bonding layer 212 may be an adhesive, such as a die-attach-film (DAF), and the bonding layer 252 may be a release film, such as a polymer-based light-to-heat-conversion (LTHC) film.

[0037] In Figure 8In [the figure], the first carrier 10 is removed to expose the surface of the conductive feature 54, which can serve as an under-bump metallization (UBM), and the electrical connection member 254 is formed on the exposed surface of the conductive feature 54. The electrical connection member 254 can allow other devices to be electrically connected to the bottom mediator 50. The electrical connection member 254 can be a ball grid array (BGA) connection member, a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, a micro-bump, a bump formed by an electroless nickel-electroless palladium-immersion gold (ENEPIG) technique, etc. In some embodiments, the electrical connection member 254 includes a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. The electrical connection member 254 can be formed by first depositing, electroplating, printing, solder transfer, ball placement, etc. to form a layer of solder. Once a layer of solder is formed on the structure, reflow soldering can be performed to shape the solder into a desired bump shape. In some embodiments, the electrical connection member 254 includes metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, etc., which do not have solder and have substantially vertical sidewalls. A metal top layer can be formed on the top of the metal pillars. The metal top layer can include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and can be formed by an electroplating process. In some embodiments, one or more integrated passive components 256 can be bonded to the electrical connection member 254. The integrated passive components 256 can be capacitors, resistors, inductors, etc.

[0038] The processes discussed above can be performed using a wafer-level process. The second carrier 250 can be a wafer and can include many structures similar to Figure 8 those shown (not shown separately). Thus, Figure 8 the structure shown in [the figure] can be referred to as a wafer structure 280 and can be singulated in subsequent processes. In Figure 9 [the figure], the wafer structure 280 is singulated to form individual integrated circuit package components 280'. The wafer structure 280 can be placed on a tape 258 supported by a frame 260. Then, the wafer structure 280 can be singulated along the scribe lines 262 such that the wafer structure 280 can be separated into individual integrated circuit package components 280'. The singulation process can include a sawing process, a laser cutting process, etc. A cleaning process or a rinsing process can be performed after the singulation process.

[0039] In Figure 10In [description], the integrated circuit package component 280' is bonded to the package substrate 300, and the underfill 310 is formed between the integrated circuit package component 280' and the package substrate 300. The package substrate 300 may include bonding pads 304 on a first side and bonding pads 306 on a second side. The package substrate 300 may include metallization layers and vias (not shown separately) that are physically and electrically connected to the bonding pads 304 and the bonding pads 306. The electrical connection member 254 of the integrated circuit package component 280' may be connected to the bonding pad 304. The electrical connection member 308 may be disposed on the bonding pad 306, and the electrical connection member 308 may be connected to other electrical devices. The electrical connection member 308 may be formed of the same or similar materials as described above for the electrical connection member 254 and may be formed by the same or similar methods. In some embodiments, the package substrate 300 includes active and passive devices (not shown separately), such as transistors, capacitors, resistors, combinations thereof, etc. The metallization layers may be formed over the active and passive devices and may connect the active and passive devices to form a functional circuit. During the bonding process, the electrical connection member 254 may be reflow soldered to bond the integrated circuit package component 280' to the bonding pad 304. The electrical connection member 254 may electrically and physically connect the package substrate 300 to the integrated circuit package component 280'.

[0040] The underfill 310 may surround the electrical connection member 254 and protect the joints generated by reflow soldering the electrical connection member 254. In a top view, the underfill 310 may surround the integrated circuit package component 280' and may follow the sidewalls of the bottom interposer 50, the bottom gap fill layer 110, the top interposer 150, and the top gap fill layer 210. The underfill 310 may be formed by a capillary flow process after the integrated circuit package component 280' is bonded to the package substrate 300, or may be formed by a suitable deposition method before the integrated circuit package component 280' is bonded to the package substrate 300. Subsequently, the underfill 310 may be cured. The integrated circuit package component 280' may have a thickness T3 in the range of about 0.7 mm to about 1 mm. The thickness T3 may be the distance from the top surface of the second carrier 250 to the top surface of the package substrate 300. Figure 10 The structure shown may be collectively referred to as the semiconductor package 400.

[0041] Figure 11 There is shown a Figure 10 semiconductor package 402 and structure similar to the semiconductor package 400 shown in [description], where like reference numerals refer to like components. Figure 11An embodiment is shown in which the second carrier 250, the bonding layer 212, and the bonding layer 252 are removed. In embodiments where the bonding layer 212 and the bonding layer 252 comprise a dielectric material, the second carrier 250, the bonding layer 212, and the bonding layer 252 can be removed by a thinning process (such as a CMP process, a grinding process, an etch-back process, combinations thereof, etc.). In embodiments where the bonding layer 212 can be an adhesive and the bonding layer 252 can be a release film, the second carrier 250, the bonding layer 212, and the bonding layer 252 can be removed by projecting a beam of light (such as a laser or UV light) onto the bonding layer 252 to cause the release film to decompose when exposed to the beam. The second carrier 250, the bonding layer 212, and the bonding layer 252 can be removed Figure 9 before or after the monolithization process shown. The bottom gap-fill layer 110 and the bottom integrated circuit die 100 can have the same thickness T1 in the range of about 15 μm to about 30 μm. The top gap-fill layer 210 and the top integrated circuit die 200 can have the same thickness T2 in the range of about 20 μm to about 500 μm. In some embodiments, the thickness T2 of the top integrated circuit die 200 is greater than the thickness T1 of the bottom integrated circuit die 100, which can result in improved heat dissipation of the semiconductor package 402 during operation. The integrated circuit package assembly 280' can have a thickness T3 in the range of about 0.7 mm to about 1 mm. The thickness T3 can be the distance from the top surface of the second carrier 250 to the top surface of the package substrate 300.

[0042] Figure 12 An illustration is shown of Figure 10 a semiconductor package 404 and a structure similar to the semiconductor package 400 shown in Figure 12An embodiment is shown in which one or more bridge die 120 are disposed beside a bottom integrated circuit die 100. The one or more bridge die 120 may have a structure similar to that of the bottom integrated circuit die 100, but the one or more bridge die 120 may not have devices disposed at the active surface of the semiconductor substrate, the active surface of the semiconductor substrate facing the interconnect structure of the one or more bridge die 120. The one or more bridge die 120 may be bonded to the bottom interposer 50 through dielectric-to-dielectric and metal-to-metal bonding. The one or more bridge die 120 may extend through the bottom gap fill layer 110 and may be physically and electrically connected to the bottom interposer 50 and the top interposer 150. Thus, the one or more bridge die 120 may be electrically connected to the bottom integrated circuit die 100 and the top integrated circuit die 200, and communication between the bottom integrated circuit die 100 and the top integrated circuit die 200 may be improved. The bottom gap fill layer 110, the bottom integrated circuit die 100, and the one or more bridge die 120 may have the same thickness T1 in the range of about 15 μm to about 30 μm. The top gap fill layer 210 and the top integrated circuit die 200 may have the same thickness T2 in the range of about 20 μm to about 500 μm. In some embodiments, the thickness T2 of the top integrated circuit die 200 is greater than the thickness T1 of the bottom integrated circuit die 100, which may result in improved heat dissipation of the semiconductor package 404 during operation. The integrated circuit package assembly 280’ may have a thickness T3 in the range of about 0.7 mm to about 1 mm. The thickness T3 may be the distance from the top surface of the second carrier 250 to the top surface of the package substrate 300.

[0043] Embodiments of the present disclosure have some advantageous features. By using the dielectric-to-dielectric and metal-to-metal bonding mechanisms to bond the bottom integrated circuit die 100 to the bottom interposer 50 and the top integrated circuit die 200 to the top interposer 150, the density of the conductive features 62 and the conductive features 162 can be increased. By using the bottom interposer 50 and the top interposer 150 to facilitate communication between the bottom integrated circuit die 100 and the top integrated circuit die 200, the die-to-die wiring distance between the bottom integrated circuit die 100 and the top integrated circuit die 200 can be reduced. Thus, the signal integrity, power integrity, and overall performance of the semiconductor packages 400, 402, and 404 can be improved during operation.

[0044] In one embodiment, a semiconductor package includes: a first interposer; a first semiconductor die including a first substrate and a first bonding layer on a first side of the first substrate, wherein a plurality of first bonding pads are disposed in the first bonding layer, and wherein the first bonding layer and the plurality of first bonding pads are bonded to the first interposer by metal-to-metal bonding and dielectric-to-dielectric bonding; a second interposer on a second side of the first substrate, the second side of the first substrate being opposite to the first side of the first substrate; and a second semiconductor die including a second substrate and a second bonding layer on a first side of the second substrate, wherein a plurality of second bonding pads are disposed in the second bonding layer, wherein the second bonding layer and the plurality of second bonding pads are bonded to the second interposer by metal-to-metal bonding and dielectric-to-dielectric bonding, and wherein the second interposer is between the first semiconductor die and the second semiconductor die. In one embodiment, the semiconductor package further includes a first encapsulant surrounding the first semiconductor die and a second encapsulant surrounding the second semiconductor die. In one embodiment, both the first encapsulant and the second encapsulant include an oxide. In one embodiment, the first encapsulant includes a molding compound and the second encapsulant includes an oxide. In one embodiment, the first encapsulant includes an oxide and the second encapsulant includes a molding compound. In one embodiment, both the first encapsulant and the second encapsulant each include a molding compound. In one embodiment, the second semiconductor die has a greater thickness than the first semiconductor die. In one embodiment, the semiconductor package further includes an integrated passive component on the first interposer, wherein the first interposer is between the first semiconductor die and the integrated passive component.

[0045] In one embodiment, a semiconductor package includes: a package substrate; a first interposer, wherein a first side of the first interposer is bonded to the package substrate; a first semiconductor die, bonded to a second side of the first interposer, the second side of the first interposer being opposite to the first side of the first interposer, wherein the first semiconductor die is bonded to the first interposer by metal-to-metal bonding and dielectric-to-dielectric bonding; a first encapsulant, along a sidewall of the first semiconductor die; a second interposer, wherein a first side of the second interposer is in contact with the first semiconductor die and the first encapsulant, and wherein the first semiconductor die is between the first interposer and the second interposer; a second semiconductor die, bonded to a second side of the second interposer, the second side of the second interposer being opposite to the first side of the second interposer, wherein the second semiconductor die is bonded to the second interposer by metal-to-metal bonding and dielectric-to-dielectric bonding; a second encapsulant, along a sidewall of the second semiconductor die; and a carrier, on the second semiconductor die and the second encapsulant. In one embodiment, the first encapsulant and the second encapsulant include the same inorganic dielectric material. In one embodiment, the first encapsulant includes an inorganic dielectric material and the second encapsulant includes an organic dielectric material. In one embodiment, the semiconductor package further includes a bridging die, wherein the bridging die is between the first interposer and the second interposer, and wherein the bridging die is electrically connected to the first interposer and the second interposer. In one embodiment, the semiconductor package further includes integrated passive components on the first side of the first interposer.

[0046] In one embodiment, a method of manufacturing a semiconductor package includes: forming a first interposer on a first carrier; bonding a first semiconductor die to a first side of the first interposer by metal-to-metal bonding and dielectric-to-dielectric bonding, wherein an active side of the first semiconductor die faces the first interposer; forming a first encapsulant along a sidewall of the first semiconductor die; forming a second interposer on the first semiconductor die and the first encapsulant, wherein the first encapsulant is between the first interposer and the second interposer; bonding a second semiconductor die to the second interposer by metal-to-metal bonding and dielectric-to-dielectric bonding, and wherein an active side of the second semiconductor die faces the second interposer, wherein the second interposer is between the first semiconductor die and the second semiconductor die; and forming a second encapsulant along a sidewall of the second semiconductor die. In one embodiment, the method further includes removing the first carrier; attaching a second side of the first interposer to a package substrate, the second side of the first interposer being opposite the first side of the first interposer; placing an underfill between the first interposer and the package substrate. In one embodiment, the method further includes bonding an integrated passive component to the second side of the first interposer. In one embodiment, the second interposer completely separates the first encapsulant and the second encapsulant. In one embodiment, the method further includes bonding a bridge die to the first side of the first interposer by metal-to-metal bonding and dielectric-to-dielectric bonding. In one embodiment, the second encapsulant includes a polymer. In one embodiment, the thickness of the second encapsulant is greater than that of the first encapsulant.

[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, and are not intended to limit them; although the embodiments of the present invention have been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor package, characterized in that: include: The first intermediary; a first semiconductor die comprising a first substrate and a first bonding layer on a first side of the first substrate, wherein a plurality of first bonding pads are disposed in the first bonding layer, and wherein the first bonding layer and the first bonding pads are bonded to the first interposer by metal-to-metal bonding and dielectric-to-dielectric bonding; a second interposer on a second side of the first substrate, the second side of the first substrate being opposite to the first side of the first substrate; as well as A second semiconductor die comprises a second substrate and a second bonding layer on a first side of the second substrate, wherein a plurality of second bonding pads are disposed in the second bonding layer, wherein the second bonding layer and the second bonding pads are bonded to the second interposer by metal-to-metal bonding and dielectric-to-dielectric bonding, and wherein the second interposer is between the first semiconductor die and the second semiconductor die.

2. The semiconductor package according to claim 1, wherein: Also includes: a first encapsulation body surrounding the first semiconductor die; as well as A second encapsulant surrounds the second semiconductor die.

3. The semiconductor package according to claim 1, wherein: Wherein the second semiconductor die has a greater thickness than the first semiconductor die.

4. The semiconductor package according to claim 1, wherein: Also includes: Integrated passive components are on the first interposer, wherein the first interposer is between the first semiconductor die and the integrated passive components.

5. The semiconductor package according to claim 1, wherein: Also includes: A packaging substrate, wherein the first interposer is disposed on the packaging substrate.

6. The semiconductor package according to claim 1, wherein: Also includes: A carrier is disposed on the second semiconductor die.

7. The semiconductor package according to claim 1, wherein: Also includes: A bridge die is between the first interposer and the second interposer and is electrically connected to the first interposer and the second interposer.

8. A semiconductor package, characterized in that: include: Package substrate; a first interposer, wherein a first side of the first interposer is bonded to the package substrate; a first semiconductor die bonded to a second side of the first interposer, the second side of the first interposer being opposite to the first side of the first interposer, wherein the first semiconductor die is bonded to the first interposer by metal-to-metal bonding and dielectric-to-dielectric bonding; a first encapsulant along a sidewall of the first semiconductor die; a second interposer, wherein a first side of the second interposer is in contact with the first semiconductor die and the first encapsulant, and wherein the first semiconductor die is between the first interposer and the second interposer; a second semiconductor die bonded to a second side of the second interposer, the second side of the second interposer being opposite to the first side of the second interposer, wherein the second semiconductor die is bonded to the second interposer by metal-to-metal bonding and dielectric-to-dielectric bonding; a second encapsulant along a sidewall of the second semiconductor die; as well as A carrier is on the second semiconductor die and the second encapsulation body.

9. The semiconductor package according to claim 8, wherein: Also includes: A bridging die, wherein the bridging die is between the first interposer and the second interposer, and wherein the bridging die is electrically connected to the first interposer and the second interposer.

10. The semiconductor package according to claim 8, wherein Also includes: Integrating passive components on the first side of the first interposer.

Images