Integrated circuit device

Abstract

Some embodiments relate to an integrated circuit element incorporating a dual via structure for through-chip connection. The integrated circuit device includes a substrate, at least one dielectric layer disposed over a front side surface of the substrate, and a plurality of metal layers residing in the at least one dielectric layer. The integrated circuit element also includes a first via structure and a second via structure. The first via structure includes a plurality of vias. The first via structure is electrically connected to one of the plurality of metal layers and extends through the front side surface of the substrate. The second via structure extends into the substrate from a back side surface of the substrate opposite the front side surface and contacts the first via structure.

Description

Technical Field

[0001] An embodiment of the present utility model relates to an integrated circuit element. Background Art

[0002] The use of through-silicon vias (TSVs) (or, alternatively, through-chip vias) in integrated circuit (IC) elements enables signals to pass vertically through the IC, thereby facilitating the development of high-performance three-dimensional (e.g., stacked) elements by increasing the connection density between ICs and shortening the connection length.

[0003] As IC technology continues to evolve, the corresponding connection structures are often updated to maintain compatibility with the IC elements being interconnected. Summary of the Utility Model

[0004] An embodiment of the present utility model provides an integrated circuit element, comprising: a substrate; at least one dielectric layer disposed on a front-side surface of the substrate; a plurality of metal layers residing in the at least one dielectric layer; a first via structure including a plurality of vias, the first via structure being electrically connected to one of the plurality of metal layers and extending through the front-side surface of the substrate; and a second via structure extending from a rear-side surface of the substrate, opposite to the front-side surface, into the substrate and contacting the first via structure.

[0005] In some embodiments, the plurality of metal layers include a top metal layer and at least one additional metal layer located between the top metal layer and the substrate; and the first via structure extends from and is electrically connected to the top metal layer. In some embodiments, each of the plurality of vias is directly connected to one of the plurality of metal layers and extends into the substrate. In some embodiments, the plurality of vias are arranged in a two-dimensional array in a top-down view of the substrate. In some embodiments, a plurality of doped regions are distributed between the plurality of vias within the substrate, wherein the plurality of doped regions are electrically isolated. In some embodiments, a plurality of metal structures are distributed between the plurality of vias within at least one of the plurality of metal layers, wherein the plurality of metal structures are electrically isolated. In some embodiments, the integrated circuit element further comprises: at least one shallow trench isolation (STI) region disposed in the substrate at the front-side surface, wherein the plurality of vias extend through the at least one STI region. In some embodiments, the substrate defines an etched region extending from the back-side surface into the substrate; and the second via structure covers the etched region. In some embodiments, the integrated circuit element further comprises: at least one shallow trench isolation (STI) region disposed in the substrate at the front-side surface, wherein the second via structure contacts at least one STI region within the etched region. In some embodiments, the second via structure extends over a portion of the back-side surface of the substrate. In some embodiments, the integrated circuit element further comprises: a dielectric structure isolating the first via structure from the substrate.

[0006] Embodiments of the present utility model provide an integrated circuit component, comprising: a substrate having a front surface and a rear surface opposite to the front surface, the substrate having an etching region in the rear surface, the etching region extending through the front surface; at least one dielectric layer disposed on the front surface of the substrate, the at least one dielectric layer including a plurality of metal layers; a plurality of through-holes, each of the plurality of through-holes being electrically connected to a top metal layer among the plurality of metal layers and extending through the remaining one or more of the plurality of metal layers and the front surface of the substrate; and a metal structure extending from the back surface into the substrate, covering the etching region, and contacting the plurality of through-holes.

[0007] Based on the above, some embodiments of the present utility model provide IC components including a double through-hole structure for through-chip connection. In some embodiments, the through-hole structure may not be implemented as a single deep and wide through-hole, thereby reducing metal loss or metal damage caused by the through-hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Reading the following detailed description in conjunction with the accompanying drawings will best understand various aspects of the present disclosure. It should be noted that, according to standard practices in the industry, various features are not drawn to scale. In fact, for the sake of clarity of the discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0009] Figure 1 FIG. shows some embodiments of an IC component employing a double through-hole structure for through-chip connection according to the present disclosure.

[0010] Figure 2 FIG. shows a cross-sectional view of some embodiments of an IC component employing a double through-hole structure for through-chip connection.

[0011] Figures 3 - 14 FIG. shows a cross-sectional view of some embodiments of the semiconductor structure of an IC component that employs a double through-hole structure for through-chip connection at various stages of manufacturing.

[0012] Figure 9A and Figure 9B FIG. shows a plan view of a part of some embodiments of the semiconductor structure of an IC component that employs a double through-hole structure for through-chip connection at relevant manufacturing stages.

[0013] Figure 15 FIG. shows a method of forming an IC component that employs a double through-hole structure for through-chip connection according to some embodiments. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Additionally, the disclosure may repeat reference numerals and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] In addition, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one component or feature shown in the figures to another (other) component or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0016] Different types of TSVs are employed in some IC components. Two such types include "via-last" TSVs (or back TSVs (BTSVs)) and "via-middle" TSVs (or middle TSVs (MTSVs)). Generally, BTSVs extend directly through the substrate from the backside surface of the IC substrate through relatively large, angled trenches to a metal layer located above the frontside surface of the substrate relative to the backside surface. MTSVs are typically created by forming a single large via (e.g., by vertical etching) through the front (or back) surface of the substrate to the backside surface.

[0017] With the advancement of IC technology, typical BTSVs and MTSVs have become less effective as solutions for some chip vias. For example, the use of thin metal layers reduces the acceptable landing margin (e.g., acceptable depth variation) of the large dorsal surface trenches associated with BTSVs. In addition, due to the etching of the large dorsal surface trenches, extremely low-k (ELK) dielectrics (e.g., sometimes used in the back-end-of-line (BEOL) IC process above the front-side surface of the substrate) are exposed to moisture, which may lead to reliability issues of the dielectrics. Generally speaking, ELK dielectrics facilitate the use of relatively thin dielectric layers, thereby providing relatively low parasitic capacitance and thus enabling higher circuit switching speeds in advanced IC components that employ such dielectrics.

[0018] MTSVs are also becoming increasingly problematic, especially at the wafer edge. More specifically, due to their relatively deep and wide front-side vias, after the typical copper electro-chemical plating (ECP) edge bevel removal (EBR) process of the wafer, the copper commonly used for vias may be completely missing or only partially present. The EBR process typically involves removing copper or other metals from the wafer edge to prevent the metal from peeling off the wafer and to improve the adhesion of the additional layer to the wafer. More generally, the relatively large volume of copper associated with the depth and width of the MTSV may be related to an increased likelihood of deformation (e.g., generating one or more nodules) after thermal processes typically associated with IC manufacturing.

[0019] To address these issues, the present disclosure provides some embodiments of an IC component including a dual via structure for through-chip connections. More specifically, in some embodiments, this IC component may include a first via structure created through the front-side surface of the substrate, which is connected to a second via structure formed through the back-side surface of the substrate. In some embodiments, the first via structure may not be implemented as a single deep and wide via (e.g., due to not extending through the entire substrate for subsequent packaging processes), thereby reducing metal loss or metal damage caused by the via. In addition, in some embodiments, the second via structure may not be as deep as typical BTSVs and thus may not directly affect any metal layer or ELK dielectric.

[0020] Figure 1Schematic diagrams of some embodiments of an IC component 100 that employs a dual-via structure to facilitate through-chip connections in accordance with the present disclosure are shown. The IC component 100 may include a substrate 102 and one or more dielectric layers 104, with a plurality of metal layers 106 residing on the front-side surface of the substrate 102. Within this configuration, the IC component 100 may also include a first via structure 108 that extends from one of the plurality of metal layers 106 and electrically connects to one of the plurality of metal layers 106. The IC component 100 may also include a second via structure 110 that extends from the back-side surface of the substrate 102, opposite the front-side surface, into the substrate 102 and contacts the first via structure 108. In some embodiments, by using the first via structure 108 and the second via structure 110 in series, neither the first via structure 108 nor the second via structure 110 has the depth and corresponding potential problems typically associated with other TSVs (such as the BTSVs and MTSVs discussed above).

[0021] Although a single through-chip via structure pair including the first via structure 108 and the second via structure 110 is discussed above and below, in other embodiments the IC component 100 may include several or more such through-chip via structures.

[0022] Figure 2 Cross-sectional views of some embodiments of an IC component 100 that employs a dual-via structure for through-chip connections are shown. In some embodiments, the IC component 100 may include a substrate 102 in which a plurality of doped (or active) regions ( Figure 2 not shown) may be implanted or otherwise formed. In some embodiments, the doped regions may include areas in the substrate 102 where source and / or drain electrodes of transistors may be formed. Additionally, in some embodiments, at least one shallow trench isolation (STI) region 214 may reside in the substrate 102 (e.g., between transistors, diodes, etc., to prevent or limit current leakage between adjacent semiconductor elements or components). For example, at least one STI region 214 may be located between transistors, at least some of which may include gate structures 224 separated from the substrate 102 by an oxide structure 222, and / or may include one or more source / drain electrodes connected to the substrate 102. In some embodiments, additional semiconductor components other than transistors may be employed.

[0023] A barrier structure 216 (e.g., silicon nitride (SiN), serving as an insulator and / or chemical / diffusion barrier layer for the substrate 102) may be disposed on the front-side surface of the substrate 102 (e.g., from Figure 2From the perspective of the substrate 102 (downward). Above the barrier structure 216, one or more dielectric layers 104 including a plurality of metal layers 106 may be disposed. Each metal layer 106 may include one or more metal structures 210, some of which may be connected to the metal structures 210 of adjacent metal layers 106 through vias 211. Additionally, in some embodiments, the contact 205 may connect component structures (e.g., the gate structure 224, direct connections to the substrate 102, etc.) to the vias 211 and / or the metal structures 210 of the metal layer 106. Further, in some embodiments, one or more dielectric layers may include a first interlayer dielectric (ILD) 234, a second ILD 244, and additional ILD 254, which may be formed of the same or different materials and have the same or varying properties (e.g., dielectric constant), etc.

[0024] Also as Figure 2 shown, in some embodiments, the first via structure 108 may include a plurality of vias 208 electrically connected to one of the metal layers 106 (e.g., the top metal layer 206). In some embodiments, the plurality of vias 208 may also extend through one or more of the metal layers 106 and the front surface of the substrate 102. In Figure 2 certain embodiments, the plurality of vias 208 may also extend through at least one STI region 214 (e.g., extending into the substrate 102). In some embodiments, the plurality of vias 208 may include a specific metal (e.g., copper or an alloy including copper).

[0025] Although Figure 2 the number of the plurality of vias 208 explicitly shown is five, other numbers greater than or less than five may be employed in other embodiments. Additionally, in some embodiments, when observed in the plan view of the IC element 100, the plurality of vias 208 may be arranged two-dimensionally, e.g., arranged in a plurality of rows and a plurality of columns. Further, in some embodiments, the number of the plurality of vias 208 and the size (e.g., width) of each individual via 208 may be configured according to the specific requirements of the IC element 100 in terms of signal connectivity, power consumption, etc.

[0026] In contact with the first via structure 108 may be a second via structure 110 extending from the back surface of the substrate 102 into the substrate 102. As Figure 2As shown, the second vias structure 110 may be a metal layer disposed above an etch region extending from the backside surface of the substrate 102 into the substrate 102. In some embodiments, the second vias structure 110 may also cover adjacent or surrounding portions of the backside surface of the substrate 102. In some embodiments, the second vias structure 110 may be partially or completely isolated from the substrate 102 by a dielectric structure 212 (e.g., an oxide layer). Additionally, in some embodiments, the second vias structure 110 may contact (e.g., "land on") the barrier structure 216, as Figure 2 shown. In yet another embodiment, the second vias structure 110 may penetrate the barrier structure 216 and "land" on adjacent surfaces of one or more dielectric layers 104.

[0027] In some embodiments, the second vias structure 110 may be copper or another metal. Additionally, in some embodiments, the second vias structure 110 may be the same or substantially the same metal as that used for the plurality of vias 208 or the first vias structure 108.

[0028] In some embodiments, the second vias structure 110 may surround and contact the end of each of the plurality of vias 208, thereby providing a significant contact surface area between the first vias structure 108 and the second vias structure 110 for increasing conductivity.

[0029] Figure 2 Also shown is an example connection mechanism (e.g., a solder ball 202) coupled to the second vias structure 110, which may facilitate electrical connection of the die including the IC element 100 to another die, a package of the IC element 100, or another circuit or component.

[0030] Based on the dual vias structure of the IC element 100 discussed above in connection with Figure 1 and Figure 2 , in some embodiments, compared to other MTSV structures that are wider and extend deeper into the substrate 102, the first vias structure 108 may provide a significant reduction in the critical distance associated with the maximum width of each portion of the first vias structure 108 (e.g., the via 208) and the maximum length of the first vias structure 108 extending into the region defined by the substrate 102. This reduction may result in a lower likelihood of metal nodule formation, metal material loss or damage (e.g., due to the ECP EBR process of the wafer) or other anomalies associated with the vias. Correlatively, in some embodiments, the shortened length of the first vias structure 108 may substantially alleviate the need for a reduced thickness of the substrate 102, the thickness of which is sometimes associated with MTSVs that traverse the entire substrate 102, thereby potentially reducing the likelihood of breakage or other damage to the IC element 100.

[0031] In addition, the use of the second vias structure 110 can eliminate the possibility of exposing the ELK dielectric (e.g., one of the one or more dielectric layers 104) due to direct connection to the metal layer 106 therein, which is typical for BTSV. Conversely, as described above, the landing area of the second vias structure 110 is located near the interface between the substrate 102 and the one or more dielectric layers 104 (e.g., at or near the barrier structure 216) before encountering the metal layer 106.

[0032] Figures 3 - 14 Cross-sectional views of some embodiments of the semiconductor structure of the IC element 100 at various manufacturing stages are shown. Additionally, Figure 9A and Figure 9B Plan views of partial embodiments of the semiconductor structure of the IC element 100 at related manufacturing stages are shown. Although Figures 3 - 14 described as a series of actions, it should be understood that these actions are not restrictive as the order of actions can be changed in other embodiments and the disclosed method is also applicable to other structures. In other embodiments, some of the actions illustrated and / or described may be omitted in whole or in part.

[0033] Figure 3 A portion of the substrate 102 that can be used as an underlying structure is shown, on which additional processing actions as Figures 4 - 14 shown can be performed. The substrate 102 can be a p-doped silicon (p-Si) substrate, but other materials can be employed in other embodiments. Additionally, in some embodiments, the substrate 102 serves as a semiconductor wafer. After processing is completed (e.g., as described below in connection with Figures 4 - 14 ) such a wafer can optionally be stacked with other wafers and then singulated into individual die corresponding to individual IC elements 100.

[0034] Figure 4 The creation (e.g., etching) of one or more trenches 402 is shown, and Figure 5 the formation of at least one shallow trench isolation (STI) region 214 within the trenches 402 is shown. In some embodiments, the at least one STI region 214 can include a dielectric (e.g., silicon dioxide (SiO2)). Although Figure 5More than one STI region 214 is shown in the cross-sectional view, but the STI regions 214 can be interconnected to form a single STI region 214. In some embodiments, at least one STI region 214 can limit or prevent leakage current therethrough during operation. Additionally, after forming at least one STI region 214, chemical mechanical planarization (CMP) can be performed on the corresponding (e.g., front side) surface of the substrate 102 including at least one STI region 214. In some embodiments, the size of at least one STI region 214 is designed to allow small regions (e.g., Figure 4 substrate regions 404) of the substrate 102 to remain therebetween. Thus, multiple doped regions 502 can be formed (e.g., implanted) within these small regions (e.g., after forming at least one STI region 214). Incorporating the doped regions 502 can facilitate compliance with the design rule manual (DRM) as it relates to the doped region pattern generated in the substrate 102. (As used herein, a doped (or active) region can be any active semiconductor region of the substrate, such as a doped n-type or p-type region for transistor source and drain, and the intervening channel region thereunder located beneath the gate structure.) Thus, the doped region pattern employed within the region of at least one STI region 214 can be somewhat consistent with the doped region pattern used in other regions of the substrate 102, as may be required by the DRM.

[0035] Figure 6 Active and / or passive components, such as diodes, transistors, resistors, etc., are shown formed above the front side surface of the substrate 102 and outside the region occupied by at least one STI region 214. As Figure 6 shown, one or more components can include, for example, an oxide structure 222 formed above the substrate 102, followed by the formation of a gate structure 224 (e.g., metal, polysilicon, etc.).

[0036] Thereafter, a barrier structure 216 (e.g., silicon nitride (SiN)) can be formed above the substrate 102 and the various structures described above (e.g., oxide structure 222, gate structure 224, etc.), followed by the formation of one or more dielectric layers 104. The barrier structure 216 can serve as an electrical insulator and / or chemical barrier to isolate the substrate 102 from the dielectric and metal structures formed above it. In some embodiments, the barrier structure 216 can also form sidewall spacer structures to abut the oxide structure 222, gate structure 224, etc.

[0037] In some embodiments, at least one dielectric layer 104 to be formed (e.g., silicon dioxide (SiO2)) can be the first interlayer dielectric (ILD) 234. Multiple contacts 205 can be formed within the first ILD 234 (e.g., by etching and subsequent filling) for connection to the gate structure 224, substrate 102, etc.

[0038] Figure 7 Shows the formation of a second ILD 244 over a first ILD 234, where one or more vias 211 and a related metal structure 210 of a plurality of metal layers 106 (e.g., by etching and related filling) are created for connection to a plurality of contacts 205 and other structures in the first ILD 234. In some embodiments, the second ILD 244 can be an extremely low-k (ELK) dielectric, where k refers to the dielectric constant of the material.

[0039] In addition, in each of the metal layers 106, a plurality of metal structures 702 can be formed between the locations where a plurality of vias 208 are to be constructed. The metal structures 702 can be at least somewhat aligned with other metal structures of the second ILD 244 in other regions of the IC element (e.g., including those regions of the metal structure 210 attached to other metal structures 210, vias 211, or functional components). Thus, such alignment can facilitate compliance with design rules related to forming metal structures throughout the IC element 100. In some embodiments, the metal structures 702 can be not electrically or functionally coupled to each other, other metal structures 210, or other active regions or components of the IC element, and can thus be referred to as "dummy" (DMY) metal structures 702.

[0040] Figure 8 Shows the formation (e.g., etching) of via pores 802, and Figure 9 Shows the formation of a plurality of vias 208 that constitute a first via structure 108 within the via pores 802. In some embodiments, the depth to which the plurality of vias 208 penetrate the substrate 102 can depend on one or more characteristics of the electrical connections provided by the plurality of vias 208 within the IC element 100 (e.g., the function of the connection, such as a control or status signal, a data signal, a power connection, etc.). In some embodiments, the plurality of vias 208 can extend into the substrate 102 by about 20%-50% of the thickness of the substrate 102, or more specifically, 30%-40% of the thickness. Additionally, in some embodiments, the depth of the plurality of vias 208 can extend two to three times the depth of the STI region 214.

[0041] Thus, unlike typical MTSV technology, the plurality of vias 208 extend into the substrate 102 with a shallow depth and a small volume. In this way, the possibility of partial or complete absence of the metal (e.g., copper) of the plurality of vias 208 after typical ECP EBR processing of the wafer can be reduced. Also, as described above, the possibility of generating unwanted nodules or other metal deformations can also be limited.

[0042] Figure 9A Shows along Figure 9Planar view of some embodiments of a plurality of vias 208 along line A-A. In some embodiments, the cross-section of each of the plurality of vias 208 may be circular, but in other embodiments other shapes (square, rectangular, etc.) are also possible. Additionally, in some embodiments, the plurality of vias 208 may be arranged as a two-dimensional array including a plurality of rows and a plurality of columns. However, other arrangements with different patterns for placing the plurality of vias 208 are also possible. Further, although Figure 9A depicts twenty-five vias 208 in a 5×5 array, other numbers of vias 208 may be employed in other embodiments. In some embodiments, the number of vias 208 may be based on one or more characteristics of the electrical connections provided by the plurality of vias 208 (e.g., as described above), as well as the width of each of the plurality of vias 208. For example, when a smaller width is used for the plurality of vias 208, a greater number of vias 208 may be employed to provide the same type of electrical connection by the plurality of vias 208.

[0043] In some embodiments, the width of each of the plurality of vias 208 may be a critical dimension (CD), which is limited to help prevent the introduction of defects, such as those discussed above. For example, compared to the width of a typical MTSV, the width of each of the plurality of vias 208 may be relatively small to prevent problems typically associated with MTSVs (e.g., metal loss in the vias 208, generation of nodules or other metal deformations due to the ECPEBR processing of the wafer, etc.).

[0044] Moreover, as Figure 9A shown, the spacing of the plurality of vias 208 in the planar view may facilitate the placement of doped regions 502 in the row direction and the column direction (e.g., within the substrate region 404 shown in Figure 4 ). In some embodiments, the doped regions 502 may be at least somewhat aligned with other doped regions formed in the substrate 102 in other regions of the IC element (e.g., those regions including functional transistors and other semiconductor components). As described above, such alignment may facilitate compliance with design rules related to forming doped regions through the IC element 100. In some embodiments, the doped regions 502 may not be electrically or functionally coupled to other active regions or components of the IC element 100 and may thus be referred to as "dummy" (DMY) doped regions.

[0045] Figure 9B shows along Figure 9A plan view of some embodiments of a plurality of vias 208 and a plurality of metal structures 702 within a second ILD 244 along line B-B. In some embodiments, the spacing of the plurality of vias 208 in the plan view may facilitate the placement of the metal structures 702 in the row and column directions. Additionally, the metal structures 702 may be at least somewhat aligned with other metal structures 210 of the second ILD 244 in other regions of the IC element 100 (e.g., those regions including metal structures 210 attached to other metal structures 210, vias 211, or functional components). Thus, such alignment can facilitate compliance with design rules related to forming metal structures through the IC element 100. In some embodiments, the metal structures 702 may not be electrically or functionally coupled to each other, other metal structures, or other active regions or components of the IC element 100, and may thus be referred to as "dummy" (DMY) metal structures 702.

[0046] Figure 10 Illustrates the formation (e.g., by etching and subsequent deposition) of an additional ILD 254 (e.g., formed of a low-K (LK) dielectric material), which includes an additional metal layer 106 (e.g., a top metal layer 206), to couple to each of the plurality of vias 208 of the second via structure 108. Generally, LK dielectrics have a lower dielectric constant than silicon dioxide, while ELK dielectrics have a lower dielectric constant relative to LK dielectrics.

[0047] Figures 11 - 14 Illustrates Figure 1 the formation of the second via structure 110 cited in. For example, Figure 11 Illustrates etching the substrate 102 through the backside surface of the substrate 102 to form an etched region 1102 corresponding to the plurality of vias 208 of the first via structure 108. In some embodiments, the etched region 1102 includes sloped sidewalls 1104. Moreover, in some embodiments, the etched region 1102 may extend from the backside surface of the substrate 102 to a barrier structure 216 (e.g., as Figure 11 shown). In some embodiments, the etching of the etched region 1102 may be configured to remove an intended portion of the substrate 102, including those portions between the plurality of vias 208, without significantly affecting the STI region 214, the barrier structure 216, or the plurality of vias 208. In some embodiments, as Figure 2 shown, the etched region 1102 may extend through the barrier structure 216 and possibly into the first ILD 234.

[0048] Figure 12Shown is a dielectric structure 212 (e.g., an oxide layer) formed (e.g., deposited) over an etched region 1102 and some surrounding regions on a backside surface of a substrate 102. In some embodiments, the dielectric structure 212 may cover each of a plurality of vias 208 and at least one STI region 214 surrounded by the etched region 1102.

[0049] Figure 13 Shown is an etching of a portion 1302 of the dielectric structure 212 from the etched region 1102. In some embodiments, this portion 1302 of the dielectric structure 212 covering the barrier structure 216, the plurality of vias 208, and at least a portion of the STI region 214 adjacent to the plurality of vias 208 may be etched, thereby allowing at least a portion of the dielectric structure 212 covering the substrate 102 to be retained.

[0050] Figure 14 Shown is a formation (e.g., deposition) of a second via structure 110 over the plurality of vias 208, at least one STI region 214, and the remaining portion of the dielectric structure 212. In some embodiments, the second via structure 110 does not directly contact the substrate 102 because the dielectric structure 212 isolates the second via structure 110 from the substrate 102 to prevent any leakage current therebetween. Additionally, in some embodiments, the second via structure 110 has sufficient depth near the plurality of vias 208 to completely cover each of the plurality of vias 208, thus potentially maximizing the contact surface between the first via structure 108 and the second via structure 110.

[0051] In some embodiments, the metal (e.g., copper) employed in the second via structure 110 is the same as or similar to the metal employed in the plurality of vias 208 or the first via structure 108.

[0052] Additionally, in some embodiments, by limiting the depth of the etched region 1102 to the barrier structure 216 or near it, any potential problems associated with a narrow landing margin (associated with typical BTSVs) related to exposing the ELK dielectric to moisture or using a thin metal layer within at least one dielectric layer 104 can be addressed. Figure 11 the

[0053] Figure 15Method 1500 for forming an IC element having a dual via structure for through-chip connection according to some embodiments is shown. Although this method and other methods shown and / or described herein are shown as a series of actions or events, it should be understood that the present disclosure is not limited to the order or actions shown. Thus, in some embodiments, these actions may be performed in an order different from that shown, and / or may be performed simultaneously. Additionally, in some embodiments, the actions or events shown may be subdivided into multiple actions or events, which may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown may be omitted, and other actions or events not shown may be included.

[0054] Actions 1502 to 1520 may correspond to, for example, structures previously shown in Figures 3 - 14 in some embodiments. At action 1502, a substrate (e.g., substrate 102) may be provided. Figure 3 A cross-sectional view of some embodiments corresponding to action 1502 is shown.

[0055] At action 1504, at least one shallow trench isolation (STI) region (e.g., at least one STI region 214) may be formed in the substrate at the front side surface of the substrate. Figure 4 and Figure 5 A cross-sectional view of some embodiments corresponding to action 1504 is shown.

[0056] At action 1506, a plurality of doped regions (e.g., DMY doped regions 502) may be formed within the substrate 102. Figure 5 A cross-sectional view of some embodiments corresponding to action 1506 is shown.

[0057] At action 1508, a plurality of metal layers (e.g., metal layer 106) may be formed above the front side surface of the substrate and within at least one dielectric layer (e.g., dielectric layer 104). Figure 6 、 Figure 7 and Figure 10 A cross-sectional view of some embodiments corresponding to action 1508 is shown.

[0058] At action 1510, a plurality of metal structures (e.g., DMY metal structures 702) may be formed within at least one dielectric layer. Figure 7 A cross-sectional view of some embodiments corresponding to action 1510 is shown.

[0059] At action 1512, a plurality of vias (e.g., a plurality of vias 208) may be formed to extend from the top metal layer (e.g., top metal layer 206) of the plurality of metal layers and electrically connect to the top metal layer (e.g., top metal layer 206), and extend through the front side surface of the substrate.Figure 8 , Figure 9 and Figure 10 shows a cross-sectional view of some embodiments corresponding to operation 1512.

[0060] In operation 1514, an etch region (e.g., etch region 1102) may be formed in the backside surface of the substrate relative to the frontside surface, where the etch region extends through the frontside surface. Figure 11 shows a cross-sectional view of some embodiments corresponding to operation 1514.

[0061] In operation 1516, a dielectric structure (e.g., dielectric structure 212) may be formed over the etch region. Figure 12 shows a cross-sectional view of some embodiments corresponding to operation 1516.

[0062] In operation 1518, a portion (e.g., portion 1302) of the dielectric structure covering the plurality of vias may be removed. Figure 13 shows a cross-sectional view of some embodiments corresponding to operation 1518.

[0063] In operation 1520, a metal structure (e.g., second via structure 110) may be formed over the etch region to contact the plurality of vias. Figure 14 shows a cross-sectional view of some embodiments corresponding to operation 1520.

[0064] Some embodiments relate to an integrated circuit element. The integrated circuit element includes a substrate, at least one dielectric layer disposed over a frontside surface of the substrate, and a plurality of metal layers located in the at least one dielectric layer. The integrated circuit element further includes a first via structure and a second via structure. The first via structure includes a plurality of vias. The first via structure is electrically connected to one of the plurality of metal layers and extends through the frontside surface of the substrate. The second via structure extends from a backside surface of the substrate relative to the frontside surface into the substrate and contacts the first via structure.

[0065] In some embodiments, the plurality of metal layers includes a top metal layer and at least one additional metal layer between the top metal layer and the substrate; and the first via structure extends from and is electrically connected to the top metal layer. In some embodiments, each of the plurality of vias is directly connected to one of the plurality of metal layers and extends into the substrate. In some embodiments, the plurality of vias are arranged in a two-dimensional array when viewed from above the substrate. In some embodiments, a plurality of doped regions are distributed between the plurality of vias within the substrate, wherein the plurality of doped regions are electrically isolated. In some embodiments, a plurality of metal structures are distributed between the plurality of vias within at least one of the plurality of metal layers, wherein the plurality of metal structures are electrically isolated. In some embodiments, the integrated circuit element further includes: at least one shallow trench isolation (STI) region disposed in the substrate at the front-side surface, wherein the plurality of vias extend through at least one STI region. In some embodiments, the substrate defines an etched region extending from the back-side surface into the substrate; and the second via structure covers the etched region. In some embodiments, the integrated circuit element further includes: at least one shallow trench isolation (STI) region disposed in the substrate at the front-side surface, wherein the second via structure contacts the at least one STI region in the etched region. In some embodiments, the second via structure extends over a portion of the back-side surface of the substrate. In some embodiments, the integrated circuit element further includes: a dielectric structure isolating the first via structure from the substrate.

[0066] Some embodiments relate to other integrated circuit elements (e.g., front-side illuminated (FSI) CMOS photosensing elements and back-side illuminated (BSI) photosensing elements). In some embodiments, the integrated circuit element (e.g., an FSI CMOS photosensing element) includes a substrate having a front-side surface and a back-side surface opposite the front-side surface. The substrate defines an etched region in the back-side surface that extends through the front-side surface. In other embodiments, the integrated circuit element is a BSI CMOS photosensing element bonded to a logic element. The logic element includes a substrate having a front-side surface and a back-side surface opposite the front-side surface that is bonded to the front-side surface of the sensing element. The substrate defines an etched region in the back-side surface of the logic element that extends through the front-side surface. The integrated circuit element further includes at least one dielectric layer disposed over the front-side surface of the substrate. The at least one dielectric layer includes a plurality of metal layers. The integrated circuit element further includes a plurality of vias. Each of the plurality of vias is electrically connected to a top metal layer of the plurality of metal layers. Each of the plurality of vias also extends through the remaining one or more of the plurality of metal layers and the front-side surface of the substrate. The integrated circuit element further includes a metal structure extending from the back-side surface into the substrate, covering the etched region, and contacting the plurality of vias.

[0067] In some embodiments, the integrated circuit element further comprises: at least one shallow trench isolation (STI) region disposed in the substrate at the front side surface, wherein the metal structure and the plurality of vias extend through the at least one STI region. In some embodiments, the integrated circuit element further comprises: a dielectric structure isolating the metal structure from the substrate.

[0068] Some embodiments relate to a method of manufacturing an integrated circuit element. The method includes providing a substrate, and forming a plurality of metal layers above the front side surface of the substrate and within at least one dielectric layer. The method further includes forming a plurality of vias electrically connected to the top metal layer of the plurality of metal layers and extending through the front side surface of the substrate. The method further includes etching a region in the back side surface of the substrate relative to the front side surface, wherein the etched region extends through the front side surface. The method further includes forming a metal structure above the etched region, the metal structure contacting the plurality of vias.

[0069] In some embodiments, the method further comprises: forming at least one shallow trench isolation (STI) region in the substrate at the front side surface before forming the plurality of metal layers, wherein the metal structure and the plurality of vias extend through the at least one STI region. In some embodiments, the method further comprises: forming a dielectric structure above the etched region before forming the metal structure, the dielectric structure isolating the metal structure from the substrate. In some embodiments, the method further comprises: forming a plurality of doped regions in the substrate between the plurality of vias, wherein the plurality of doped regions are electrically isolated. In some embodiments, the method further comprises: forming a plurality of metal structures in at least one of the plurality of metal layers between the plurality of vias, wherein the plurality of metal structures are electrically isolated. In some embodiments, the plurality of vias are arranged in a two-dimensional array in a top view of the substrate.

[0070] It should be understood that in this written description and in the claims below, the terms "first", "second", "second", "third", etc. are merely general identifying symbols used for convenience of description to distinguish different components of one drawing or a series of drawings. By themselves, these terms do not imply any chronological order or structural proximity of these elements and are not intended to describe corresponding elements in different illustrated embodiments and / or unillustrated embodiments. For example, a "first dielectric layer" described in connection with a first figure may not necessarily correspond to a "first dielectric layer" described in connection with another figure and may not necessarily correspond to a "first dielectric layer" in an unillustrated embodiment.

[0071] The foregoing has outlined the features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for the same purpose and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the present utility model, and various changes, substitutions, and alterations can be made to this text without departing from the spirit and scope of the present utility model.

Claims

1. An integrated circuit component, comprising: substrate; At least one dielectric layer is disposed on the front surface of the substrate; A plurality of metal layers reside in the at least one dielectric layer; a first via structure comprising a plurality of vias, the first via structure being electrically connected to one of the plurality of metal layers and extending through the front side surface of the substrate; as well as A second via structure extends from a backside surface of the substrate opposite to the frontside surface into the substrate and contacts the first via structure.

2. The integrated circuit device according to claim 1, characterized in that: The plurality of metal layers include a top metal layer and at least one additional metal layer between the top metal layer and the substrate; and The first via structure extends from the top metal layer and is electrically connected to the top metal layer.

3. The integrated circuit device according to claim 1, characterized in that: Each of the plurality of vias is directly connected to one of the plurality of metal layers and extends into the substrate.

4. The integrated circuit device according to claim 3, characterized in that: The plurality of through holes are arranged in a two-dimensional array in a top-view angle of the substrate.

5. The integrated circuit element according to claim 3, characterized in that: Also includes: A plurality of doped regions are distributed between the plurality of vias in the substrate, wherein the plurality of doped regions are electrically isolated.

6. The integrated circuit element according to claim 3, characterized in that: Also includes: A plurality of metal structures are distributed between the plurality of vias within at least one of the plurality of metal layers, wherein the plurality of metal structures are electrically isolated.

7. The integrated circuit element according to claim 1, characterized in that: Also includes: At least one shallow trench isolation (STI) region is disposed in the substrate at the frontside surface, wherein the plurality of vias extend through the at least one STI region.

8. The integrated circuit device according to claim 1, wherein: The substrate defines an etch region extending from the backside surface into the substrate; and The second through hole structure covers the etching area.

9. The integrated circuit element according to claim 1, characterized in that: Also includes: A dielectric structure isolates the first via structure from the substrate.

10. An integrated circuit component, comprising: A substrate having a front side surface and a back side surface opposite to the front side surface, the substrate having an etched region in the back side surface, the etched region extending through the front side surface; At least one dielectric layer is disposed on the front surface of the substrate, and the at least one dielectric layer includes a plurality of metal layers; a plurality of vias, each of the plurality of vias being electrically connected to a top metal layer of the plurality of metal layers and extending through remaining one or more metal layers of the plurality of metal layers and the front side surface of the substrate; as well as A metal structure extends from the backside surface into the substrate, covers the etched region, and contacts the plurality of vias.

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