Semiconductor device structure

Abstract

Embodiments of the present disclosure provide a semiconductor device structure. The semiconductor device structure includes a source / drain region disposed over a substrate, a gate electrode layer disposed over the substrate, a first gate spacer disposed between the gate electrode layer and the source / drain region, and a dielectric spacer disposed between the gate electrode layer and the source / drain region. The first portion of the dielectric spacer contacts the first portion of the first gate spacer. The semiconductor device structure further includes a sacrificial layer disposed between the second portion of the first gate spacer and the second portion of the dielectric spacer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device structure, and more particularly to a semiconductor device structure including gate spacers. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each generation having smaller and more complex circuits than the previous generation. In the field of IC development, as the geometric dimensions (i.e., the smallest components (or wires) that can be formed using a manufacturing process) shrink, the functional density (i.e., the number of interconnect devices per unit wafer area) generally increases. Such a size reduction process generally provides benefits by increasing production efficiency and reducing associated costs. Such a size reduction process also increases the complexity of processing and manufacturing ICs.

[0003] Therefore, there is a need to improve the processing and manufacturing of ICs. Summary of the Utility Model

[0004] According to an embodiment of the present disclosure, a semiconductor device structure includes a source / drain region above a substrate, wherein the source / drain region includes a first portion and a second portion above the first portion; a gate electrode layer above the substrate, wherein the gate electrode layer includes a first portion and a second portion above the first portion; a first gate spacer disposed between the gate electrode layer and the source / drain region, wherein the first gate spacer includes a first portion and a second portion above the first portion; a dielectric spacer disposed between the gate electrode layer and the source / drain region, wherein the dielectric spacer includes a first portion and a second portion above the first portion, and the second portion of the dielectric spacer contacts the second portion of the first gate spacer; and a sacrificial layer disposed between the first portion of the first gate spacer and the first portion of the dielectric spacer.

[0005] According to an embodiment of the present disclosure, a semiconductor device structure includes a source / drain region above a substrate, wherein the source / drain region includes a first portion and a second portion above the first portion; a gate electrode layer above the substrate, wherein the gate electrode layer includes a first portion and a second portion above the first portion; and a first gate spacer disposed between the gate electrode layer and the source / drain region, wherein the first gate spacer includes a first portion and a second portion above the first portion. The first portion of the first gate spacer includes a first main portion, a first end portion, and a first angle formed between the first main portion and the first end portion, and the second portion of the first gate spacer includes a second main portion, a second end portion, and a second angle formed between the second main portion and the second end portion, wherein the second angle is different from the first angle.

[0006] According to an embodiment of the present disclosure, a semiconductor device structure includes source / drain regions above a substrate, wherein the source / drain regions include a first portion and a second portion above the first portion; a gate electrode layer above the substrate, wherein the gate electrode layer includes a first portion and a second portion above the first portion; a first gate spacer disposed between the gate electrode layer and the source / drain regions, wherein the first gate spacer includes a first portion and a second portion above the first portion; a second gate spacer disposed between the gate electrode layer and the source / drain regions, wherein the second gate spacer includes a first portion and a second portion above the first portion; and a dielectric spacer disposed between the gate electrode layer and the source / drain regions, wherein the dielectric spacer includes a first portion and a second portion above the first portion, the second portion of the dielectric spacer contacts the second portion of the first gate spacer, and the combined thickness of the first portion of the first gate spacer and the first portion of the second gate spacer is the same as the thickness of the first portion of the dielectric spacer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that the various features are not drawn to scale in accordance with standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figures 1 to 5 is a perspective view of multiple stages of manufacturing a semiconductor device structure according to some embodiments;

[0009] Figure 6 is a cross-sectional side view of a semiconductor device structure according to some embodiments along line A-A of Figure 5 ;

[0010] Figures 7A to 7C is a plurality of views of one of the multiple stages of manufacturing a semiconductor device structure according to some embodiments;

[0011] Figures 8A to 8C is a plurality of views of one of the multiple stages of manufacturing a semiconductor device structure according to some embodiments;

[0012] Figure 9 and Figure 10 are cross-sectional side views of multiple stages of manufacturing a semiconductor device structure according to some embodiments;

[0013] Figure 11A and Figure 11B are cross-sectional top views of a semiconductor device structure according to some embodiments along lines B-B and C-C of Figure 10 respectively;

[0014] Figure 12is a cross-sectional side view of one of multiple stages of manufacturing a semiconductor device structure according to some embodiments;

[0015] Figure 13A and Figure 13B are cross-sectional top views of a semiconductor device structure according to some embodiments along lines D-D and E-E respectively. Figure 12

[0016]

Symbol Explanation

[0017] 100: Semiconductor device structure

[0018] 101: Substrate

[0019] 103: First sacrificial layer

[0020] 104: Semiconductor layer stack

[0021] 105: Second sacrificial layer

[0022] 106: First semiconductor layer

[0023] 107: By-product layer

[0024] 107b: Second corner portion

[0025] 107f: Flat portion

[0026] 107t: First corner portion

[0027] 108: Second semiconductor layer

[0028] 110: Oxide layer

[0029] 111: Nitride layer

[0030] 112: Fin structure

[0031] 113: Nitride layer

[0032] 114: Trench

[0033] 115: Oxide layer

[0034] 116: Well portion

[0035] 118: Insulating material

[0036] 120: Isolation region

[0037] 130: Sacrificial gate structure / sacrificial gate stack

[0038] 134: Sacrificial gate electrode layer

[0039] 134b: Second corner portion ​

[0040] 134m: Main part

[0041] 134t: First corner part

[0042] 138: Gate spacer

[0043] 138A: First gate spacer

[0044] 138B: Second gate spacer

[0045] 144: Dielectric spacer

[0046] 146: Source / drain region

[0047] 162: Contact etch stop layer

[0048] 164: Interlayer dielectric layer

[0049] 170: Gate dielectric layer

[0050] 172: Gate electrode layer

[0051] 174: Gate structure

[0052] A, B: Angles

[0053] A - A, A′ - A′, B - B, C - C, D - D, E - E: Lines

[0054] D1: Dimension

[0055] X, Y, Z: Directions Detailed implementation manners

[0056] To implement different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. The following describes specific examples of components, configurations, etc. to simplify the present disclosure. Of course, these are merely examples and not restrictive. For example, in the following description, forming the first feature above or on top of the second feature may include embodiments where the first feature and the second feature are formed in direct contact, and may also include embodiments where additional features are formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0057] In addition, this document may use spatial relative terms, such as "under", "below", "lower", "above", "upper", etc., to facilitate the description of the relationship between one element or feature and another element or feature as shown in the figure. Except for the orientation shown in the figure, the spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative description symbols used herein can be correspondingly interpreted as well.

[0058] Embodiments of the present disclosure provide a semiconductor device structure including a gate spacer, where the gate spacer includes a straight portion and a terminal portion located at different positions, and a plurality of different angles are formed between the straight portion and the corresponding terminal portion. Therefore, the risk of electrical short - circuit occurring between the gate electrode layer and the source / drain region is reduced.

[0059] Although the embodiments described in the present disclosure are related to nanostructure channel field - effect transistors (FETs), embodiments of some aspects of the present disclosure can be used in other processes and / or other devices, such as fin - field - effect transistors, horizontal gate all - around (HGAA) field - effect transistors, vertical gate all - around (VGAA) field - effect transistors, and other suitable devices. Those of ordinary skill in the art should understand that other modifications that can be implemented are covered within the scope of the present disclosure. In the case of adopting a gate all - around (GAA) transistor structure, the gate all - around transistor structure can be patterned by any suitable method. For example, one or more lithography processes can be used to pattern the structure, including double - patterning or multi - patterning processes. Generally, double - patterning or multi - patterning processes combine lithography and self - alignment processes, allowing the formation of patterns with, for example, a pitch smaller than that obtained using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed along the sides of the patterned sacrificial layer using a self - alignment process. Then, the sacrificial layer is removed, and the remaining spacers can then be used to pattern the gate all - around structure.

[0060] Figures 1 to 13B An example process for manufacturing a semiconductor device structure 100 according to an embodiment of the present disclosure is shown. It should be understood that additional steps can be provided before, during, and after the Figures 1 to 13B shown process, and some of the steps described below can be replaced or deleted for additional embodiments of the method. The order of the steps / processes is not restrictive and can be interchanged.

[0061] Figures 1 to 5is a perspective view of multiple stages of fabricating a semiconductor device structure 100 according to some embodiments. As Figure 1 shown, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed above the front side of a substrate 101. The substrate 101 can be a semiconductor substrate. The substrate 101 can include a crystalline semiconductor material such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimonide phosphide (GaSbP), gallium arsenide antimonide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers to enhance the structure. In one aspect, the insulating layer is an oxygen-containing layer.

[0062] The substrate 101 can include multiple regions doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopants can be, for example, phosphorus for an n-type field effect transistor (NFET) and boron for a p-type field effect transistor (PFET).

[0063] The semiconductor layer stack 104 includes semiconductor layers made of alternating and different materials to facilitate the formation of nanostructured channels in multi-gate devices, such as nanostructured channel field effect transistors. In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials having different etch selectivities and / or oxidation rates. For example, the first semiconductor layer 106 can be made of Si, and the second semiconductor layer 108 can be made of SiGe. In some examples, the first semiconductor layer 106 can be made of SiGe, and the second semiconductor layer 108 can be made of Si. Alternatively, in some embodiments, either the first semiconductor layer 106 or the second semiconductor layer 108 can be or include other materials such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination of the above.

[0064] The first semiconductor layer 106 and the second semiconductor layer 108 can be formed by any suitable deposition process, such as epitaxy. By way of example, epitaxial growth of the semiconductor layer stack 104 can be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0065] The first semiconductor layer 106 or a portion of the first semiconductor layer 106 can form a nanostructured channel of the semiconductor device structure 100 in a subsequent manufacturing stage. As used herein, the term "nanostructure" represents any material portion at the nanoscale (or even at the microscale size) and having an extended shape, regardless of the cross-sectional shape of this portion. Thus, the term "nanostructure" represents both circular and substantially circular cross-section extended material portions, and the bundle-like or rod-like material portions include, for example, cylindrical or substantially rectangular cross-sections. The gate electrode can surround the nanostructured channel of the semiconductor device structure 100. The semiconductor device structure 100 can include nanostructure transistors. The nanostructure transistors can be referred to as nanosheet transistors, nanowire transistors, gate-all-around transistors, multi-bridge channel (MBC) transistors, or any transistor having a gate electrode surrounding the channel. The use of the first semiconductor layer 106 to define the channel or channels of the semiconductor device structure 100 is further discussed below.

[0066] Each of the first semiconductor layers 106 can have a thickness in the range of about 5 nanometers to about 30 nanometers. Each of the second semiconductor layers 108 can have a thickness equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each of the second semiconductor layers 108 has a thickness in the range of about 2 nanometers to about 50 nanometers. Figure 1 Three first semiconductor layers 106 and three second semiconductor layers 108 arranged alternately are shown for illustrative purposes and are not intended to limit the specific description of the patent scope. It should be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the semiconductor layer stack 104, and the number of layers depends on the preset number of channels of the semiconductor device structure 100. As Figure 1 As shown, an oxide layer 110 is formed on the topmost first semiconductor layer 106, and a nitride layer 111 is formed on the oxide layer 110. The oxide layer 110 can be silicon oxide and can have an etching selectivity different from that of the nitride layer 111. The nitride layer 111 can include any suitable nitride material, such as silicon nitride. In some embodiments, the oxide layer 110 and the nitride layer 111 can be a mask structure.

[0067] In Figure 2 , fin structures 112 are formed from semiconductor layer stack 104. Each fin structure 112 has an upper portion including a first semiconductor layer 106 and a second semiconductor layer 108 and a well portion 116 formed from substrate 101. Forming the fin structures 112 may be accomplished by using multiple patterning steps including photolithography and etching processes to pattern hard mask layers (such as oxide layer 110 and nitride layer 111) formed on semiconductor layer stack 104. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The photolithography process may include forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer to a pattern, performing a post-exposure bake process, and developing the photoresist layer to form a mask element including the photoresist layer. In some embodiments, a lithography process using an electron beam (e-beam) may be performed to pattern the photoresist layer to form the mask element. The etching process etches through the hard mask layer, through semiconductor layer stack 104, and into substrate 101 to form trenches 114 in the unprotected regions, leaving a plurality of extended fin structures 112. The trenches 114 extend along the X direction. The trenches 114 may be etched using dry etching (such as reactive ion etching), wet etching, and / or a combination of the above.

[0068] In Figure 3 , after forming the fin structures 112, an insulating material 118 is formed on substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structures 112 are embedded in the insulating material 118. Then, a planarization step (such as a chemical mechanical polishing (CMP) method and / or an etch-back method) is performed to expose the tops of the fin structures 112. The insulating material 118 may be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low dielectric constant dielectric material, or any suitable dielectric material. Forming the insulating material 118 may be accomplished by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), or flowable CVD (FCVD).

[0069] In Figure 4Therein, the recessed insulating material 118 is formed to form the isolation region 120. The recessed insulating material 118 exposes a portion of the fin structure 112, such as the semiconductor layer stack 104. The recessed insulating material 118 exposes the trench 114 between adjacent fin structures 112. The isolation region 120 can be formed using a suitable process, such as a dry etching process, a wet etching process, or a combination of the above. The top surface of the insulating material 118 can be flush with or lower than the surface of the second semiconductor layer 108 contacting the well portion 116, wherein the well portion 116 is formed by the substrate 101. In some embodiments, the isolation region 120 is a shallow trench isolation (STI). In some embodiments, the oxide layer 110 and the nitride layer 111 are also removed during the recessing of the insulating material 118.

[0070] In Figure 5 therein, a first sacrificial layer 103 is formed on the exposed surface of the semiconductor device structure 100, and a second sacrificial layer 105 is formed on the first sacrificial layer 103. In some embodiments, the first sacrificial layer 103 includes a dielectric material, such as an oxide which is silicon oxide. The first sacrificial layer 103 can be formed by any suitable process, such as chemical vapor deposition or plasma-enhanced chemical vapor deposition. In some embodiments, the first sacrificial layer 103 is a conformal layer formed by a conformal process, such as atomic layer deposition (ALD). In some embodiments, the second sacrificial layer 105 includes a semiconductor material, such as polysilicon. The second sacrificial layer 105 can be formed by any suitable process, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or physical vapor deposition (PVD). The second sacrificial layer 105 can be deposited first to coat the fin structure 112, and then a planarization process, such as a chemical mechanical polishing process, is performed. In some embodiments, the second sacrificial layer 105 can have a thickness in the range of about 100 nanometers to about 200 nanometers in the Z direction. In some embodiments, a mask layer (not shown) can be formed on the second sacrificial layer 105 after the planarization process. The mask layer can include more than one layer of material, such as an oxide layer and a nitride layer.

[0071] Figure 6 is a cross-sectional side view of the semiconductor device structure 100 along Figure 5 line A-A according to some embodiments. According to some embodiments, Figures 7A to 7C is one of the multiple views of one of the multiple stages of manufacturing the semiconductor device structure 100. Figure 6 、 Figure 7A 、 Figure 7C and Figures 8A to 8C The mask layer is omitted for clarity of illustration. Figure 7BA mask layer including a nitride layer 113 and an oxide layer 115 on the nitride layer 113 is shown. As Figure 7A and Figure 7B shown, the mask layer is used to pattern the second sacrificial layer 105 to form one or more sacrificial gate electrode layers 134. The patterning process includes a lithography process (e.g., photolithography or electron beam lithography), which may further include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations of the above. In some embodiments, the patterning further includes an etching process, where the etching process may include dry etching (e.g., reactive ion etching), wet etching, other etching methods, and / or combinations of the above. In some embodiments, the etching process is an anisotropic dry etching process using a chlorine-based etchant. In some embodiments, other etchants such as HBr and / or an oxygen-containing etchant may be used. In the anisotropic dry etching process, carrier gases or dilution gases such as Ar, N2, or He other than the etchant may also be used.

[0072] During the anisotropic dry etching process, by-products such as SiO, SiO-Cl, SiO-HBr, SiO-N, or SiO-Ar may form on the surface of the semiconductor device structure 100. Thus, a by-product layer 107 is formed on the surface of the semiconductor device structure 100, such as around the sacrificial gate electrode layer 134, the nitride layer 113, the oxide layer 115, and on the first sacrificial layer 103, as Figure 7A and Figure 7B shown. In some embodiments, the second sacrificial layer 105 has a thickness in the range of about 200 nanometers to about 300 nanometers, and a portion of the material of the second sacrificial layer 105 is located at the corners, such as between the side surface of the sacrificial gate electrode layer 134 and the portion of the first sacrificial layer 103 on the topmost first semiconductor layer 106, and between the side surface of the sacrificial gate electrode layer 134 and the portion of the first sacrificial layer 103 on the side surface of the bottommost first semiconductor layer 106 / second semiconductor layer 108, and these portions of the second sacrificial layer 105 located at the corners may not be removed by the anisotropic dry etching process. Additionally, a by-product layer 107 may be formed on the portions of the second sacrificial layer 105 located at the corners, making it even more difficult for the anisotropic etching process to remove these portions of the second sacrificial layer 105 because the etchant used in the anisotropic etching process is for etching semiconductor materials such as polysilicon. As described above, the by-product layer 107 is a silicon oxide base material. Furthermore, the subsequent process of removing the by-product layer 107 may use an etchant for removing oxides. Therefore, portions of the second sacrificial layer 105 located at the corners may be left, resulting in the gate electrode layer 172 (as Figure 12 ) and the source / drain regions 146 (asFigure 12 an electrical short circuit therebetween.

[0073] As Figure 7A and Figure 7B shown, the by-product layer 107 includes a first corner portion 107t between the side surface of the sacrificial gate electrode layer 134 and a portion of the first sacrificial layer 103 on the topmost first semiconductor layer 106. The by-product layer 107 includes a substantially flat portion 107f and a first corner portion 107t extending from the substantially flat portion 107f. In some embodiments, an angle A is formed between the substantially flat portion 107f and the first corner portion 107t of the by-product layer 107, and the angle A is less than 180 degrees. In some embodiments, the angle A ranges from about 120 degrees to about 170 degrees. The first corner portion 107t may be located on both sides of the sacrificial gate electrode layer 134, as Figure 7B shown. The first corner portion 107t of the by-product layer 107 may be formed on the first corner portion 134t of the sacrificial gate electrode layer 134, as Figure 7B shown. The sacrificial gate electrode layer 134 includes a main portion 134m and first corner portions 134t extending from the main portion 134m on both sides of the sacrificial gate electrode layer 134. An angle may be formed between the outer surface of the main portion 134m and the outer surface of the first corner portion 134t, and this angle may be the same as the angle A. In some embodiments, the sacrificial gate electrode layer 134 includes a top portion having a substantially fixed width along the X direction and a bottom portion having an increasing width toward the substrate 101.

[0074] Referring Figure 7A , the by-product layer 107 further includes a second corner portion 107b between the side surface of the sacrificial gate electrode layer 134 and a portion of the first sacrificial layer 103 on the side surface of the bottommost first semiconductor layer 106 / second semiconductor layer 108, where the side surface of the bottommost first semiconductor layer 106 / second semiconductor layer 108 is not covered by the sacrificial gate electrode layer 134. The second corner portion 107b extends from the substantially flat portion 107f and contacts a portion of the by-product layer 107 adjacent to the portion of the semiconductor layer stack 104 not covered by the sacrificial gate electrode layer 134. The second corner portion 107b of the by-product layer 107 is formed on the second corner portion 134b of the sacrificial gate electrode layer 134 (as Figure 7C ). The second corner portion 134b of the sacrificial gate electrode layer 134 may have a shape similar to that of the second corner portion 107b.

[0075] Figure 7C is the semiconductor device structure 100 along Figure 7ACross-sectional side view of line A'-A'. The by-product layer 107 and the first sacrificial layer 103 are omitted in the drawings to show the second corner portion 134b of the sacrificial gate electrode layer 134. As Figure 7C shown, the second corner portion 134b may be formed on the opposite side of the semiconductor layer stack 104 that is not covered by the sacrificial gate electrode layer 134. The second corner portion 134b has a dimension D1 in the Y direction. In some embodiments, the dimension D1 ranges from about 4 nanometers to about 9 nanometers. The second corner portion 134b also has a dimension in the X direction ranging from about 4 nanometers to about 9 nanometers.

[0076] Next, as Figures 8A to 8C shown, the first corner portion 107t, the second corner portion 107b, and the first corner portion 134t are removed, and the second corner portion 134b is recessed, and then the by-product layer 107 is removed. In some embodiments, the first corner portion 107t and the second corner portion 107b are removed using a first etching process, and the first corner portion 134t and the second corner portion 134b are recessed using a second etching process. For example, the first etching process may be an anisotropic dry etching process using a first etchant to remove the first corner portion 107t and the second corner portion 107b of the by-product layer 107. The first etchant may include HF, NH3, or a combination thereof. The first etchant removes the oxide substrate material at a faster rate relative to the semiconductor material. In addition, the anisotropic dry etching process is controlled to remove the first corner portion 107t and the second corner portion 107b of the by-product layer 107, and the main portion of the by-product layer 107 is substantially unaffected. The first etching process may further include, for example, N2, O2, or CO2 as a selective passivation gas and a dilution gas such as He, Ar, or N2. The flow rates of the various gases in the first etching process may range from about 20 standard cubic centimeters per minute (sccm) to about 3000 sccm. The plasma energy of the first etching process may range from about 10 watt (W) to about 4000 W, and the process pressure may range from about 1 millitorr (mTorr) to about 800 mTorr.

[0077] After the first etching process, the first corner portion 134t and the second corner portion 134b of the sacrificial gate electrode layer 134 are exposed. Then, a second etching process is performed to remove the first corner portion 134t of the sacrificial gate electrode layer 134 and the second corner portion 134b of the recessed sacrificial gate electrode layer 134. In some embodiments, the second etching process can be an anisotropic dry etching process using a second etchant to remove the first corner portion 134t and the recessed and second corner portion 134b. The second etchant can be different from the first etchant. In some embodiments, the second etchant is H2. In some embodiments, the etchant used to form the sacrificial gate electrode layer 134 includes a chlorine-based etchant and / or HBr and an oxygen-containing etchant, and the second etchant is different from the etchant used to form the sacrificial gate electrode layer 134. The chlorine-based etchant and / or HBr and the oxygen-containing etchant remove semiconductor materials such as polysilicon at a faster rate than the second etchant. Using the chlorine-based etchant and / or HBr and the oxygen-containing etchant to remove / recess the first corner portion 134t and the second corner portion 134b of the sacrificial gate electrode layer 134 may cause an unintended removal of a portion of the semiconductor layer stack 104 and / or the main portion 134m of the sacrificial gate electrode layer 134. The second etching process can further include, for example, N2, O2, or CO2 as a selective protective gas and a dilution gas such as He, Ar, or N2. The flow rates of the various gases in the second etching process can range from about 20 sccm to about 3000 sccm. The plasma energy of the second etching process can range from about 10 W to about 4000 W, and the process pressure can range from about 1 mTorr to about 800 mTorr.

[0078] In some embodiments, the second corner portion 134b is not completely removed, and a small portion of the second corner portion 134b is retained, as Figure 8A and Figure 8B shown. The remaining second corner portion 134b can have its dimensions D1 in the Y direction and in the X direction reduced to less than about 2 nanometers. In some embodiments, the remaining portion of the second corner portion 134b forms an acute angle with a portion of the first sacrificial layer 103 formed on the isolation region 120. This acute angle can range from about 30 degrees to about 60 degrees, for example, about 45 degrees. Additionally, the amount of the second corner portion 134b increases towards the substrate 101. In other words, the maximum amount of the second corner portion 134b is adjacent to the well portion 116 below the bottommost second semiconductor layer 108, and the minimum amount of the second corner portion 134b is adjacent to the topmost first semiconductor layer 106. In some embodiments, the second corner portion 134b is completely removed.

[0079] In some embodiments, a single anisotropic dry etching process using a mixed first etchant and second etchant may be performed to remove the first corner portion 107t, the second corner portion 107b, the first corner portion 134t, and the recessed second corner portion 134b.

[0080] After removing / recessing the first corner portion 107t, the second corner portion 107b, the first corner portion 134t, and the second corner portion 134b, a wet clean is performed to remove the by-product layer 107, as Figures 8A to 8C shown. The wet clean uses a solution that removes the oxide substrate material of the by-product layer 107, but does not remove the semiconductor material of the sacrificial gate electrode layer 134. In some embodiments, the wet clean also removes the exposed portion of the first sacrificial layer 103. In some embodiments, an etching process is performed to remove the exposed portion of the first sacrificial layer 103. After removing the by-product layer 107 and the exposed portion of the first sacrificial layer 103, the sacrificial gate electrode layer 134, a portion of the first sacrificial layer 103 below the sacrificial gate electrode layer 134, and the mask layer ( Figure 7B the nitride layer 113 and the oxide layer 115 in) form the sacrificial gate structure 130. Although Figure 8C two sacrificial gate structures 130 are shown, in some embodiments three or more sacrificial gate structures 130 may be arranged along the X direction.

[0081] Next, as Figure 9 shown, gate spacers 138 are formed on the sidewalls of the sacrificial gate structure 130. The formation of the gate spacers 138 may be by conformally depositing one or more layers, such as Figure 9 the first gate spacer 138A and the second gate spacer 138B shown, and then anisotropically etching one or more layers, for example. The first gate spacer 138A and the second gate spacer 138B may be formed of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon carbon oxide, SiOCN, and / or combinations thereof. The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as the channel region of the semiconductor device structure 100.

[0082] As Figure 9As shown, the portions of the fin structure 112 and the gate spacers 138 that are not covered by the sacrificial gate structure 130 are recessed to be above, flush with, or below the top surface of the isolation region 120. Any etching process of isotropic or anisotropic etching processes can be used to recess the portions of the fin structure 112, and the etching process can be selective to one or more crystalline planes of the substrate 101. The etching process can be, for example, reactive ion etching, neutral beam etching (NBE), or similar dry etching, or can be, for example, wet etching using tetramethyalammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant. Next, the edge portions of each of the second semiconductor layers 108 of the semiconductor layer stack 104 are horizontally removed along the X direction. Removing the edge portions of the second semiconductor layers 108 forms cavities. In some embodiments, a selective wet etching process is used to remove portions of the second semiconductor layers 108. In an example where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, a wet etchant such as, but not limited to, ammonium hydroxide (NH4OH), tetramethyalammonium hydroxide, ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution can be used to selectively etch the second semiconductor layer 108.

[0083] After removing the edge portions of each of the second semiconductor layers 108, a dielectric layer is deposited in the cavities to form dielectric spacers 144, as Figure 9 shown. The dielectric spacers 144 can be made of a low dielectric constant dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. The formation of the dielectric spacers 144 can first form a conformal dielectric layer through a conformal deposition process such as atomic layer deposition, and then perform anisotropic etching to remove the portions of the conformal dielectric layer other than the dielectric spacers 144. During the anisotropic etching process, the first semiconductor layer 106 protects the dielectric spacers 144. The remaining second semiconductor layers 108 are encapsulated between the dielectric spacers 144 along the X direction.

[0084] As Figure 10As shown, source / drain (S / D) regions 146 are formed from well portions 116. The source / drain regions 146 can grow in both vertical and horizontal directions to form facets, where the facets can correspond to the crystal planes of the material used for the well portions 116. In the present disclosure, the source region and the drain region can be used interchangeably, and the structures of the source region and the drain region are substantially the same. Additionally, the source / drain region can represent the source or the drain alone or both together depending on the context. The source / drain regions 146 of the n-type channel field effect transistor can be formed of one or more layers of Si, SiP, SiC, and SiCP, while the source / drain regions 146 of the p-type channel field effect transistor can be formed of one or more layers of Si, SiGe, Ge. For the p-type channel field effect transistor, the source / drain regions 146 can also include a p-type dopant such as boron (B). Forming the source / drain regions 146 can be achieved by an epitaxial growth method such as chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy.

[0085] Next, as Figure 10 shown, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surfaces of the semiconductor device structure 100. The contact etch stop layer 162 covers the sidewalls of the sacrificial gate structure 130, the insulating material 118, and the source / drain regions 146. The contact etch stop layer 162 can include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, the like, or a combination of the above, and can be formed by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or any suitable deposition technique. Next, an interlayer dielectric (ILD) 164 is formed on the contact etch stop layer 162 above the semiconductor device structure 100. The material of the interlayer dielectric 164 can include compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, or SiOC. An organic material such as a polymer can also be used for the interlayer dielectric 164. Depositing the interlayer dielectric 164 can be accomplished by a plasma-enhanced chemical vapor deposition process or other suitable deposition techniques. In some embodiments, after forming the interlayer dielectric 164, the semiconductor device structure 100 can undergo a thermal process to anneal the interlayer dielectric 164.

[0086] After forming the interlayer dielectric 164, a planarization step such as chemical mechanical polishing is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed, as Figure 10 shown.

[0087] According to some embodiments, Figure 11A and Figure 11Bare cross-sectional top views of the semiconductor device structure 100 along Figure 10 lines B-B and C-C, respectively. Figure 11A is a cross-sectional top view of a portion of the semiconductor device structure 100 along line B-B, which spans the bottommost second semiconductor layer 108. As Figure 11A shown, a second corner portion 134b remains in a position adjacent to the bottommost second semiconductor layer 108. In some embodiments, due to the presence of the second corner portion 134b of the sacrificial gate electrode layer 134, a portion of the first gate spacer 138A includes a straight portion contacting the sidewall of the sacrificial gate electrode layer 134 and an end portion contacting the source / drain region 146, and an angle B is formed between the straight portion and the end portion. In some embodiments, because of the presence of the second corner portion 134b, the angle B is an obtuse angle, as Figure 11A shown. For example, the angle B can be in the range of about 105 degrees to about 130 degrees. In some embodiments, the angle B is less than 130 degrees. If the angle B is greater than about 130 degrees, the gap between the first gate spacer 138A and the first sacrificial layer 103 may be too large. As a result, the first sacrificial layer 103 may be removed during the removal of the sacrificial gate stack 130, exposing the source / drain region 146. When the angle B is less than about 130 degrees, the gap between the first gate spacer 138A and the first sacrificial layer 103 is small, and the portion of the first sacrificial layer 103 contacting the source / drain region 146 is not removed during the removal of the sacrificial gate stack 130. In addition, due to the small gap between the first gate spacer 138A and the first sacrificial layer 103, the process window for removing the sacrificial gate stack 130 can be expanded.

[0088] Figure 11B is a cross-sectional top view of a portion of the semiconductor device structure 100 along line C-C, which spans the topmost second semiconductor layer 108. As Figure 11B shown, the second corner portion 134b does not appear in a position adjacent to the topmost second semiconductor layer 108. Due to the absence of the second corner portion 134b, a portion of the first sacrificial layer 103 is removed during a wet cleaning or an etching process for removing the first sacrificial layer 103 not covered by the sacrificial gate electrode layer 134. As a result, the first sacrificial layer 103 is not located between the gate spacer 138 and the dielectric spacer 144. As a result, the angle B between the straight portion and the end portion of the first gate spacer 138A is less than the angle B adjacent to the bottommost second semiconductor layer 108 (as Figure 11A)。In some embodiments, the angle B adjacent to the topmost second semiconductor layer 108 is a right angle. The angle B adjacent to the middle second semiconductor layer 108 can be between the angle B adjacent to the topmost second semiconductor layer 108 and the angle B adjacent to the bottommost second semiconductor layer 108. In other words, the angle B increases in the direction towards the substrate 101.

[0089] As Figure 12 shown, the sacrificial gate structure 130 and the second semiconductor layer 108 are removed. Removing the sacrificial gate structure 130 and the second semiconductor layer 108 forms openings between the gate spacers 138 and openings between the first semiconductor layers 106. During the removal process, the interlayer dielectric layer 164 protects the source / drain regions 146. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. Any suitable process can be used to first remove the sacrificial gate electrode layer 134, such as dry etching, wet etching, or a combination of the above, and then any suitable process can be performed to remove the exposed portion of the first sacrificial layer 103, such as dry etching, wet etching, or a combination of the above. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide solution can be used to selectively remove the sacrificial gate electrode layer 134 without removing the gate spacers 138, the interlayer dielectric layer 164, and the contact etch stop layer 162.

[0090] A selective wet etching process can be used to remove part of the second semiconductor layer 108. In an example where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of Si, the chemical agent used in the selective wet etching process removes SiGe but substantially does not affect Si, the dielectric material of the gate spacers 138, and the dielectric spacers 144. In one embodiment, removing the second semiconductor layer 108 can use a wet etchant such as, but not limited to, hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), phosphoric acid (H3PO4), a dry etchant such as a fluorine-based gas (such as F2) or a chlorine-based gas (such as Cl2), or any suitable isotropic etchant.

[0091] After forming the nanostructured channel (i.e., the exposed portion of the first semiconductor layer 106), a gate dielectric layer 170 is formed surrounding the exposed portion of the first semiconductor layer 106, and a gate electrode layer 172 is formed on the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 may be collectively referred to as a gate structure 174. In some embodiments, an interfacial layer (IL) (not shown) is formed between the gate dielectric layer 170 and the exposed surface of the first semiconductor layer 106. In some embodiments, the gate dielectric layer 170 includes one or more layers of dielectric material, such as silicon oxide, silicon nitride, or high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium oxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 170 may be formed by chemical vapor deposition, atomic layer deposition, or any suitable deposition technique. The gate electrode layer 172 may include one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloy, other suitable materials, and / or any combination of the above. The gate electrode layer 172 may be formed by chemical vapor deposition, atomic layer deposition, electroplating, or other suitable deposition techniques. The gate electrode layer 172 may also be deposited above the upper surface of the interlayer dielectric layer 164. Then, the gate dielectric layer 170 and the gate electrode layer 172 formed above the interlayer dielectric layer 164 are removed using, for example, chemical mechanical polishing until the top surface of the interlayer dielectric layer 164 is exposed.

[0092] According to some embodiments, Figure 13A and Figure 13B are cross-sectional top views of the semiconductor device structure 100 along Figure 12 lines D-D and E-E, respectively. Figure 13A is a cross-sectional top view of a portion of the semiconductor device structure 100 along line D-D, which spans a portion of the gate electrode layer 172 located below the bottommost first semiconductor layer 106. As Figure 13A shown, a portion of the first sacrificial layer 103 between the gate spacer 138 and the dielectric spacer 144 is retained and separates the gate dielectric layer 170 and the source / drain regions 146. In some embodiments, the thickness of the portion of the first sacrificial layer 103 between the gate spacer 138 and the dielectric spacer 144 along the Y direction is less than about 1 nanometer, such as about 0.3 nanometer to about 1 nanometer. In some embodiments, the first sacrificial layer 103 contacts the source / drain regions 146, the first gate spacer 138A, and the dielectric spacer 144.

[0093] Figure 13B is a top cross-sectional view of a partial semiconductor device structure 100 along line E-E, which spans a partial gate electrode layer 172 located below the topmost first semiconductor layer 106. As Figure 13B shown, the gate spacer 138 and the dielectric spacer 144 separate the gate dielectric layer 170 from the source / drain region 146. In some embodiments, the thickness of the gate spacer 138 (the combined thickness of the first gate spacer 138A and the second gate spacer 138B) can range from about 5 nanometers to about 10 nanometers, and the thickness of the dielectric spacer 144 can be the same as the thickness of the gate spacer 138. Since there is such a thick dielectric material between the gate dielectric layer 170 and the source / drain region 146, the risk of electrical short circuit between the gate electrode layer 172 and the source / drain region 146 can be reduced. Additionally, since the gate spacer 138 contacts the dielectric spacer 144, the process window for removing the sacrificial gate stack 130 can be enlarged. For example, when removing the sacrificial gate electrode layer 134, the portion of the first sacrificial layer 103 covered by the sacrificial gate electrode layer 134, and the second semiconductor layer 108, the risk of exposing the source / drain region 146 can be reduced.

[0094] Embodiments of the present disclosure provide a semiconductor device structure 100 including a first gate spacer 138A, where the first gate spacer 138A includes a straight portion and a terminal portion located at different positions, and different angles B are formed between the straight portion and the corresponding terminal portion. Some embodiments can achieve advantages. For example, the process of forming the semiconductor device structure 100 can have an enlarged process window for removing the sacrificial gate stack 130. In addition, the risk of electrical short circuit between the gate electrode layer 172 and the source / drain region 146 can be reduced.

[0095] An embodiment of the present disclosure is a semiconductor device structure. The semiconductor device structure includes a source / drain region above a substrate, and the source / drain region includes a first portion and a second portion above the first portion. The semiconductor device structure further includes a gate electrode layer above the substrate, and the gate electrode layer includes a first portion and a second portion above the first portion. The semiconductor device structure further includes a first gate spacer disposed between the gate electrode layer and the source / drain region, and the first gate spacer includes a first portion and a second portion above the first portion. The semiconductor device structure further includes a dielectric spacer disposed between the gate electrode layer and the source / drain region, and the dielectric spacer includes a first portion and a second portion above the first portion, where the second portion of the dielectric spacer contacts the second portion of the first gate spacer. The semiconductor device structure further includes a sacrificial layer disposed between the first portion of the first gate spacer and the first portion of the dielectric spacer.

[0096] In some embodiments, the sacrificial layer contacts a first portion of the source / drain region. In some embodiments, the semiconductor device structure further includes a gate dielectric layer, wherein the gate dielectric layer includes a first portion and a second portion over the first portion, and the first portion of the gate dielectric layer is disposed between the sacrificial layer and the first portion of the gate electrode layer. In some embodiments, the second portion of the gate dielectric layer contacts the second portion of the first gate spacer and the second portion of the dielectric spacer. In some embodiments, the semiconductor device structure further includes a second gate spacer, wherein the second gate spacer includes a first portion and a second portion over the first portion. In some embodiments, the combined thickness of the first portion of the first gate spacer and the first portion of the second gate spacer ranges from about 5 nanometers to about 10 nanometers. In some embodiments, the first portion of the dielectric spacer has a thickness ranging from about 5 nanometers to about 10 nanometers.

[0097] Another embodiment of the present disclosure is a semiconductor device structure. The semiconductor device structure includes a source / drain region disposed over a substrate, and the source / drain region includes a first portion and a second portion over the first portion. The semiconductor device structure further includes a gate electrode layer over the substrate, and the gate electrode layer includes a first portion and a second portion over the first portion. The semiconductor device structure further includes a first gate spacer disposed between the gate electrode layer and the source / drain region, and the first gate spacer includes a first portion and a second portion over the first portion. The first portion includes a first main portion, a first end portion, and a first angle formed between the first main portion and the first end portion. The second portion includes a second main portion, a second end portion, and a second angle formed between the second main portion and the second end portion. The second angle is different from the first angle.

[0098] In some embodiments, the first angle is an obtuse angle, and the second angle is a right angle. In some embodiments, the first angle ranges from 105 degrees to about 130 degrees. In some embodiments, the semiconductor device structure further includes a first semiconductor layer and a second semiconductor layer above the first semiconductor layer, wherein a first portion of the gate electrode layer is located below the first semiconductor layer, and a second portion of the gate electrode layer is located above the second semiconductor layer. In some embodiments, a first portion of the first gate spacer is disposed between the first portion of the gate electrode layer and the first portion of the source / drain region, and a second portion of the first gate spacer is disposed between the second portion of the gate electrode layer and the second portion of the source / drain region. In some embodiments, the semiconductor device structure further includes a sacrificial layer, wherein the sacrificial layer contacts the first portion of the source / drain region and the first portion of the first gate spacer. In some embodiments, the semiconductor device structure further includes a second gate spacer, wherein the second gate spacer includes a first portion and a second portion above the first portion. In some embodiments, the combined thickness of the first portion of the first gate spacer and the first portion of the second gate spacer ranges from about 5 nanometers to about 10 nanometers.

[0099] A further embodiment of the present disclosure is a method of forming a semiconductor device structure. The method includes forming a fin structure from a substrate, depositing a first sacrificial layer around the fin structure, depositing a second sacrificial layer on the first sacrificial layer, and performing a first etching process to form a sacrificial gate electrode layer. A by-product layer is formed on the sacrificial gate electrode layer, and each of the sacrificial gate electrode layer and the by-product layer includes one or more corner portions. The method further includes performing a second etching process to remove one or more corner portions of the by-product layer and expose one or more corner portions of the sacrificial gate electrode layer, performing a third etching process to remove at least one of the one or more corner portions of the sacrificial gate electrode layer, removing a portion of the fin structure to expose a well portion, and forming source / drain regions from the exposed well portion.

[0100] In some embodiments, the method further includes performing a wet clean to remove the by-product layer after performing the third etching process. In some embodiments, the first etching process uses a first etchant, the second etching process uses a second etchant different from the first etchant, and the third etching process uses a third etchant different from the first etchant and the second etchant. In some embodiments, the first etchant is a chlorine-based etchant, the second etchant includes HF, NH3, or a combination thereof, and the third etchant includes H2. In some embodiments, the third etching process recesses at least one of the one or more corner portions of the sacrificial gate electrode layer.

[0101] Another embodiment of the present disclosure is a semiconductor device structure. The semiconductor device structure includes source / drain regions above a substrate, wherein the source / drain regions include a first portion and a second portion above the first portion. The semiconductor device structure further includes a gate electrode layer above the substrate, wherein the gate electrode layer includes a first portion and a second portion above the first portion. The semiconductor device structure further includes a first gate spacer disposed between the gate electrode layer and the source / drain regions, wherein the first gate spacer includes a first portion and a second portion above the first portion. The semiconductor device structure further includes a second gate spacer disposed between the gate electrode layer and the source / drain regions, wherein the second gate spacer includes a first portion and a second portion above the first portion. The semiconductor device structure further includes a dielectric spacer disposed between the gate electrode layer and the source / drain regions, wherein the dielectric spacer includes a first portion and a second portion above the first portion, the second portion of the dielectric spacer contacts the second portion of the first gate spacer, and the combined thickness of the first portions of the first gate spacer and the second gate spacer is the same as the thickness of the first portion of the dielectric spacer.

[0102] The features of some embodiments are outlined above so that those skilled in the art may better understand the concepts of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for the same purpose and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device structure, characterized in that: include: A source / drain region above a substrate, wherein the source / drain region includes a first portion and a second portion above the first portion; a gate electrode layer above the substrate, wherein the gate electrode layer includes a first portion and a second portion above the first portion; a first gate spacer disposed between the gate electrode layer and the source / drain region, wherein the first gate spacer includes a first portion and a second portion above the first portion; a dielectric spacer disposed between the gate electrode layer and the source / drain region, wherein the dielectric spacer includes a first portion and a second portion above the first portion, and the second portion of the dielectric spacer contacts the second portion of the first gate spacer; and A sacrificial layer is disposed between the first portion of the first gate spacer and the first portion of the dielectric spacer.

2. The semiconductor device structure according to claim 1, wherein: The sacrificial layer contacts the first portion of the source / drain region.

3. The semiconductor device structure according to claim 1, wherein: The invention further comprises a gate dielectric layer, wherein the gate dielectric layer comprises a first portion and a second portion above the first portion, and the first portion of the gate dielectric layer is disposed between the sacrificial layer and the first portion of the gate electrode layer.

4. The semiconductor device structure according to claim 1, wherein: A second gate spacer is further included, wherein the second gate spacer includes a first portion and a second portion above the first portion.

5. The semiconductor device structure according to claim 4, wherein: Wherein the first portion of the first gate spacer and the first portion of the second gate spacer have a combined thickness in a range of 5 nanometers to 10 nanometers.

6. A semiconductor device structure, characterized in that: include: A source / drain region above a substrate, wherein the source / drain region includes a first portion and a second portion above the first portion; a gate electrode layer above the substrate, wherein the gate electrode layer includes a first portion and a second portion above the first portion; as well as A first gate spacer is disposed between the gate electrode layer and the source / drain region, wherein the first gate spacer includes a first portion and a second portion above the first portion, the first portion includes a first main portion, a first end portion and a first angle formed between the first main portion and the first end portion, and the second portion includes a second main portion, a second end portion and a second angle formed between the second main portion and the second end portion, wherein the second angle is different from the first angle.

7. The semiconductor device structure according to claim 6, wherein: The first angle is an obtuse angle, and the second angle is a right angle.

8. The semiconductor device structure according to claim 6, wherein: The invention further comprises a first semiconductor layer and a second semiconductor layer above the first semiconductor layer, wherein the first portion of the gate electrode layer is located below the first semiconductor layer, and the second portion of the gate electrode layer is located above the second semiconductor layer.

9. The semiconductor device structure according to claim 8, wherein: The first portion of the first gate spacer is disposed between the first portion of the gate electrode layer and the first portion of the source / drain region, and the second portion of the first gate spacer is disposed between the second portion of the gate electrode layer and the second portion of the source / drain region.

10. A semiconductor device structure, characterized in that: include: A source / drain region above a substrate, wherein the source / drain region includes a first portion and a second portion above the first portion; a gate electrode layer above the substrate, wherein the gate electrode layer includes a first portion and a second portion above the first portion; a first gate spacer disposed between the gate electrode layer and the source / drain region, wherein the first gate spacer includes a first portion and a second portion above the first portion; a second gate spacer disposed between the gate electrode layer and the source / drain region, wherein the second gate spacer includes a first portion and a second portion above the first portion; and a dielectric spacer disposed between the gate electrode layer and the source / drain region, wherein the dielectric spacer includes a first portion and a second portion above the first portion, and the second portion of the dielectric spacer contacts the second portion of the first gate spacer, The first portion of the first gate spacer and the first portion of the second gate spacer have a combined thickness that is the same as a thickness of the first portion of the dielectric spacer.

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