Image sensor and electronic device
By preparing multiple initial gate structures on the semiconductor substrate of the image sensor and performing the source-drain injection process in steps, the problem of single steps in the transistor preparation process in the prior art is solved, and diversified transistor design and performance improvement are achieved.
Patent Information
- Application Number
- CN202420644001.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-29
- Publication Date
- 2025-06-27
- Estimated Expiration
- 2034-03-29
AI Technical Summary
In the prior art, the transistor preparation process of image sensors has a single step and is difficult to prepare devices that meet different needs.
By preparing a plurality of initial gate structures on the first side of the semiconductor substrate, and performing the source-drain implantation process in steps based on these initial gate structures, the first and second transistor structures are formed, with different source-drain structures and channel distances respectively.
The diversified design of transistors is realized, which can meet different performance requirements, such as the demand for different electric field strengths, and improve the adaptability and performance diversity of image sensors.
Smart Images
Figure CN223040491U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of image acquisition, and particularly relates to an image sensor and an electronic device. Background Art
[0002] An image sensor is an important component of a digital camera. According to different components, it can be divided into two categories: CCD (Charge Coupled Device) and CMOS (Complementary Metal Oxide Semiconductor). With the continuous development of CMOS integrated circuit manufacturing technology, especially the design and manufacturing technology of CMOS image sensors, CMOS image sensors have gradually replaced CCD image sensors and become the mainstream. CMOS image sensors have the advantages of low voltage, low power consumption, low cost, and high integration, and have important application values in the fields of machine vision, consumer electronics, high-definition monitoring, and medical imaging.
[0003] However, in the preparation of existing image sensors, there are often problems such as a single process step, making it difficult to obtain devices with different requirements. For example, in the preparation process of transistors, the source and drain of traditional processes are formed after the spacer process, and the unified spacer serves as the blocking layer for the source and drain injection of the transistor. The corresponding source and drain structures of the obtained transistors are the same, and the performance of the corresponding transistors and the requirements that can be met are relatively similar, thus making it difficult to meet the requirements of the sensor for transistors with different structures and performances.
[0004] Therefore, it is necessary to provide an image sensor and an electronic device to solve the problems such as the single process step of the transistor preparation process of the sensor in the prior art, which is difficult to meet different requirements. Summary of the Utility Model
[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present utility model is to provide an image sensor and an electronic device, which are used to solve the problems such as the single process step of the transistor preparation process of the sensor and the single transistor structure in the prior art, which are difficult to meet different requirements.
[0006] To achieve the above purpose and other related purposes, the present utility model provides a preparation method for an image sensor, and the preparation method includes the following steps:
[0007] Provide a semiconductor substrate, and the semiconductor substrate has opposite first and second surfaces;
[0008] Prepare a plurality of initial gate structures on the semiconductor substrate from the first surface of the semiconductor substrate. Each initial gate structure includes an initial gate and an initial spacer located on the sidewall of the initial gate. Among them, at least a first gate structure and a second gate structure are defined based on the plurality of initial gate structures;
[0009] Perform a first source-drain implantation process from the first surface of the semiconductor substrate to obtain a first transistor structure, wherein the first source-drain implantation process is performed based on the first gate structure to form a first source-drain corresponding to the first gate structure and obtain the first transistor structure;
[0010] Prepare a sidewall improvement layer on the first surface of the semiconductor substrate and at least on the surface of the second gate structure, so as to obtain a second improved gate structure based on the sidewall improvement layer and the second gate structure;
[0011] Perform a second source-drain implantation process from the first surface of the semiconductor substrate to obtain a second transistor structure, wherein the second source-drain implantation process is performed based on the second improved gate structure to form a second source-drain corresponding to the second improved gate structure and obtain the second transistor structure.
[0012] The present invention also provides an image sensor, which is preferably prepared by using the preparation method of the image sensor of the present invention. Of course, it can also be prepared by other methods. The image sensor includes:
[0013] A semiconductor substrate having opposite first and second surfaces;
[0014] A first improved gate structure located on the first surface of the semiconductor substrate, including a first gate structure and a sidewall improvement layer located on the sidewall of the first gate structure;
[0015] A first source-drain located in the semiconductor substrate around the first improved gate structure, and having a first distance between the first source-drain and the first gate structure;
[0016] A second improved gate structure located on the first surface of the semiconductor substrate and having a spacing from the first improved gate structure, including a second gate structure and a sidewall improvement layer located on the sidewall of the second gate structure;
[0017] A second source-drain located in the semiconductor substrate around the second improved gate structure, and having a second distance different from the first distance between the second source-drain and the second gate structure.
[0018] The present invention also provides an electronic device including the image sensor according to any one of the above solutions.
[0019] As described above, the image sensor and electronic device of the present utility model design the preparation process and corresponding structure of the image sensor, so that the transistor can meet the requirements of different performances. For example, it can meet the requirements of the transistor for different electric field strengths. By adopting the method of forming the initial sidewall and the sidewall improvement layer step by step, the source and drain of different types of transistors can be obtained, so that the transistor has different structures, and the distance between the source and drain of the transistor and the channel of the transistor is different. Finally, transistors with different performances (such as electric field strength) can be obtained, which can meet the requirements of the transistor for different electric field strengths. Description of the Drawings
[0020] Figure 1 It is shown as a basic structural block diagram of an image sensor system.
[0021] Figure 2 It is shown as a schematic diagram of the pixel circuit of an image sensor.
[0022] Figure 3 It is shown as a process flow chart of the preparation of the image sensor provided by the embodiment of the present application.
[0023] Figures 4 to 14 It is shown as a schematic diagram of the structure obtained in each step in the preparation of the image sensor provided by the embodiment of the present application. Among them, Figures 12 - 14 It is shown as the structural diagram after forming the first source-drain and the second source-drain.
[0024] Figure 15 It is shown as a schematic cross-sectional structure diagram of a pixel unit provided by the embodiment of the present application.
[0025] Figure 16 It is shown as a schematic top view structure diagram of another pixel unit provided by the embodiment of the present application.
[0026] Figure 17 It is shown as an image sensor having a pixel region and a peripheral logic region provided by the embodiment of the present application.
[0027] Description of Component Labels
[0028] 101 - Semiconductor substrate; 102 - Initial gate; 103a, 103b - Initial doping regions; 104 - Sidewall material layer; 105 - Initial sidewall; 106a, 506a - First gate structure; 106b, 506b - Second gate structure; 106c - First improved gate structure; 106d - Second improved gate structure; 107 - First source-drain; 108 - Sidewall improvement layer; 109 - Second source-drain; 110 - Interlayer dielectric layer; 111 - Improved sidewall; 201 - Isolation structure; 301 - First mask layer; 401 - Second mask layer; 601 - Pixel region; 602 - Peripheral logic region. Detailed Embodiments
[0029] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0030] It should be emphasized that the term "comprising / including" when used herein refers to the presence of features, whole, steps or components, but does not exclude the presence or addition of one or more other features, whole, steps or components.
[0031] Features described and / or illustrated for one embodiment can be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or replace features in other embodiments. When detailing the embodiments of the present invention, for ease of illustration, the cross-sectional views showing the device structure are enlarged locally not in accordance with the general scale. The schematic diagrams are only examples and should not limit the scope of protection of the present invention herein. In actual production, the three-dimensional spatial dimensions of length, width and depth should be included.
[0032] For ease of description, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers. The structure in which the described first feature is "above" the second feature can include embodiments where the first and second features are formed in direct contact, and can also include embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, "coupled" means that it can be directly or indirectly connected.
[0033] The illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation. The type, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex. The following details the content proposed by the present invention with reference to the accompanying drawings.
[0034] Figure 1Shown is a basic structural block diagram of an image sensor system. The image sensor includes a readout circuit and a control circuit connected to a pixel array. Additionally, a functional logic unit is connected to the readout circuit, and the readout circuit and the control circuit are connected to a status register to enable control of the pixel array. The pixel array includes a plurality of pixels (P1, P2, P3) arranged in rows (R1, R2, R3…Ry) and columns (C1, C2, C3…Cx), and the pixel signals output by the pixel array are output to the readout circuit via column lines. In some applications, after the pixels acquire image data, they are read out in a readout mode specified by the status register and then transmitted to the functional logic unit. In a specific implementation, the readout circuit may include an analog-to-digital conversion (ADC) circuit and other circuits.
[0035] In certain applications, the status register may include a programmed selection system for determining whether the readout system exposes and reads out through a rolling shutter mode or a global shutter mode. The functional logic unit may store the original image data or the image data after image processing. In some implementations, the readout circuit may read out one row of image data along the readout column lines at a time. Of course, other methods may also be used to read out the image data. The operation of the control circuit can be determined by the current settings of the status register. For example, the control circuit generates a shutter signal for controlling image acquisition. In some applications, this shutter signal may be a global exposure signal, enabling all pixels of the pixel array to simultaneously acquire their image data through a single acquisition window. In other applications, this shutter signal may also be a rolling exposure signal, enabling the pixels of each pixel row of the pixel array to continuously perform exposure reading operations through the acquisition window.
[0036] Figure 2 Shown is a schematic diagram of a pixel unit in an image sensor. As Figure 2 shown, each pixel unit includes a photoelectric conversion element (e.g., a photodiode PD) and a pixel circuit (shown as the transistors within the dashed box in the figure). The photodiode may be a buried photodiode (PPD) used in the current image sensor. In an application example, the pixel circuit includes a reset transistor (RST), a source follower transistor (SF), and a pixel selection transistor (RS), connected to as Figure 2The transfer transistor (TX) and photodiode shown in [figure]. In an application example of a stacked structure, the pixel circuit includes a reset transistor, a source follower transistor, and a pixel selection transistor disposed on a first circuit chip, and further includes a transfer transistor disposed on a second circuit chip. The photodiode in the second circuit chip is connected to other transistors in the first circuit chip based on the transfer transistor. In a further application example, the pixel circuit may further include a gain control transistor (DCG) connected between a floating diffusion region (FD) and the reset transistor. During operation, the photoelectric conversion element generates photo charges in response to incident light during exposure. The transfer transistor connects a transfer signal, which controls the transfer transistor to transfer the charges accumulated in the photoelectric conversion element to the floating diffusion region. The reset transistor is connected between the power supply voltage and the floating diffusion region, and responds to a reset signal to reset the sensor pixel circuit (for example, discharge or charge the floating diffusion region and the photodiode to the current voltage). The floating diffusion region is connected to the gate of the source follower transistor. The source follower transistor is connected between the power supply voltage and the pixel selection transistor, responds to the potential of the floating diffusion region and outputs it. The pixel selection transistor connects the source follower transistor and the bit line, and realizes pixel selection readout in response to a pixel selection control signal and outputs it to the readout column.
[0037] However, with the rapid development of image sensors, the demand for some devices with combined performance is continuously increasing. In existing technology image sensors, there are often problems such as a single preparation process step, and it is difficult to obtain devices with different performance requirements. For example, in the preparation process of transistors, the source and drain formation in traditional processes is all after the spacer process. The unified spacer is used as the blocking layer for the source and drain injection of the transistor, and the obtained source and drain structures of the transistors are the same. The performance of the corresponding transistors and the requirements that can be met are relatively similar, and it is difficult to meet the requirements of the sensor for transistors with different structures and performances. For example, it is difficult for transistors to meet the requirements for different electric field intensities, so the transistors in the sensor are difficult to effectively adapt to different electric field intensities. Through the improvement of the preparation and structure of the image sensor in this application, the above problems can be effectively improved.
[0038] Embodiment 1:
[0039] Please refer to Figures 3 to 17 shown. This embodiment provides a method for preparing an image sensor, Figure 3 shown as a flowchart of this preparation method. The preparation method includes the following steps:
[0040] S1: Provide a semiconductor substrate, and the semiconductor substrate has opposite first and second surfaces;
[0041] S2: Prepare a plurality of initial gate structures on the semiconductor substrate from the first surface of the semiconductor substrate. Each of the initial gate structures includes an initial gate and an initial sidewall located on the sidewall of the initial gate. Among them, at least a first gate structure and a second gate structure are defined based on the plurality of initial gate structures;
[0042] S3: Perform a first source-drain implantation process from the first surface of the semiconductor substrate to obtain a first transistor structure. Among them, the first source-drain implantation process is performed based on the first gate structure to form a first source-drain corresponding to the first gate structure and obtain the first transistor structure;
[0043] S4: Prepare a sidewall improvement layer on the first surface of the semiconductor substrate and at least on the surface of the second gate structure to obtain a second improved gate structure based on the sidewall improvement layer and the second gate structure;
[0044] S5: Perform a second source-drain implantation process from the first surface of the semiconductor substrate to obtain a second transistor structure. Among them, the second source-drain implantation process is performed based on the second improved gate structure to form a second source-drain corresponding to the second improved gate structure and obtain the second transistor structure.
[0045] It should be noted that the preparation sequence corresponding to the existing process in the above steps can be changed according to actual needs, as long as the beneficial effects of the present application can be achieved, and it is not limited to the order of S1 to S5 above.
[0046] Next, the preparation of the image sensor according to the embodiment of the present application will be described in detail with reference to specific drawings.
[0047] First, as Figure 3 in S1 and Figure 4 shown, perform step S1 to provide a semiconductor substrate 101, and the semiconductor substrate 101 has opposite first surface 101a and second surface 101b.
[0048] Specifically, the semiconductor substrate 101 has opposite first surface 101a (front side) and second surface 101b (back side). The semiconductor substrate 101 may be a structure composed of a single-layer material layer, including but not limited to a silicon substrate, and its material may be single-crystalline silicon, single-crystalline germanium, polycrystalline silicon, amorphous silicon, or a silicon-germanium compound. Of course, the semiconductor substrate 101 may also be a silicon-on-insulator (SOI), etc. In addition, the semiconductor substrate 101 may also have N-type doped or P-type doped regions to meet actual requirements.
[0049] In addition, the semiconductor substrate 101, being the substrate of the image sensor, can also be a multi-layer structure, such as including a semiconductor substrate and an epitaxial layer formed on the surface of the semiconductor substrate. In this case, the epitaxial layer serves as the device functional layer to realize the preparation of the device of the image sensor. Moreover, in other embodiments, the semiconductor substrate 101 can be any structure in the field of image sensors used for preparing the functional regions of the image sensor. The photosensitive elements, various transistors of the CMOS image sensor, and interconnection wiring, etc. can be fabricated based on the semiconductor substrate 101.
[0050] In one example, the semiconductor substrate 101 includes a device functional layer, and the device functional layer has doping of a first doping type. Additionally, it can also be that the semiconductor substrate 101 itself has doping of the first doping type, and the preparation of the image sensor device can be carried out based on the region of the first doping type. In this embodiment, it is described with the first doping type being P-type to obtain an image sensor of the corresponding type. Of course, in other examples, the first doping type can also be set as N-type according to the actual situation for different types of image sensors.
[0051] Specifically, the device functional layer can be a part of the semiconductor substrate 101. For example, it can be a P-type epitaxial layer (EPI) formed on a semiconductor substrate (such as a silicon substrate). The epitaxial layer can be directly formed by an epitaxial process or formed by other methods of existing processes. At this time, the semiconductor substrate and the epitaxial layer constitute the semiconductor substrate 101, and the epitaxial layer serves as the device functional layer. Among them, in one implementation, each functional region (including semiconductor devices) in the image sensor is fabricated in the device functional layer. In other examples, it can also be considered that the entire semiconductor substrate 101 is a device functional layer of the first doping type. At this time, the functional regions in the image sensor can be fabricated in the semiconductor substrate 101. Of course, if necessary, the structures required for the image sensor can also be fabricated in the semiconductor substrate or other material layers. Further, a back-illuminated image sensor can be fabricated based on this semiconductor substrate and the device functional layer.
[0052] It should be noted that for the convenience of description and to show the relationships between various structures and regions during the preparation process of the image sensor, the semiconductor substrate 101 in each drawing of this embodiment can be directly understood as the device functional layer, the first surface 101a of the semiconductor substrate 101 can be directly understood as the first surface of the device functional layer, and the second surface 101b of the semiconductor substrate 101 can be directly understood as the second surface of the device functional layer.
[0053] Next, as Figure 3 in S2 and Figures 5 - 8As shown, step S2 is performed to fabricate a plurality of initial gate structures 106 on the semiconductor substrate 101 from the first surface 101a of the semiconductor substrate 101. Each initial gate structure 106 includes an initial gate 102 and an initial spacer 105 located on the sidewalls of the initial gate 102. Among them, at least a first gate structure 106a and a second gate structure 106b are defined based on the plurality of initial gate structures 106.
[0054] As an example, the method for fabricating a plurality of initial gate structures 106 on the semiconductor substrate 101 includes:
[0055] First, as Figure 5 shown, a plurality of initial gates 102 are fabricated on the semiconductor substrate from the first surface 101a of the semiconductor substrate 101; among them, the initial gate 102 may include a gate oxide layer located on the surface of the semiconductor substrate 101 and a gate layer located on the gate oxide layer. The gate oxide layer includes but is not limited to silicon oxide, and the gate layer includes but is not limited to polysilicon. Subsequent MOS transistor structures can be obtained based on the initial gate 102.
[0056] Next, as Figure 6 shown, a doping implantation process is performed from the first surface 101a of the semiconductor substrate 101 to form initial doped regions 103a and 103b in the semiconductor substrate 101 around the initial gate 102; among them, the initial doped region 103a corresponds to the first transistor structure to be formed subsequently, and the initial doped region 103b corresponds to the second transistor structure to be formed subsequently. In this example, the concentrations of the respective initial doped regions may be the same, and the widths may be different. The initial doped regions may correspond to the source / drain structures to be formed subsequently and may be lightly doped drains (LDDs).
[0057] Finally, as Figures 7 - 8 shown, an initial spacer 105 is formed on the sidewalls of the initial gate 102. The initial spacer 105 extends to the adjacent initial doped regions, and the first source / drain 107 to be formed subsequently is formed corresponding to the initial doped region 103a, and the second source / drain 109 to be formed subsequently is formed corresponding to the initial doped region 103b.
[0058] In an alternative example, the method for forming the initial spacer 105 includes: forming a spacer material layer 104 on the exposed surface of the initial gate 102 and the surface of the semiconductor substrate 101 around the initial gate 102, as Figure 7 shown; further, an etching process is performed on the spacer material layer 104 to obtain the initial spacer 105 located on the sidewalls of the initial gate 102 and continuously extending to the initial doped regions, as Figure 8 shown.
[0059] In an example, the initial spacer includes at least one of an ONO (oxide - nitride - oxide) structure, an ON (oxide - nitride) structure, and an oxide layer.Figure 8 It is shown in the figure that the sidewall material layer 104 includes a silicon oxide material layer 104a and a silicon nitride material layer 104b, and the initial sidewall 105 is obtained by etching the two layers.
[0060] It should be noted that based on the requirements of the transistors obtained subsequently, at least the first gate structure 106a and the second gate structure 106b can be defined, so that transistors with different performances can be obtained based on different gate structures. Among them, multiple initial gate structures 106 can have the same material layer configuration. Further, different sizes can be configured according to different requirements. Of course, they can also have the same size and structure.
[0061] Next, as shown in Figure 3 S3 and 9 in the figure, step S3 is performed. A first source / drain implantation process (the first ion implantation in the figure) is performed from the first surface 101a of the semiconductor substrate 101 to obtain a first transistor structure. The first source / drain implantation process is performed based on the first gate structure 106a to form a first source / drain 107 corresponding to the first gate structure 106a and obtain a first transistor structure including the first gate structure 106a and the first source / drain 107.
[0062] As an example, the method of performing the first source / drain implantation process from the first surface of the semiconductor substrate 101 includes:
[0063] First, a first mask layer 301 is formed on the first surface 101a of the semiconductor substrate 101. The first mask layer 301 covers at least the second gate structure 106b and the ion implantation region corresponding to the second gate structure 106b. Among them, the first mask layer 301 includes, but is not limited to, a photoresist layer. In addition, the ion implantation region corresponding to the second gate structure 106b may include the region where the second source / drain 109 needs to be formed subsequently.
[0064] Next, a first source / drain 107 is formed in the semiconductor substrate 101 on the side of the first gate structure 106a based on the first mask layer 301 and the first gate structure 106a, and a first transistor structure is obtained. That is to say, in this step, under the shielding of the first mask layer 301, the first source / drain 107 is formed based on the initial sidewall 105 corresponding to the first gate structure 106a as a blocking layer. That is to say, the size of the initial sidewall 105 defines the distance between the side of the first source / drain 107 close to the first gate structure 106a and the first gate structure 106a, so that there is a first channel distance between the first source / drain 107 and the channel of the first transistor structure.
[0065] Next, as shown in Figure 3 S4 and Figure 10As shown, step S4 is performed to prepare a sidewall improvement layer 108 on the first surface 101a of the semiconductor substrate 101 and at least on the surface of the second gate structure 106b, so as to obtain a second improved gate structure based on the sidewall improvement layer 108 and the second gate structure 106b.
[0066] In an optional example, the step of preparing a sidewall improvement layer on at least the surface of the second gate structure includes:
[0067] A continuous sidewall improvement layer 108 is formed on the surface of the first gate structure 106a, the surface of the second gate structure 106b, and the surface of the semiconductor substrate 101 around the two; wherein, the second gate structure 106b and the sidewall improvement layer 108 located on the sidewall of the second gate structure 106b and extending to the surface of the semiconductor substrate 101 constitute the second improved gate structure, and the initial sidewall 105 and the sidewall improvement layer 108 together serve as the improved sidewall.
[0068] As an example, the structure of the sidewall improvement layer 108 includes at least one of a silicon oxide layer and a silicon nitride layer; that is, it can be composed of any one of the two, or a stacked structure composed of the two.
[0069] As an example, the formation method of the sidewall improvement layer 108 includes at least one of a chemical vapor deposition process CVD and a furnace tube deposition process; the above processes are beneficial to forming the sidewall improvement layer 108 on the surface of the semiconductor substrate 101, so that it can serve as a sidewall together with the initial sidewall 105, facilitating the implementation of subsequent processes.
[0070] As an example, the thickness of the sidewall improvement layer 108 is between 1 / 4 and 2 / 3 of the thickness of the initial sidewall 105. For example, it can be selected as 1 / 3, 1 / 2, etc., which is beneficial to the stability of the overall improved sidewall.
[0071] As an example, the thickness of the sidewall improvement layer 108 is between 50 Å and 500 Å, such as it can be 100 Å.
[0072] Finally, as Figure 3 in S5 and Figures 11 - 12 shown, step S5 is performed to perform a second source / drain implantation process (the second ion implantation in the figure) from the first surface of the semiconductor substrate to obtain a second transistor structure. Among them, the second source / drain implantation process is performed based on the second improved gate structure to form a second source / drain 109 corresponding to the second improved gate structure and obtain a second transistor structure including the second improved gate structure and the second source / drain.
[0073] As an example, the method of performing the second source / drain implantation process from the first surface of the semiconductor substrate 101 includes:
[0074] First, a second mask layer 401 is formed on the first surface 101a of the semiconductor substrate 101. The second mask layer 401 covers at least the first gate structure 106a and the first source / drain 107 corresponding to the first gate structure 106a. Among them, the second mask layer 401 includes, but is not limited to, a photoresist layer.
[0075] Next, a second source / drain 109 is formed in the semiconductor substrate 101 on the side of the second improved gate structure based on the second mask layer 401 and the second improved gate structure, and a second transistor structure is obtained, as Figure 11 shown. That is to say, in this step, under the shielding of the second mask layer 401, based on the initial sidewall 105 corresponding to the second improved gate structure and the sidewall improvement layer 108 as a whole sidewall as a blocking layer, the second source / drain 109 is formed. That is to say, the size of the whole sidewall of the initial sidewall 105 and the sidewall improvement layer 108 defines the distance between the side of the second source / drain 109 close to the second gate structure 106b and the second gate structure 106b, so that there is a relatively large second channel distance between the second source / drain 109 and the channel of the second transistor structure.
[0076] Finally, the second mask layer 401 is removed, as Figure 12 shown, and at least two transistor structures are obtained.
[0077] It should be noted that in this application, the first transistor structure and the second transistor structure are obtained based on the above process. Among them, the source / drains corresponding to the two have different distances from their own channels, so they have different electric field intensities. For example, the distance between the first source / drain of the first transistor structure and the channel is small, and it has a relatively large electric field intensity. However, the distance between the second source / drain of the second transistor structure and the channel is large, that is, the second distance is greater than the first distance, so it has a relatively small electric field intensity. Therefore, the two have different electric field intensities and can be applied to different requirements. For example, using a smaller field strength can improve G IDLE.
[0078] As an example, the depth and / or concentration of the initial doping region 103a is less than that of the first source / drain 107. As an example, the depth and / or concentration of the initial doping region 103b is less than that of the second source / drain 109. Thus, an effective potential gradient can be formed based on the adjustment of their concentrations and / or depths, which is beneficial to the operation of the corresponding transistors.
[0079] As an example, the depth and / or concentration of the first source / drain 107 is equal to that of the second source / drain 109.
[0080] Please refer to Figure 13 shown. As an example, after forming the second source / drain 109, the following steps are further included:
[0081] A interlayer dielectric layer 110 is formed on the surface of the sidewall improvement layer 108 to prepare an electrical interconnection structure based on the sidewall improvement layer 108 and the interlayer dielectric layer 110, so as to obtain an image sensor. In this example, the entire sidewall improvement layer 108 serves as a material layer of the subsequent image sensor, which can simplify the process and save costs. In addition, the corresponding first transistor structure and second transistor structure both have an initial gate 102, an initial sidewall 105, and a sidewall improvement layer 108, thereby improving the structural stability of the transistors of the image sensor.
[0082] Please refer to Figure 14 As shown, as an example, after forming the second source / drain 109, the method further includes the steps of:
[0083] Removing the sidewall improvement layer 108 on the surface of the semiconductor substrate 101 and on the top of each gate structure, and retaining the sidewall improvement layer 108 on the sidewalls of the first gate structure 106a and the second gate structure 106b to obtain an improved sidewall 111, so as to form a first improved gate structure 106c including the first gate structure 106a and the improved sidewall 111, and a second improved gate structure 106d including the second gate structure 106b and the improved sidewall 111 on the semiconductor substrate.
[0084] In this example, a part of the sidewall improvement layer 108 serves as a material layer of the subsequent image sensor, which can simplify the subsequent processes on the surface of the exposed semiconductor substrate. For example, a contact layer for forming an interconnection contact and a corresponding interconnection contact CT can be continuously formed. In addition, the corresponding first transistor structure and second transistor structure both have an initial gate 102, an initial sidewall 105, and a sidewall improvement layer 108, thereby improving the structural stability of the transistors of the image sensor.
[0085] Please refer to Figure 15 and Figure 16 As shown, the image sensor includes a plurality of pixel units arranged in an array. Each pixel unit includes a photoelectric conversion element 202, a transfer transistor, a floating diffusion region, and at least one pixel circuit transistor. Among them, the transfer transistor corresponds to the second gate structure, and the pixel circuit transistor corresponds to the first gate structure. Optionally, the pixel circuit transistor can be a reset transistor RST, as Figure 15 shown.
[0086] In this example, the transfer transistor corresponds to the second gate structure, and the floating diffusion region corresponds to the second source / drain. Thus, the electric field strength can be reduced based on the distance between the channel of the relatively large transfer transistor and the floating diffusion region. Further, due to the potential difference between the transfer transistor and the floating diffusion region during the operation of the image sensor, the potential of the floating diffusion region is higher than that under the transfer transistor, resulting in the problem of gate-induced drain current. Based on the design method of this application, the distance between the floating diffusion region and the channel of the transfer transistor can be increased, so that a relatively small electric field can be achieved compared with other pixel circuit transistors, and the above problem can be improved.
[0087] As Figure 16 shown, a shared pixel unit structure is provided. A pixel unit includes four photoelectric conversion elements PD1-4 and corresponding transfer transistors TX1-4 one by one. Among them, the pixel circuit transistors in the pixel unit include a source follower transistor SF, a reset transistor RST, and a pixel selection transistor RS. Further, the pixel circuit transistors may further include a gain control transistor DCG. In addition, the floating diffusion region includes two floating diffusion nodes FD1 and FD2, which are respectively located on both sides of the source follower transistor SF and shared by two transfer transistors. For example, transfer transistors TX1 and TX3 share the floating diffusion node FD1, and transfer transistors TX2 and TX4 share the floating diffusion node FD2. Further, the combination formed by the reset transistor RST and the gain control transistor DCG and the pixel selection transistor RS are respectively arranged between the corresponding rows and columns of the source follower transistor SF.
[0088] In this example, the transfer transistors TX1-4 correspond to the second gate structure 506b, and the source follower transistor SF, the reset transistor RST, the pixel selection transistor RS, and the gain control transistor DCG correspond to the first gate structure 506a.
[0089] Please refer to Figure 17 shown. As an example, the image sensor 600 includes a pixel region 601 and a peripheral logic region 602. The peripheral logic region 602 includes a plurality of logic circuit transistors. Among them, the logic circuit transistors may include a first transistor structure and a second transistor structure, that is, they may have different source / drain and channel distances, so as to meet the requirements of the transistors for different electric field strengths.
[0090] In one example, the pixel circuit corresponding to the pixel unit in the pixel region may have at least one of the first transistor structure and the second transistor structure, and the logic circuit transistors in the peripheral logic region may have at least one of the first transistor structure and the second transistor structure. Among them, when the same type of transistors exist in two different regions, the same type of transistors may be fabricated based on the same process.
[0091] Please refer toFigures 5 - 16 As shown, before forming the initial gate from the first surface of the semiconductor substrate, the following steps are further included:
[0092] Prepare an isolation structure 201 in the semiconductor substrate 101 from the first surface 101a of the semiconductor substrate 101, and define the positions of the first source / drain 107 and / or the second source / drain 109 based on the isolation structure 201. The side of the first source / drain and / or the second source / drain away from the corresponding gate structure is arranged adjacent to the isolation structure 201.
[0093] In an example, before forming the initial gate 102, an isolation structure 201 is formed in the provided semiconductor substrate 101. The isolation structure 201 includes, but is not limited to, a shallow trench isolation structure STI. The position of the isolation structure 201 can be defined based on the subsequent need to form the first transistor structure and the second transistor structure, such that there is a first distance d1 between the isolation structure 201 and the initial gate 102 of the first gate structure 106a. Thus, based on the first distance d1, the subsequent corresponding initial doping region 103a and the first source / drain 107 can be formed, and there is a second distance d2 between the isolation structure 201 and the initial gate 102 of the second gate structure 106b. Thus, based on the second distance d2, the subsequent corresponding initial doping region 103b and the second source / drain 109 can be formed.
[0094] As an example, the distance d2 between the isolation structure 201 and the initial gate of the second gate structure 106b is greater than the distance d1 between the isolation structure 201 and the initial gate of the first gate structure 106a; this is beneficial for forming the second source / drain of the channel that is further away from the second gate structure 106b subsequently, and is convenient for reducing the electric field strength.
[0095] In an alternative example, as Figure 6 shown, after defining the first distance d1 and the second distance d2 based on the isolation structure, when performing initial doping to form the initial doping regions 103a and 103b, the width of the initial doping layer 103a corresponding to the first gate structure 106a is the width s1 corresponding to the first distance d1, and the width of the initial doping layer 103b corresponding to the second gate structure 106b is the width s2 corresponding to the second distance d2.
[0096] In an alternative example, as Figure 12 shown, after defining the first distance d1 and the second distance d2 based on the isolation structure, further, after forming the initial doping region 103a with a width of s1 and the initial doping region 103b with a width of s2, further based on the formation of the sidewall improvement layer 108, a first source / drain 107 with a distance t1 from the corresponding initial gate 102 is formed corresponding to the first gate structure 106a, and a second source / drain 109 with a distance t2 from the corresponding initial gate 102 is formed corresponding to the second gate structure 106b.
[0097] As an example, the distance t2 between the second source / drain 109 and the corresponding initial gate 102 is greater than the distance t1 between the first source / drain 107 and the corresponding initial gate 102, so that the second source / drain 109 is farther from the channel of the second gate structure 106b, which is beneficial to reducing the electric field strength therebetween.
[0098] As an example, the width w of the first source / drain 107 is equal to the width w of the second source / drain 109. Of course, they may also have different widths. In this example, the distances between the first source / drain and the second source / drain and the corresponding channels can be flexibly improved, and the size configuration of the source / drain may not be affected, and they can be configured with equal widths.
[0099] As an example, the depths of both the first source / drain 107 and the second source / drain 109 are less than the depth of the isolation structure 201. Further, the depths of the corresponding initial doping regions 103a and 103b are also less than the depth of the isolation structure 201. This is beneficial to the normal operation of the corresponding transistor structure and prevents mutual crosstalk.
[0100] As an example, the width of the initial gate 102 corresponding to the second source / drain 109 is greater than the width of the initial gate 102 corresponding to the first source / drain 107. Of course, their widths may also be equal, which can be set according to requirements.
[0101] Please refer to Figures 12 - 17 As shown, this embodiment also provides an image sensor. Among them, the structure of the image sensor in this embodiment is preferably prepared by using the above-mentioned method for preparing an image sensor. Of course, it can also be prepared by other methods. For the structure of the devices and the corresponding features in this embodiment, please refer to the description in the method for preparing an image sensor, which will not be elaborated here. Among them, the image sensor includes:
[0102] A semiconductor substrate having opposite first and second surfaces;
[0103] A first improved gate structure located on the first surface of the semiconductor substrate, including a first gate structure and a sidewall improvement layer located on the sidewalls of the first gate structure;
[0104] A first source / drain located in the semiconductor substrate around the first improved gate structure, and there is a first distance between the first source / drain and the first gate structure;
[0105] A second improved gate structure located on the first surface of the semiconductor substrate and having a spacing from the first improved gate structure, including a second gate structure and a sidewall improvement layer located on the sidewalls of the second gate structure;
[0106] A second source / drain located in the semiconductor substrate around the second improved gate structure, and there is a second distance different from the first distance between the second source / drain and the second gate structure.
[0107] As an example, there is an overlap between the first source / drain and the sidewall improvement layer corresponding to the first gate structure. Further, the projection of the sidewall improvement layer corresponding to the first gate structure on the surface of the semiconductor substrate falls within the range of the first source / drain; the second source / drain and the sidewall improvement layer corresponding to the second gate structure are adjacently arranged.
[0108] As an example, the sidewall improvement layer includes at least one of a silicon oxide layer and a silicon nitride layer.
[0109] As an example, the thickness of the sidewall improvement layer is between 50 and 500 angstroms.
[0110] As an example, the thickness of the sidewall improvement layer is between 1 / 4 and 2 / 3 of the thickness of the initial sidewall.
[0111] As an example, the image sensor further includes an initial doping region. The first gate structure and the second gate structure both include an initial gate and an initial sidewall. The initial doping region is located in the semiconductor substrate around the initial gate. Among them, the initial sidewall also extends to the surface of the initial doping region adjacent to the initial gate, and both the first source / drain and the second source / drain extend into the semiconductor substrate corresponding to the initial doping region.
[0112] As an example, the image sensor includes a plurality of pixel units arranged in an array. Each pixel unit includes a photoelectric conversion element, a transfer transistor, a floating diffusion region, and a pixel circuit transistor. Among them, the transfer transistor corresponds to the second gate structure, and at least one pixel circuit transistor corresponds to the first gate structure.
[0113] As an example, the image sensor includes a pixel region and a peripheral logic region. The pixel units are located in the pixel region, and the peripheral logic region includes a plurality of logic circuit transistors; among them, the logic circuit transistors correspond to at least one of the first gate structure and the second gate structure. As an example, the same type of transistor structures in the peripheral logic region and the pixel region are fabricated based on the same process.
[0114] As an example, the image sensor further includes an isolation structure extending from the first surface of the semiconductor substrate into the semiconductor substrate. The isolation structure defines the positions of the first source / drain and / or the second source / drain. The side of the first source / drain and / or the second source / drain away from the corresponding gate structure is adjacent to the isolation structure.
[0115] As an example, the distance between the isolation structure and the second gate structure is greater than the distance between the isolation structure and the first gate structure; as an example, the distance between the second source / drain and the corresponding initial gate is greater than the distance between the first source / drain and the corresponding initial gate.
[0116] As an example, the width of the initial gate corresponding to the second source / drain is greater than the width of the initial gate corresponding to the first source / drain; as an example, the width of the first source / drain is equal to the width of the second source / drain; as an example, the depth of the first source / drain is less than the depth of the isolation structure and the depth of the second source / drain is less than the depth of the isolation structure.
[0117] Embodiment 2:
[0118] The present utility model further provides an electronic device, including the image sensor as described in any one of the above solutions. The electronic device can be a security monitoring device, an in-vehicle electronic device, a mobile phone camera, a machine vision device, etc. Based on the image sensor of the present utility model, high-quality image information can be obtained, and it can also be used in an infrared utilization device.
[0119] In summary, the present utility model designs the manufacturing process and corresponding structure of the image sensor, so that the obtained transistors can meet the requirements of different performances. For example, they can meet the requirements of transistors for different electric field strengths. By adopting the method of forming the initial sidewall and the sidewall improvement layer step by step, source / drains of different types of transistors can be obtained, so that the transistors have different structures, and the distance between the source / drain of the transistor and the channel of the transistor is different, and finally transistors with different performances (such as electric field strength) are obtained. Therefore, the present utility model effectively overcomes various shortcomings in the prior art and has high industrial utilization value.
[0120] The above embodiments are only illustrative of the principles and effects of the present utility model and are not used to limit the present utility model. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present utility model. All equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present utility model shall still be covered by the claims of the present utility model.
Claims
1. An image sensor, characterized in that: The image sensor comprises: A semiconductor substrate having a first surface and a second surface opposite to each other; A first improved gate structure, located on the first surface of the semiconductor substrate, comprising a first gate structure and a sidewall improvement layer located on the sidewall of the first gate structure; A first source and drain is located in the semiconductor substrate around the first improved gate structure, and a first distance exists between the first source and drain and the first gate structure; A second improved gate structure, located on the first surface of the semiconductor substrate and spaced apart from the first improved gate structure, comprising a second gate structure and a sidewall improvement layer located on a sidewall of the second gate structure; A second source and drain is located in the semiconductor substrate around the second improved gate structure, and a second distance different from the first distance exists between the second source and drain and the second gate structure.
2. The image sensor according to claim 1, wherein: The first source and drain overlap with the sidewall improvement layer corresponding to the first gate structure, and the second source and drain are adjacent to the sidewall improvement layer corresponding to the second gate structure; and / or the sidewall improvement layer is composed of any one of a silicon oxide layer or a silicon nitride layer, or the sidewall improvement layer is composed of a stacked structure composed of a silicon oxide layer and a silicon nitride layer; and / or the thickness of the sidewall improvement layer is between 50-500 angstroms; and / or each gate structure includes an initial gate and an initial sidewall, and the initial sidewall includes one of a silicon oxide-silicon nitride-silicon oxide structure, a silicon oxide-silicon nitride structure and an oxide layer.
3. The image sensor according to claim 1, wherein: The image sensor also includes an initial doping region, the first gate structure and the second gate structure both include an initial gate and an initial sidewall, the initial doping region is located in the semiconductor substrate around the initial gate, wherein the initial sidewall also extends to the surface of the initial doping region adjacent to the initial gate, and the first source and drain and the second source and drain both extend into the semiconductor substrate corresponding to the initial doping region.
4. The image sensor according to claim 3, wherein: The depth and / or concentration of the initial doping region is less than that of the first source drain, and the depth and / or concentration of the initial doping region is less than that of the second source drain; and / or the depth and / or concentration of the first source drain is equal to that of the second source drain.
5. The image sensor according to claim 1, wherein: The image sensor includes a plurality of pixel units arranged in an array, each of the pixel units includes a photoelectric conversion element, a transfer transistor, a floating diffusion region and a pixel circuit transistor, wherein the transfer transistor corresponds to the second gate structure, and at least one pixel circuit transistor corresponds to the first gate structure.
6. The image sensor according to claim 5, characterized in that The image sensor includes a pixel area and a peripheral logic area, the pixel unit is located in the pixel area, and the peripheral logic area includes a plurality of logic circuit transistors; wherein the logic circuit transistor corresponds to at least one of the first gate structure and the second gate structure; and / or, the transistor structure of the same type in the peripheral logic area and the pixel area is prepared based on the same process.
7. The image sensor according to any one of claims 1 to 6, characterized in that: The image sensor also includes an isolation structure extending from the first surface of the semiconductor substrate to the semiconductor substrate, the isolation structure defines the position of the first source drain and / or the second source drain, and the first source drain and / or the second source drain is arranged adjacent to the isolation structure on a side away from the corresponding gate structure.
8. The image sensor according to claim 7, wherein: The distance between the isolation structure and the second gate structure is greater than the distance between the isolation structure and the first gate structure; and / or each gate structure includes an initial gate and an initial sidewall, and the width of the initial gate corresponding to the second source and drain is greater than the width of the initial gate corresponding to the first source and drain; And / or, the depth of the first source drain is less than the depth of the isolation structure and the depth of the second source drain is less than the depth of the isolation structure.
9. The image sensor according to claim 7, wherein: Each gate structure includes an initial gate and an initial side wall, the distance between the second source drain and the corresponding initial gate is greater than the distance between the first source drain and the corresponding initial gate; and / or the width of the first source drain is equal to the width of the second source drain.
10. An electronic device, characterized in that: The electronic device comprises the image sensor as claimed in any one of claims 1 to 9.