Multichannel charge sensitive reading device

Abstract

The utility model relates to the technical field of detectors, and particularly discloses a multichannel charge sensitive reading device, which comprises a detector, a configuration switch, GEMYC32 chips, DAC digital-to-analog conversion chips, an FPGA chip, an upper computer, a crystal oscillator and a power network, the two groups of GEMYC32 chips, the DAC digital-to-analog conversion chips, the crystal oscillator, the power network and the upper computer are respectively connected with the FPGA chip, the configuration switch is connected with the two groups of GEMYC32 chips, and the two groups of GEMYC32 chips are respectively connected with the FPGA chip. The DAC digital-to-analog conversion chip is connected with the two groups of GEMYC32 chips, the detector is connected with the two groups of GEMYC32 chips, the crystal oscillator is used for providing clock signals for the FPGA chip, the DAC digital-to-analog conversion chip controls the magnitude of output voltage through the FPGA chip to provide threshold voltage for the GEMYC32 chips, and the FPGA chip is used for controlling the DAC digital-to-analog conversion chip, processing data information discriminated and output by the two groups of GEMYC32 chips and sending the data information to an upper computer. Induced electric signals can be output at the same time, interference between channels is weak, the integration level of the system is improved, and the system has the characteristics of high gain, high counting rate and radiation resistance.

Description

Technical Field

[0001] The utility model relates to the technical field of detectors, in particular to a multi-channel charge sensitive readout device. Background Art

[0002] At present, the charge sensitive readout device is mainly applied to the front-end readout of nuclear particle detection. When a particle hits the detector, the internal gas is ionized, and electron gain is achieved through the high-voltage electric field in the micro-holes of the GEM membrane. The induced electrical signal is output through two groups of mutually orthogonal metal strips on the surface of the readout electrode, amplified by a charge sensitive preamplifier, and sent to different data acquisition channels for further amplification and processing. Finally, the data acquisition channel transmits the data of the corresponding channel to the upper computer for data analysis to obtain the position coordinates of the incident particle.

[0003] However, in the prior art, the charge sensitive readout device has a large occupied space, high power consumption, and poor anti-interference ability, which limits the integration degree of the system. Summary of the Utility Model

[0004] The purpose of the utility model is to provide a multi-channel charge sensitive readout device, aiming at solving the technical problems that the charge sensitive readout device in the prior art has a large occupied space, high power consumption, poor anti-interference ability, and limits the integration degree of the system.

[0005] To achieve the above purpose, a multi-channel charge sensitive readout device adopted by the utility model includes a detector, a configuration switch, a GEMYC32 chip, a DAC digital-to-analog conversion chip, an FPGA chip, an upper computer, a crystal oscillator, and a power network. The number of the GEMYC32 chips is two groups. The two groups of GEMYC32 chips, the DAC digital-to-analog conversion chip, the crystal oscillator, the power network, and the upper computer are respectively connected to the FPGA chip. The configuration switch is connected to the two groups of GEMYC32 chips. The DAC digital-to-analog conversion chip is connected to the two groups of GEMYC32 chips. The detector is connected to the two groups of GEMYC32 chips. The crystal oscillator is used to provide a clock signal for the FPGA chip. The DAC digital-to-analog conversion chip controls the output voltage magnitude through the FPGA chip to provide a threshold voltage for the GEMYC32 chip. The FPGA chip is used to control the DAC digital-to-analog conversion chip and process the discrimination output data information of the two groups of GEMYC32 chips, and send it to the upper computer.

[0006] Wherein, the upper computer and the FPGA chip are connected by using a UART communication and synchronous transmission protocol.

[0007] Wherein, the two groups of GEMYC32 chips and the DAC digital-to-analog conversion chip are connected to the FPGA chip by using an SPI communication.

[0008] Among them, each group of the GEMYC32 chips is composed of an analog module and a digital module.

[0009] Among them, the analog module is composed of a charge-sensitive preamplifier circuit, a CR-RC shaping filter circuit, a discriminator circuit, and a reference circuit. The charge-sensitive preamplifier circuit amplifies the input fc-level charge and converts it into a voltage signal. The CR-RC shaping filter circuit performs secondary amplification on the voltage signal output by the charge-sensitive preamplifier circuit to form a quasi-Gaussian waveform. The discriminator circuit compares the voltage signal input from the CR-RC shaping filter circuit with the threshold voltage input by the external DAC digital-to-analog conversion chip. When the voltage signal input from the CR-RC shaping filter circuit exceeds the threshold voltage input by the DAC digital-to-analog conversion chip, the discriminator circuit outputs a high level.

[0010] Among them, the digital module is composed of a scale signal configuration circuit and a decoder circuit. The decoder circuit is used to select a channel to view its analog waveform during testing.

[0011] The beneficial effects of a multi-channel charge-sensitive reading device of the present utility model are as follows: Using two groups of the GEMYC32 chips to form 64 channels, the induced electrical signals can be output simultaneously, and the interference between channels is weak. The charge is amplified by the charge-sensitive preamplifier and sent to different data acquisition channels for further processing. Finally, the data acquisition channels transmit the data of the corresponding channels to the host computer for data analysis, improving the integration of the system, and having the characteristics of high gain, high counting rate, and radiation resistance. Description of the Drawings

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0013] Figure 1 It is a schematic structural diagram of a multi-channel charge-sensitive reading device of the present utility model.

[0014] Figure 2 It is a schematic composition structure diagram of the GEMYC32 chip of the present utility model.

[0015] Figure 3 It is a charge-sensitive preamplifier circuit diagram of the present utility model.

[0016] Figure 4 It is a CR-RC shaping filter circuit diagram of the present utility model.

[0017] Figure 5 is the discriminator circuit diagram of the present utility model.

[0018] Figure 6 is the scale signal configuration circuit diagram of the present utility model.

[0019] Figure 7 is the decoder circuit diagram of the present utility model.

[0020] Figure 8 is the structural schematic diagram of the FPGA chip of the present utility model.

[0021] Figure 9 is the circuit diagram of the first high-speed IO interface of the present utility model.

[0022] Figure 10 is the circuit diagram of the second high-speed IO interface of the present utility model.

[0023] Figure 11 is the circuit diagram of the first GEMYC32 chip of the present utility model.

[0024] Figure 12 is the circuit diagram of the second GEMYC32 chip of the present utility model.

[0025] Figure 13 is the circuit diagram of the DAC digital-to-analog conversion chip of the present utility model.

[0026] Figure 14 is the circuit diagram of the FPGA chip of the present utility model.

[0027] Figure 15 is the serial port to USB circuit diagram of the present utility model.

[0028] Figure 16 is the power network circuit diagram of the present utility model.

[0029] Figure 17 is the crystal oscillator circuit diagram of the present utility model.

[0030] 1 - Detector, 2 - Configuration switch, 3 - GEMYC32 chip, 4 - DAC digital-to-analog conversion chip, 5 - FPGA chip, 6 - Host computer, 7 - Crystal oscillator, 8 - Power network, 9 - Charge sensitive preamplifier circuit, 10 - CR-RC shaping filter circuit, 11 - Discriminator circuit, 12 - Reference circuit, 13 - Scale signal configuration circuit, 14 - Decoder circuit. Specific implementation manner

[0031] Please refer to Figures 1 to 17, the present utility model provides a multi-channel charge sensitive reading device, including a detector 1, a configuration switch 2, a GEMYC32 chip 3, a DAC digital-to-analog conversion chip 4, an FPGA chip 5, a host computer 6, a crystal oscillator 7 and a power network 8. The number of the GEMYC32 chips 3 is two groups. The two groups of the GEMYC32 chips 3, the DAC digital-to-analog conversion chip 4, the crystal oscillator 7, the power network 8 and the host computer 6 are respectively connected to the FPGA chip 5. The configuration switch 2 is connected to the two groups of the GEMYC32 chips 3. The DAC digital-to-analog conversion chip 4 is connected to the two groups of the GEMYC32 chips 3. The detector 1 is connected to the two groups of the GEMYC32 chips 3. The crystal oscillator 7 is used to provide a clock signal for the FPGA chip 5. The DAC digital-to-analog conversion chip 4 controls the output voltage magnitude through the FPGA chip 5 to provide a threshold voltage for the GEMYC32 chip 3. The FPGA chip 5 is used to control the DAC digital-to-analog conversion chip 4 and process the discrimination output data information of the two groups of the GEMYC32 chips 3, and send it to the host computer 6.

[0032] Further, the host computer 6 and the FPGA chip 5 are connected by using a UART communication and synchronous transmission protocol.

[0033] Further, the two groups of the GEMYC32 chips 3 and the DAC digital-to-analog conversion chip 4 are connected to the FPGA chip 5 by using an SPI communication.

[0034] Further, each group of the GEMYC32 chips 3 is composed of an analog module and a digital module.

[0035] Further, the analog module is composed of a charge sensitive preamplifier circuit 9, a CR-RC shaping filter circuit 10, a discriminator circuit 11 and a reference circuit 12. The charge sensitive preamplifier circuit 9 amplifies the input fc-level charge and converts it into a voltage signal. The CR-RC shaping filter circuit 10 performs a secondary amplification on the voltage signal output by the charge sensitive preamplifier circuit 9 to form a quasi-Gaussian waveform. The discriminator circuit 11 compares the voltage signal input by the CR-RC shaping filter circuit 10 with the threshold voltage input by the external DAC digital-to-analog conversion chip 4. When the voltage signal input by the CR-RC shaping filter circuit 10 exceeds the threshold voltage input by the DAC digital-to-analog conversion chip 4, the discriminator circuit 11 outputs a high level.

[0036] Further, the digital module is composed of a calibration signal configuration circuit 13 and a decoder circuit 14. The decoder circuit 14 is used to select a channel to view its analog waveform during testing.

[0037] In this embodiment, the GEMYC32 chip 3 designs a common calibration signal inlet for each analog channel. Since the continuous activation of the calibration signal will affect the normal input signal, the chip designs the calibration signal configuration circuit 13 to control the enabling and disabling of the calibration signal channel through the switching function of CMOS;

[0038] The decoder circuit 14 is used to select a channel to view its analog waveform during testing. The GEMYC32 chip 3 has a total of 32 analog channels, with every 8 channels as a group. The first channel of each group is led out and connected to the MUX, and a specific channel is selected by the 2-4 decoder circuit 14 to conduct to the analog I / O buffer circuit, and then analog output is performed through the pins;

[0039] The FPGA chip 5 includes a clock management circuit, a data reading control circuit, a data storage and forwarding circuit, and a data transmission circuit. The data reading control circuit is responsible for controlling the reading of the data transmitted by the GEMYC32 chip 3. The data storage and forwarding circuit is respectively connected to the clock management circuit, the data reading control circuit, and the data transmission circuit, and is used for caching the read data and sending the data to the data transmission circuit according to the requirements of the data transmission circuit. The data transmission circuit is responsible for transmitting the read data to the host computer 6;

[0040] The crystal oscillator 7 provides the clock signal for the chip to work, mainly composed of an active 20M crystal oscillator 7;

[0041] The power supply network 8 is mainly composed of a 5V to 3.3V power supply chip, which provides the working voltage required for the FPGA chip 5, the GEMYC32 chip 3, and the crystal oscillator 7;

[0042] Example 1:

[0043] First, two high-speed IO interfaces 114805 are designed in the device. The first high-speed IO interface is for the detector to transmit the charge signal to the high-speed IO interface of the device. The high-speed IO interface is mainly connected to the input pins of the detector to the GEMYC32 chip 3, as Figure 9 shown. Then, the charge signal generated by the detector will be transmitted to the inside of the GEMYC32 chip 3 for analog amplification and shaping. The second high-speed IO interface functions to connect the differential chip output to the cable of the host computer 6. The FPGA chip 5 transmits a large amount of data generated by 64 channels to the host computer 6, and is transmitted to the host computer 6 through the differential chip and the high-speed IO interface, as Figure 10 shown;

[0044] The schematic diagram of the GEMYC32 chip 3 is as Figure 11 and Figure 12 shown, where all the pins of AIN are connected fromFigure 9 All OUT pins are connected to the same net name pins in Figure 14 On the BANK pin in;

[0045] The circuit principle of the DAC digital-to-analog conversion chip 4 is as follows: Figure 13 shown, where the OUT pin is connected to Figure 11 and Figure 12 The DIN, SCLK, and SYNC pins are connected to the corresponding pins. Figure 14 On the corresponding pins of Bank P6-7;

[0046] The principle of the FPGA chip 5 is as follows Figure 14 As shown in the schematic diagram, the main connection method between the FPGA pins and the GEMYC32, DAC, USB serial port and high-speed IO port;

[0047] The serial port to USB circuit uses the CP2102-GM chip as the adapter chip. The schematic diagram of the serial port to USB circuit is as follows: Figure 15 As shown, UART_RX and UART_TX are connected to Figure 14 On pins 6 and 7 of P6-2Bank;

[0048] The power supply network 8 mainly uses AMS1117-3.3 and AMS1117-1.8 power supply chips to convert 5V input into 3.3V and 1.8V voltages, and provide the required working voltages for the FPGA chip 5, the GEMYC32 chip 3 and the crystal oscillator 7;

[0049] The crystal oscillator 7 is composed of a 20M active crystal oscillator 7 and a number of capacitors and magnetic beads. The BLM21PG121SN1 magnetic beads play a role in suppressing high-frequency noise in the circuit. Figure 17 shown.

[0050] The above disclosure is only a preferred embodiment of the present invention, and certainly cannot be used to limit the scope of rights of the present invention. Ordinary technicians in this field can understand that all or part of the processes of the above embodiment and equivalent changes made according to the claims of the present invention still fall within the scope covered by the utility model.

Claims

1. A multi-channel charge sensitive reading device, characterized in that: It includes a detector, a configuration switch, a GEMYC32 chip, a DAC digital-to-analog conversion chip, an FPGA chip, a host computer, a crystal oscillator and a power supply network. The number of the GEMYC32 chips is two groups. The two groups of GEMYC32 chips, the DAC digital-to-analog conversion chip, the crystal oscillator, the power supply network and the host computer are respectively connected to the FPGA chip. The configuration switch is connected to the two groups of GEMYC32 chips. The DAC digital-to-analog conversion chip is connected to the two groups of GEMYC32 chips. The detector is connected to the two groups of GEMYC32 chips. The crystal oscillator is used to provide a clock signal for the FPGA chip. The DAC digital-to-analog conversion chip controls the output voltage through the FPGA chip to provide a threshold voltage to the GEMYC32 chip. The FPGA chip is used to control the DAC digital-to-analog conversion chip and process the data information identified and output by the two groups of GEMYC32 chips, and send it to the host computer.

2. A multi-channel charge sensitive reading device as claimed in claim 1, characterized in that: The host computer and the FPGA chip are connected using UART communication and synchronous transmission protocol.

3. A multi-channel charge sensitive reading device as claimed in claim 1, characterized in that: The two groups of GEMYC32 chips and the DAC digital-to-analog conversion chip are connected to the FPGA chip using SPI communication.

4. A multi-channel charge sensitive reading device as claimed in claim 3, characterized in that: Each group of GEMYC32 chips consists of an analog module and a digital module.

5. A multi-channel charge sensitive reading device as claimed in claim 4, characterized in that: The analog module is composed of a charge-sensitive preamplifier circuit, a CR-RC shaping filter circuit, a discriminator circuit and a reference circuit. The charge-sensitive preamplifier circuit amplifies the input fc-level charge and converts it into a voltage signal. The CR-RC shaping filter circuit performs secondary amplification on the voltage signal output by the charge-sensitive preamplifier circuit to form a quasi-Gaussian waveform. The discriminator circuit compares the voltage signal transmitted by the CR-RC shaping filter circuit with the threshold voltage input by the external DAC digital-to-analog conversion chip. When the voltage signal transmitted by the CR-RC shaping filter circuit exceeds the threshold voltage input by the DAC digital-to-analog conversion chip, the discriminator circuit outputs a high level.

6. A multi-channel charge sensitive reading device as claimed in claim 4, characterized in that: The digital module is composed of a scale signal configuration circuit and a decoder circuit. The decoder circuit is used to select a channel to view its analog waveform during testing.

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