Intelligent analysis host SATA hard disk interface expansion circuit

Abstract

The utility model discloses an intelligent analysis host SATA (Serial Advanced Technology Attachment) hard disk interface expansion circuit, which relates to the field of electronic information and comprises a 3.3 V step-down circuit used for outputting 3.3 V direct current as a power supply; the 1.25 V step-down circuit is used for outputting 1.2 V direct current as a power supply; the filter circuit is used for filtering the 3.3 V direct current and 1.2 V direct current and filtering high-frequency interference of a power supply; and the FLASH driving circuit is used for reserving an SPI (Serial Peripheral Interface) interface and writing in a chip driver through the reserved SPI interface. The beneficial effects of the utility model are that the conversion master control circuit is arranged, the chip JMB585 is used for expansion, and a PCIE (Peripheral Component Interface Express) interface is converted into an SATA (Serial Advanced Technology Attachment) interface, so that when an analysis host CPU (Central Processing Unit) adopts a NVIDIA Jetson scheme, a 2.5-inch solid state disk with the SATA interface can be used.

Description

Technical Field

[0001] The utility model relates to the field of electronic information, and specifically to an SATA hard disk interface expansion circuit for an intelligent analysis host. Background Technique

[0002] The intelligent analysis host can accurately identify the abnormal state of the pantograph and give prompts. The abnormal prompts are divided into two categories: early warning and alarm according to the severity of the fault. Early warning: large spark, dirty picture, and carbon slide wear reaching the limit; Alarm: pantograph tilt, pantograph structure abnormality, hanging foreign object, inconsistent lifting and lowering pantograph state. The analysis board can perform pop-up prompts for different types of pre / alarm information and automatically save the video information for 1 minute before and 1 minute before and after the fault. When a high-voltage fault (from the monitoring screen) occurs in the vehicle, the analysis board records the video for 1 minute before and 1 minute before and after the fault moment and pushes it to the intelligent monitoring screen for video linkage. The generation time of the 1-minute video is not more than 5 seconds, and the generation time of the 1-minute video before and after is not more than 65 seconds.

[0003] According to the on-site function requirements, the hard disk needs to use a 2.5-inch solid-state hard disk with an SATA interface. When the CPU of the intelligent analysis host adopts the NVIDIA jetson solution, this model of CPU has no SATA interface and cannot use a 2.5-inch solid-state hard disk with an SATA interface, which needs to be improved. Content of the Utility Model

[0004] The purpose of the utility model is to provide an SATA hard disk interface expansion circuit for an intelligent analysis host to solve the problems raised in the above background technique.

[0005] To achieve the above purpose, the utility model provides the following technical solutions:

[0006] An SATA hard disk interface expansion circuit for an intelligent analysis host, including:

[0007] A 3.3V step-down circuit for outputting 3.3V direct current as a power supply;

[0008] A 1.25V step-down circuit for outputting 1.2V direct current as a power supply;

[0009] A filtering circuit for filtering the 3.3V and 1.2V direct currents to filter out the high-frequency interference of the power supply;

[0010] A FLASH driving circuit for reserving an SPI interface and writing a chip driver through the reserved SPI interface to ensure the normal operation of the conversion main control circuit;

[0011] A conversion main control circuit for converting a PCIE interface into an SATA interface;

[0012] The 3.3V step-down circuit is connected to the 1.25V step-down circuit and the filtering circuit. The 1.25V step-down circuit is connected to the filtering circuit. The filtering circuit is connected to the conversion main control circuit. The FLASH driving circuit is connected to the conversion main control circuit.

[0013] As a further solution of the present utility model: The 3.3V step-down circuit includes chip U1, the model of chip U1 is MP2491C. The 1st pin of chip U1 introduces 24V voltage. The 9th pin of chip U1 is connected to one end of resistor R3. The other end of resistor R3 is connected to one end of capacitor C5. The other end of capacitor C5 is connected to one end of inductor L1 and the 8th pin of chip U1. The other end of inductor L1 outputs 3.3V voltage. The other end of inductor L1 is connected to one end of resistor R4, one end of capacitor C18, one end of capacitor C13, one end of capacitor C14, one end of capacitor C15, and one end of capacitor C16. The other end of resistor R4 is connected to the other end of capacitor C18, one end of resistor R8, and the 6th pin of chip U1. The other end of resistor R8 is grounded. The other end of capacitor C13 is grounded. The other end of capacitor C14 is grounded. The other end of capacitor C15 is grounded. The other end of capacitor C16 is grounded.

[0014] As a further solution of the present utility model: The 1.25V step-down circuit includes chip U12. The 2nd pin of chip U12 introduces 3.3V voltage. The 3rd pin of chip U12 is connected to one end of inductor L3. The other end of inductor L3 outputs 1.25V voltage. The other end of inductor L3 is connected to one end of resistor R60, one end of capacitor C26, one end of capacitor C27, and the 5th pin of chip U12. The other end of capacitor C26 is grounded. The other end of capacitor C27 is grounded. The other end of resistor R60 is connected to one end of resistor R74 and the 7th pin of chip U12. The other end of resistor R74 is grounded.

[0015] As a further solution of the present utility model: The FLASH driving circuit includes chip U21, the model of chip U21 is W25X20CLSNIG. The 1st, 2nd, 3rd, 5th, and 6th pins of chip U21 are connected to the conversion main control circuit. The 7th and 8th pins of chip U21 are connected to the filtering circuit. The 3rd pin of chip U21 is connected to the filtering circuit through resistor R97.

[0016] As a further solution of the present utility model: The conversion main control circuit includes chip U20, the model of chip U20 is JMB585. The 13th, 15th, 17th, 18th, and 19th pins of chip U20 are connected to the FLASH driving circuit. The 23rd, 24th, 26th, 27th, 29th, 30th, 33rd, 34th, 36th, and 37th pins of chip U20 are respectively connected to the PCIE interface through a capacitor. The 40th, 41st, 43rd, 44th, 46th, 47th, 49th, and 50th pins of chip U20 are connected to the SATA interface.

[0017] Compared with the prior art, the beneficial effects of the present utility model are as follows: By setting up a conversion main control circuit and expanding it through the chip JMB585, the PCIE interface is converted to the SATA interface, enabling the use of a 2.5-inch solid-state drive with a SATA interface when the analysis host CPU adopts the NVIDIA jetson solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of the SATA hard disk interface expansion circuit of an intelligent analysis host.

[0019] Figure 2 It is a circuit diagram of the 3.3V step-down circuit.

[0020] Figure 3 It is a circuit diagram of the 1.25V step-down circuit.

[0021] Figure 4 It is a circuit diagram of the filter circuit.

[0022] Figure 5 It is a circuit diagram of the FLASH drive circuit.

[0023] Figure 6 It is a circuit diagram of the conversion main control circuit. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] The technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without creative efforts shall fall within the protection scope of the present utility model.

[0025] Please refer to Figure 1 , an intelligent analysis host SATA hard disk interface expansion circuit, including:

[0026] A 3.3V step-down circuit for outputting 3.3V direct current as a power supply;

[0027] A 1.25V step-down circuit for outputting 1.2V direct current as a power supply;

[0028] A filter circuit for filtering the 3.3V and 1.2V direct currents to remove high-frequency interference from the power supply;

[0029] A FLASH drive circuit for reserving an SPI interface and writing the chip driver through the reserved SPI interface to ensure the normal operation of the conversion main control circuit;

[0030] A conversion main control circuit is used to convert a PCIE interface to a SATA interface;

[0031] The 3.3V step-down circuit is connected to the 1.25V step-down circuit and the filtering circuit. The 1.25V step-down circuit is connected to the filtering circuit. The filtering circuit is connected to the conversion main control circuit. The FLASH driving circuit is connected to the conversion main control circuit.

[0032] In a specific embodiment: Please refer to Figure 4 , the filtering circuit filters the 3.3V voltage and the 1.2V voltage by setting inductors and capacitors. By using magnetic beads and multiple capacitors for filtering, high-frequency interference in the power supply can be effectively filtered out, avoiding signal interference to the main circuit and affecting the normal operation of the main control.

[0033] In this embodiment: Please refer to Figure 2 , the 3.3V step-down circuit includes chip U1. The model of chip U1 is MP2491C. The 24V voltage is introduced into the 1st pin of chip U1. The 9th pin of chip U1 is connected to one end of resistor R3. The other end of resistor R3 is connected to one end of capacitor C5. The other end of capacitor C5 is connected to one end of inductor L1 and the 8th pin of chip U1. The other end of inductor L1 outputs 3.3V voltage. The other end of inductor L1 is connected to one end of resistor R4, one end of capacitor C18, one end of capacitor C13, one end of capacitor C14, one end of capacitor C15, and one end of capacitor C16. The other end of resistor R4 is connected to the other end of capacitor C18, one end of resistor R8, and the 6th pin of chip U1. The other end of resistor R8 is grounded. The other end of capacitor C13 is grounded. The other end of capacitor C14 is grounded. The other end of capacitor C15 is grounded. The other end of capacitor C16 is grounded.

[0034] Using a non-isolated BUCK circuit structure, it has high conversion efficiency and small PCB area occupation, and converts the input 24V voltage into a 3.3V low voltage as the power supply.

[0035] In this embodiment: Please refer to Figure 3 , the 1.25V step-down circuit includes chip U12. The 3.3V voltage is introduced into the 2nd pin of chip U12. The 3rd pin of chip U12 is connected to one end of inductor L3. The other end of inductor L3 outputs 1.25V voltage. The other end of inductor L3 is connected to one end of resistor R60, one end of capacitor C26, one end of capacitor C27, and the 5th pin of chip U12. The other end of capacitor C26 is grounded. The other end of capacitor C27 is grounded. The other end of resistor R60 is connected to one end of resistor R74 and the 7th pin of chip U12. The other end of resistor R74 is grounded.

[0036] Using a non-isolated BUCK circuit structure, it has high conversion efficiency and small PCB area occupation. It further converts the DC voltage converted by the 3.3V buck circuit into a 1.2V logic supply voltage to power the control logic chip on the system.

[0037] In this embodiment: Please refer to Figure 5 , the FLASH driver circuit includes chip U21, the model of chip U21 is W25X20CLSNIG. Pins 1, 2, 3, 5, and 6 of chip U21 are connected to the conversion main control circuit. Pins 7 and 8 of chip U21 are connected to the filtering circuit. Pin 3 of chip U21 is connected to the filtering circuit through resistor R97.

[0038] W25X20CLSNIG is powered by 3.3V and has a reserved SPI interface. The board can write the chip driver through the reserved interface to ensure the normal operation of the main control CPU (using a specific chip to complete a specific driver is a common technology and does not involve innovation of the method).

[0039] In this embodiment: Please refer to Figure 6 , the conversion main control circuit includes chip U20, the model of chip U20 is JMB585. Pins 13, 15, 17, 18, and 19 of chip U20 are connected to the FLASH driver circuit. Pins 23, 24, 26, 27, 29, 30, 33, 34, 36, and 37 of chip U20 are respectively connected to the PCIE interface through a capacitor. Pins 40, 41, 43, 44, 46, 47, 49, and 50 of chip U20 are connected to the SATA interface.

[0040] By designing with chip JMB585 to convert the PCIE interface into a SATA interface, when the analysis host CPU adopts the NVIDIA jetson solution, a 2.5-inch solid-state drive with a SATA interface can be used.

[0041] The working principle of the present utility model is as follows: The 3.3V buck circuit is used to output 3.3V DC power as the power supply; the 1.25V buck circuit is used to output 1.2V DC power as the power supply; the filtering circuit is used to filter the 3.3V and 1.2V DC powers to filter out the high-frequency interference of the power supply; the FLASH driver circuit is used to reserve the SPI interface and write the chip driver through the reserved SPI interface to ensure the normal operation of the conversion main control circuit; the conversion main control circuit is used to convert the PCIE interface into a SATA interface.

[0042] For those skilled in the art, it is obvious that the present utility model is not limited to the details of the above-mentioned exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or basic characteristics of the present utility model. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting.

[0043] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. An intelligent analysis host SATA hard disk interface expansion circuit, characterized in that: The intelligent analysis host SATA hard disk interface expansion circuit includes: 3.3V step-down circuit, used to output 3.3V DC as power supply; 1.25V step-down circuit, used to output 1.2V DC as power supply; The filter circuit is used to filter the 3.3V and 1.2V DC power to remove the high-frequency interference of the power supply; FLASH driving circuit, used to reserve SPI interface, write chip driver through the reserved SPI interface to ensure the normal operation of the conversion main control circuit; Conversion master control circuit, used to convert PCIE interface to SATA interface; The 3.3V step-down circuit is connected to the 1.25V step-down circuit and the filter circuit, the 1.25V step-down circuit is connected to the filter circuit, the filter circuit is connected to the conversion main control circuit, and the FLASH driving circuit is connected to the conversion main control circuit.

2. The intelligent analysis host SATA hard disk interface expansion circuit according to claim 1, characterized in that: The 3.3V step-down circuit includes a chip U1. The model of the chip U1 is MP2491C. Pin 1 of the chip U1 introduces a 24V voltage. Pin 9 of the chip U1 is connected to one end of the resistor R3. The other end of the resistor R3 is connected to one end of the capacitor C5. The other end of the capacitor C5 is connected to one end of the inductor L1 and pin 8 of the chip U1. The other end of the inductor L1 outputs a 3.3V voltage. The other end of the inductor L1 is connected to one end of the resistor R4, one end of the capacitor C18, one end of the capacitor C13, one end of the capacitor C14, one end of the capacitor C15, and one end of the capacitor C16. The other end of the resistor R4 is connected to the other end of the capacitor C18, one end of the resistor R8, and pin 6 of the chip U1. The other end of the resistor R8 is grounded, the other end of the capacitor C13 is grounded, the other end of the capacitor C14 is grounded, the other end of the capacitor C15 is grounded, and the other end of the capacitor C16 is grounded.

3. The intelligent analysis host SATA hard disk interface expansion circuit according to claim 1, characterized in that: The 1.25V step-down circuit includes chip U12, pin 2 of chip U12 introduces 3.3V voltage, pin 3 of chip U12 is connected to one end of inductor L3, the other end of inductor L3 outputs 1.25V voltage, the other end of inductor L3 is connected to one end of resistor R60, one end of capacitor C26, one end of capacitor C27, and pin 5 of chip U12, the other end of capacitor C26 is grounded, the other end of capacitor C27 is grounded, the other end of resistor R60 is connected to one end of resistor R74 and pin 7 of chip U12, and the other end of resistor R74 is grounded.

4. The intelligent analysis host SATA hard disk interface expansion circuit according to claim 1, characterized in that: The FLASH driving circuit includes chip U21. The model of chip U21 is W25X20CLSNIG. Pins 1, 2, 3, 5 and 6 of chip U21 are connected to the conversion main control circuit. Pins 7 and 8 of chip U21 are connected to the filter circuit. Pin 3 of chip U21 is connected to the filter circuit through resistor R97.

5. The intelligent analysis host SATA hard disk interface expansion circuit according to any one of claims 1 to 4, characterized in that: The conversion main control circuit includes chip U20. The model of chip U20 is JMB585. Pins 13, 15, 17, 18 and 19 of chip U20 are connected to the FLASH drive circuit, pins 23, 24, 26, 27, 29, 30, 33, 34, 36 and 37 of chip U20 are connected to the PCIE interface through a capacitor respectively, and pins 40, 41, 43, 44, 46, 47, 49 and 50 of chip U20 are connected to the SATA interface.

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