Semiconductor device

Abstract

A semiconductor device is disclosed. A memory device includes a substrate; a sense amplifier including a plurality of first gate-all-around field effect transistors having a plurality of first drain / source regions extending into the substrate; and a plurality of bit cells including a plurality of fuse memory elements and a plurality of second gate-all-around field effect transistors. Each bit cell includes a fuse memory element having a first terminal and a second terminal. The first terminal is connected to the input terminal of the sense amplifier, and the second terminal is connected to the second gate-all-around field effect transistor. The second gate-all-around field effect transistor includes a plurality of second drain / source regions and a bottom dielectric isolation layer, and the bottom dielectric isolation layer is located below the second drain / source regions.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Semiconductor devices include different types of memories, such as random-access memory (RAM), read-only memory (ROM), and electrical fuse (eFuse) memory. The eFuse memory is a programmable non-volatile memory (NVM) that does not lose data when the semiconductor device is powered off. Generally, the eFuse is integrated into the semiconductor device using a narrow strip of conductive material (referred to as a fuse) located between terminals. To program the eFuse, a current needs to be applied to the fuse body to change the resistivity of the fuse body. A sensing circuit (such as a sense amplifier) is used to read the state of the eFuse, i.e., whether it has been programmed. Summary of the Utility Model

[0003] According to some embodiments of the present disclosure, a semiconductor device includes a substrate, a sense amplifier, and a plurality of bit cells. The sense amplifier includes a plurality of first surround-gate field-effect transistors having a plurality of first drain / source regions extending into the substrate. The plurality of bit cells include a plurality of fuse memory elements and a plurality of second surround-gate field-effect transistors. Each bit cell includes a fuse memory element having a first terminal and a second terminal. The first terminal is connected to an input terminal of the sense amplifier, and the second terminal is connected to the second surround-gate field-effect transistor. The second surround-gate field-effect transistor includes a plurality of second drain / source regions and a bottom dielectric isolation layer, and the bottom dielectric isolation layer is located below the second drain / source regions.

[0004] According to some embodiments of the present disclosure, a semiconductor device includes a substrate, at least one sense amplifier, and a plurality of bit cells. The sense amplifier includes a plurality of first surround-gate field-effect transistors and a plurality of second surround-gate field-effect transistors. The first surround-gate field-effect transistors have a plurality of first drain / source regions extending into the substrate. Each second surround-gate field-effect transistor includes a plurality of second drain / source regions and a bottom dielectric isolation layer, and the bottom dielectric isolation layer is located below the second drain / source regions. The plurality of bit cells include a plurality of indium gallium zinc oxide transistors, and each bit cell is connected to the sense amplifier and configured to store at least one bit of data in a fuse or an antifuse.

[0005] According to some embodiments of the present disclosure, a semiconductor device includes a substrate, a plurality of first gate-all-around field-effect transistors, a plurality of second gate-all-around field-effect transistors, and a plurality of fuse memory elements. The plurality of first gate-all-around field-effect transistors include a plurality of first drain / source regions extending into the substrate, and the first gate-all-around field-effect transistors are part of at least one sense amplifier. The plurality of second gate-all-around field-effect transistors include a plurality of second drain / source regions and a bottom dielectric isolation layer, and the bottom dielectric isolation layer is located under the second drain / source regions. At least one of the second gate-all-around field-effect transistors is connected to at least one of the fuse memory elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] As the following detailed description is read in conjunction with the accompanying Figure 1 drawings, aspects of the present disclosure may be best understood. It should be emphasized that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased. Additionally, the drawings are illustrative of embodiments of the present disclosure and are not intended to be limiting.

[0007] Figure 1 FIG. 1 is a schematic diagram of a semiconductor device including a bit cell memory array and a sense circuit configured to provide an output voltage (Vout) according to some embodiments;

[0008] Figure 2 FIG. 2 is a schematic diagram of a semiconductor device including a bit cell memory array and peripheral circuits according to some embodiments;

[0009] Figure 3 FIG. 3 is a schematic diagram of a gate-all-around (GAA) metal-oxide semiconductor field-effect transistor (MOSFET) including drain / source regions extending into the substrate of a semiconductor device according to some embodiments;

[0010] Figure 4 FIG. 4 is a schematic diagram of a GAA MOSFET having drain / source regions extending to a depth D1 into the substrate according to some embodiments;

[0011] Figure 5 FIG. 5 is a schematic diagram of a GAA MOSFET having drain / source regions extending to a depth D2 into the substrate according to some embodiments;

[0012] Figure 6 FIG. 6 is a schematic diagram of a bit cell of a bit cell memory array according to some embodiments;

[0013] Figure 7 Schematic diagram of a super bottom isolation (SBI) GAA MOSFET according to some embodiments;

[0014] Figure 8 Schematic diagram of a flexible bottom isolation (FBI) GAA MOSFET according to some embodiments;

[0015] Figure 9 Schematic diagram of a graph showing the off - current Ioff of different GAA MOSFETs according to some embodiments;

[0016] Figure 10 Schematic diagram of a bit cell as a stacked indium gallium zinc oxide (IGZO) element according to some embodiments;

[0017] Figure 11 Schematic diagram of a bit cell including an SBI GAA MOSFET each coupled to a sense amplifier according to some embodiments Figure 7 ;

[0018] Figure 12 Schematic diagram of a bit cell including an FBI GAA MOSFET each coupled to a sense amplifier according to some embodiments Figure 8 ;

[0019] Figure 13 Schematic diagram of a bit - cell memory array including bit cells electrically connected to a sense amplifier according to some embodiments;

[0020] Figure 14 Schematic diagram of a bit - cell memory array including bit cells electrically connected to a sense amplifier according to some embodiments, the sense amplifier including n - channel GAA MOSFETs, each n - channel GAA MOSFET being an SBI GAA MOSFET or an FBI GAA MOSFET;

[0021] Figure 15 Schematic diagram of a stacked IGZO element bit cell coupled to a sense amplifier according to some embodiments;

[0022] Figure 16 Schematic diagram of a high - density storage device according to some embodiments;

[0023] Figure 17Schematic diagram showing the layout of a high-density storage device according to some embodiments;

[0024] Figure 18 Schematic diagram showing two transistor antifuse bit cells according to some embodiments;

[0025] Figure 19 Schematic diagram showing another high-density storage device according to some embodiments;

[0026] Figure 20 Schematic diagram showing according to some embodiments Figure 20 the layout of a high-density storage element;

[0027] Figure 21 Schematic diagram showing the deposition of an oxide layer in a semiconductor device (such as Figure 1 and / or Figure 2 semiconductor devices) according to some embodiments;

[0028] Figure 22 Schematic diagram showing the TiN deposition and photolithography of the TiN deposition to form two TiN gates on the oxide layer according to some embodiments;

[0029] Figure 23 Schematic diagram showing the deposition of a high-k dielectric on the TiN gate and photolithography of the high-k dielectric according to some embodiments;

[0030] Figure 24 Schematic diagram showing the deposition and photolithography of the IGZO active region to provide an IGZO active region deposited on the high-k dielectric according to some embodiments;

[0031] Figure 25 Schematic diagram showing the deposition and photolithography of a TiN layer to form drain / source regions in a tin layer according to some embodiments;

[0032] Figure 26 Schematic diagram showing the deposition of an oxide layer according to some embodiments;

[0033] Figure 27 Schematic diagram showing contact etching through the oxide layer to provide vias to the drain / source regions according to some embodiments;

[0034] Figure 28 Schematic diagram showing conductive wiring (such as vias and metal layer wiring) contacting the drain / source regions of an IGZO transistor according to some embodiments;

[0035] Figure 29 Schematic diagram showing a method of manufacturing a semiconductor device according to some embodiments;

[0036] Figure 30 Schematic diagram of another manufacturing method of a display semiconductor device according to some embodiments;

[0037] Figure 31 Schematic diagram of another method of a manufacturing method of a display semiconductor device according to some embodiments;

[0038] Figure 32 Block diagram of an example of a computer system configured to provide the semiconductor device and method of the present disclosure according to some embodiments;

[0039] Figure 33 Block diagram of a semiconductor device manufacturing system and a semiconductor device manufacturing process related thereto according to some embodiments.

[0040]

Reference Signs

[0041] 20: Semiconductor device

[0042] 22: Bit cell memory array

[0043] 24: Sensing circuit

[0044] 26: Conductive path

[0045] 28: Conductive path

[0046] 30: Row decoder circuit

[0047] 32: Column decoder circuit

[0048] 34a: Row line

[0049] 34n: Row line

[0050] 36a: Column line

[0051] 36n: Column line

[0052] 38: Control circuit

[0053] 40: Conductive path

[0054] 42: Conductive path

[0055] 44: Conductive path

[0056] 46: Peripheral circuit

[0057] 50: GAA MOSFET

[0058] 52a: Drain / source region

[0059] 52b: Drain / source region

[0060] 54: Substrate

[0061] 56a:MG contact

[0062] 56b:MG contact

[0063] 56c:MG contact

[0064] 56d:MG contact

[0065] 58a: Silicon channel

[0066] 58b: Silicon channel

[0067] 58c: Silicon channel

[0068] 60a: Internal insulation

[0069] 60b: Internal insulation

[0070] 60c: Internal insulation

[0071] 60d: Internal insulation

[0072] 60e: Internal insulation

[0073] 60f: Internal insulation

[0074] 60g:Internal insulation

[0075] 60h: Internal insulation

[0076] 70: Bit unit

[0077] 72:eFuse

[0078] 74: n-channel MOSFET

[0079] 76:Reference

[0080] 80: GAA MOSFET

[0081] 82: GAA MOSFET

[0082] 84:Substrate

[0083] 86: bottom dielectric layer

[0084] 86a: bottom dielectric layer

[0085] 86b: bottom dielectric layer

[0086] 88a: drain / source region

[0087] 88b: drain / source region

[0088] 90a:MG contact

[0089] 90b:MG contact

[0090] 90c: MG Contact

[0091] 90d: MG Contact

[0092] 92a: Silicon Channel

[0093] 92b: Silicon Channel

[0094] 92c: Silicon Channel

[0095] 94a: Internal Isolator

[0096] 94b: Internal Isolator

[0097] 94c: Internal Isolator

[0098] 94d: Internal Isolator

[0099] 94e: Internal Isolator

[0100] 94f: Internal Isolator

[0101] 96: X - axis

[0102] 98: Y - axis

[0103] 100: Stacked IGZO Device

[0104] 102: IGZO Transistor

[0105] 104: eFuse Memory Element

[0106] 106: TiN Gate

[0107] 108: Oxide Layer

[0108] 110: High - k Dielectric

[0109] 112: IGZO Active Region

[0110] 114: TiN Layer

[0111] 116: Drain / Source Region

[0112] 118: Drain / Source Region

[0113] 120: Via

[0114] 122: Contact Layer

[0115] 124: Via

[0116] 126: Via

[0117] 128: Contact Layer

[0118] 130: Via

[0119] 132: Contact layer

[0120] 150: Bit cell

[0121] 152: Sense amplifier

[0122] 154: eFuse memory element

[0123] 156: First p-channel MOSFET

[0124] 158: Second p-channel MOSFET

[0125] 160: First n-channel MOSFET

[0126] 162: Second n-channel MOSFET

[0127] 164: Third n-channel MOSFET

[0128] 166: Bias resistor

[0129] 168: Reference

[0130] 170: Third p-channel MOSFET

[0131] 172: Fourth p-channel MOSFET

[0132] 174: Fifth p-channel MOSFET

[0133] 176: Sixth p-channel MOSFET

[0134] 178: Fourth n-channel MOSFET

[0135] 180: Fifth n-channel MOSFE

[0136] 182: Seventh p-channel MOSFET

[0137] 184: Sixth n-channel MOSFET

[0138] 186: Inverter

[0139] 188: Inverter

[0140] 190: Bit cell

[0141] 210: High-density storage device

[0142] 212: Bit cell

[0143] 214: Peripheral circuit

[0144] 216: BEOL wiring

[0145] 218: Oxide layer

[0146] 220: Oxide layer

[0147] 222: First n-channel MOSFET

[0148] 224: Second n-channel MOSFET

[0149] 230: High-density storage device

[0150] 232: Bit cell

[0151] 234: Peripheral circuit

[0152] 236: BEOL wiring

[0153] 238: Oxide layer

[0154] 240: Oxide layer

[0155] 242: TiN gate

[0156] 244: High-k dielectric

[0157] 246: IGZO active region

[0158] 248: TiN layer

[0159] 250: Drain / source region

[0160] 252: Drain / source region

[0161] 254: Via hole

[0162] 256: Metal layer segment

[0163] 258: Via hole

[0164] 260: Via hole

[0165] 262: Metal layer segment

[0166] 264: Via hole

[0167] 266: Metal layer segment

[0168] 270: Oxide layer

[0169] 272: Oxide layer

[0170] 274: Via hole

[0171] 276: Conductive wiring

[0172] 300: Step

[0173] 302: Step

[0174] 304: Step

[0175] 306: Step

[0176] 320: Step

[0177] 322: Step

[0178] 324: Step

[0179] 330: Step

[0180] 332: Step

[0181] 334: Step

[0182] 400: System

[0183] 402: Processor

[0184] 404: Non - transitory computer - readable storage medium

[0185] 406: Instruction

[0186] 408: Manufacturing tool

[0187] 410: Bus

[0188] 412: I / O interface

[0189] 414: Network interface

[0190] 416: Network

[0191] 418: Database

[0192] 420: User interface

[0193] 422: Manufacturing system

[0194] 424: Design office

[0195] 426: Mask room

[0196] 428: Manufacturing plant

[0197] 430: Semiconductor device design layout diagram

[0198] 432: Data preparation

[0199] 434: Mask manufacturing

[0200] 436: Mask

[0201] 438: Semiconductor wafer

[0202] 440: Wafer manufacturing

[0203] 442: Semiconductor device

[0204] BL: Bit Line

[0205] D1: Depth

[0206] D2: Depth

[0207] MAF: Anti - fuse Transistor

[0208] MST: Selection Transistor

[0209] T: Terminal

[0210] WL: Word Line Signal

[0211] WLR: Bit Line Signal

[0212] WLP: Word Line Signal Detailed Implementation Manner

[0213] The following disclosure provides many different embodiments or examples of different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the various embodiments of the present disclosure. Of course, these examples are merely exemplary and are not intended to be restrictive. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Additionally, the various embodiments of the present disclosure may repeat reference numerals and / or letters in different instances. This repetition is for the purpose of simplicity and clarity and does not in itself prescribe a relationship between the various embodiments and / or configurations discussed.

[0214] In addition, spatial relative terms, such as "below", "beneath", "lower", "above", "upper" and their like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature, as shown in the drawings. Spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be oriented in other ways (rotated 90 degrees or at other orientations) and the spatial relative descriptors used herein may be understood accordingly.

[0215] Generally, an eFuse bit cell includes a fuse link and circuitry for programming and reading the eFuse. Historically, fuse links have occupied a large area in semiconductor devices. In some embodiments, the fuse link is fabricated in a metal layer, such as metal layer 2. However, there are some drawbacks to using metal layer 2 to fabricate the fuse link, such as not being able to use metal layer 2 for other wiring considerations and not being able to reduce the bit cell memory area layer due to design rule requirements between the fuse links on the same metal.

[0216] In some embodiments, a bit cell includes a transistor and a resistive fuse (1T1R). Each fuse is electrically connected to the transistor for programming and reading the eFuse. In some embodiments, the transistor in the 1T1R bit cell is a gate-all-around (GAA) metal-oxide semiconductor field-effect transistor (MOSFET) fabricated in a nanosheet process. In some embodiments, these GAA transistors have drain / source regions extending into the substrate such that the GAA transistors have a large off-current Ioff. Thus, unselected bits have a large leakage current, which may result in high resistance and read 1 errors. For example, if a high resistance value is read from a selected bit and the sense current includes a large leakage current from an unselected bit, the total current may exceed the read 1 margin of the sense amplifier, resulting in a read 1 error. This is especially a problem at higher temperatures, where the leakage current (i.e., off-current) of unselected bits is large.

[0217] The disclosed embodiments provide a semiconductor device with improved read 1 margin, where the off-current Ioff of unselected bits is reduced and the read 1 margin is increased. In some embodiments, the semiconductor device includes bit cells, each bit cell having a GAA MOSFET with a bottom dielectric layer located beneath the drain / source region of the MOSFET, which reduces the off-current Ioff of the GAA MOSFET. In some embodiments, the semiconductor device includes bit cells, each bit cell including an indium gallium zinc oxide (IGZO) device, the IGZO device including an IGZO transistor with a reduced off-current Ioff connected to a fuse memory element such as a metal fuse.

[0218] In some embodiments, the semiconductor device includes a substrate, a sense amplifier, and bit cells. The sense amplifier includes a plurality of first GAA transistors having a plurality of first drain / source regions extending into the substrate. The bit cells include a plurality of second GAA transistors, each second GAA transistor including a plurality of second drain / source regions and a bottom dielectric isolation layer located beneath the second drain / source regions, wherein each second GAA transistor is connected to a fuse memory element. In some embodiments, each second GAA transistor includes a bottom dielectric isolation layer in contact with the second drain / source regions.

[0219] Further disclosed embodiments provide a semiconductor device that includes a stacked IGZO device over a sense amplifier in a high-density memory. In some embodiments, the semiconductor device includes a substrate, at least one sense amplifier, and a bit cell that includes IGZO transistors. The sense amplifier includes a GAA transistor having a first drain / source region extending into the substrate. Each bit cell is connected to at least one sense amplifier and is configured to store at least one bit of data in a fuse memory element or an antifuse memory element. In some embodiments, each IGZO transistor is connected to a fuse memory element. In some embodiments, each bit cell includes at least two IGZO transistors connected in series to provide an antifuse bit cell. In some embodiments, each bit cell includes more than two IGZO transistors that are connected to provide a memory element, such as an antifuse memory element.

[0220] Further disclosed embodiments include semiconductor devices having different layouts or designs and methods of forming the semiconductor devices described herein.

[0221] Figure 1 Schematic diagram of a semiconductor device 20 according to some embodiments showing a bit cell memory array 22 and a sense circuit 24 configured to provide an output voltage (Vout). The bit cell memory array 22 is electrically connected to the sense circuit 24 via memory array conduction paths 26 and 28. In some embodiments, the semiconductor device 20 is an integrated circuit.

[0222] The semiconductor device 20 includes a bit cell memory array 22, a row decoder circuit 30, and a column decoder circuit 32. The bit cell memory array 22 includes bit cells arranged in an x-y grid. The row decoder circuit 30 is electrically connected to the bit cell memory array 22 via row lines 34a - 34n extending in the x direction. The column decoder circuit 32 is electrically connected to the bit cell memory array 22 via column lines 36a - 36n extending in the y direction. The rows of the x-y grid of the bit cell memory array 22 extend along the x-axis and the columns extend along the y-axis.

[0223] In some embodiments, the bit cell memory array 22 includes eFuse memory elements. In some embodiments, the bit cell memory array 22 includes anti-fuse memory elements. In some embodiments, the bit cell memory array 22 includes 1T1R memory elements. In some embodiments, the bit cell memory array 22 includes 1T1C memory elements. In some embodiments, the bit cell memory array 22 includes NTMR memory elements, where N>0 and M>0. In some embodiments, the bit cell memory array 22 includes NTMC memory elements, where N>0 and M>0. In some embodiments, the bit cell memory array 22 includes multi-transistor (e.g., two-transistor) anti-fuse memory elements. In some embodiments, the bit cell memory array 22 is one of a static random-access memory (SRAM), a resistive random-access memory (RRAM), a phase-change random-access memory (PCRAM), and a magneto-resistive random-access memory (MRAM).

[0224] The semiconductor device 20 includes a control circuit 38. The control circuit 38 is electrically connected to the sense circuit 24 through a conductive path 40 and is electrically connected to the row decoder circuit 30 and the column decoder circuit 32 through conductive paths 42 and 44. The row decoder circuit 30 receives and decodes row addresses, and the column decoder circuit 32 receives and decodes column addresses. In addition, the sense circuit 24, the row decoder circuit 30, and the column decoder circuit 32 receive instructions from the control circuit 38 to control the operation of the semiconductor device 20.

[0225] The sense circuit 24 includes a sense amplifier configured to read selected bit cells of the bit cell memory array 22. The bit cell memory array 22 and the sense circuit 24 provide an improved read 1 margin, where the cut-off current Ioff of unselected bits is reduced and the read 1 margin is increased. In addition, the semiconductor device 20 includes a circuit for programming the bit cells. In some embodiments, the programming circuit for programming the bit cells is located in the sense circuit 24.

[0226] In some embodiments, the semiconductor device 20 includes bit cells. Each bit cell has a GAA MOSFET. The GAA MOSFET has a bottom dielectric layer located below the drain / source regions of the MOSFET, which reduces the off-current Ioff of the GAA MOSFET. In some embodiments, the semiconductor device 20 includes bit cells. Each bit cell has at least one IGZO transistor, which reduces the off-current Ioff of the unselected bit cells and improves the read 1 margin of the sense circuit 24.

[0227] Figure 2 FIG. is a schematic diagram of a semiconductor device 20 including a bit cell memory array 22 and a peripheral circuit 46 according to some embodiments. The peripheral circuit 46 includes one or more sense amplifiers. In some embodiments, the peripheral circuit 46 includes a sense circuit 24, a row decoder 30, a column decoder 32, and a control circuit 38.

[0228] The bit cell memory array 22 includes bit cells, each bit cell including an eFuse memory element and circuitry for programming and reading the eFuse memory element. In some embodiments, the circuitry for programming and reading the eFuse is formed in a plane of the semiconductor device 20, and the eFuse is formed in a different plane of the semiconductor device 20. In some embodiments, the circuitry for programming and reading the eFuse is formed in a plane of the semiconductor device 20 that is below the plane of the semiconductor device 20 including the eFuse. In some embodiments, the eFuse is formed in a metal layer that is in a plane of the semiconductor device 20 above the plane including the circuitry for programming and reading the eFuse. In some embodiments, the eFuse is formed in a metal layer, such as a metal 2 layer.

[0229] A semiconductor device 20 including a bit cell memory array 22 and a sense circuit 24 provides an improved read 1 margin, where the cutoff current Ioff of unselected bits is reduced and the read 1 margin is increased. Each bit cell in the bit cell memory array 22 includes an eFuse and a circuit for programming and reading the eFuse. In some embodiments, each circuit for programming and reading the eFuse includes a transistor with a lower cutoff current Ioff, thereby reducing leakage current and increasing the read 1 margin. In some embodiments, each circuit for programming and reading the eFuse includes a GAA MOSFET that has a bottom dielectric layer located below the drain / source regions of the MOSFET, which reduces the cutoff current Ioff of the GAA MOSFET and increases the read 1 margin. In some embodiments, each circuit for programming and reading the eFuse includes an IGZO transistor that has a lower cutoff current Ioff, thereby increasing the read 1 margin.

[0230] The peripheral circuit 46 includes GAA MOSFETs having drain / source regions extending into the substrate of the semiconductor device 20, where the peripheral circuit 46 includes a sense circuit 24 having one or more sense amplifiers. Each of these GAA MOSFETs has a higher cutoff current Ioff than a GAA MOSFET having a bottom dielectric layer located below the drain / source regions of the MOSFET and a higher cutoff current Ioff than an IGZO transistor. In some embodiments, the GAA MOSFETs having drain / source regions extending into the substrate are formed in a plane of the semiconductor device 20 that is the same plane as the circuit including the circuit for programming and reading the eFuse, such as a GAA MOSFET having a bottom dielectric layer. In some embodiments, the GAA MOSFETs having drain / source regions extending into the substrate are formed in a plane of the semiconductor device 20 that is the same plane as the circuit including the circuit for programming and reading the eFuse (such as an IGZO transistor). In some embodiments, the peripheral circuit 46 including GAA MOSFETs having drain / source regions extending into the substrate is formed in a plane of the semiconductor device 20 that is a different plane from the plane including the IGZO transistor, such as a plane below it, so that the semiconductor device 20 can have a higher memory density. In some embodiments, the GAA MOSFETs are fabricated in a nanosheet process. In other embodiments, the GAA MOSFETs are other transistors, such as planar transistors, fin field-effect transistors (finFETs), CFETs, and fork-nanosheet transistors.

[0231] Figure 3 Schematic diagram showing a GAA MOSFET 50 including drain / source regions 52a and 52b extending into substrate 54 of semiconductor device 20. A peripheral circuit 46 including one or more sense amplifiers is fabricated using GAA MOSFET 50.

[0232] GAA MOSFET 50 includes metal-over-gate (MG) contacts 56a - 56d on each side of silicon channels 58a - 58c. Internal spacers 60a - 60f separate MG contacts 56b - 56d from drain / source regions 52a and 52b.

[0233] In operation, GAA MOSFET 50 has a higher off-state current Ioff than a GAA MOSFET having a bottom dielectric layer under the drain / source regions of the MOSFET, and has a higher off-state current Ioff than an IGZO transistor.

[0234] Figure 4 and Figure 5 Schematic diagram showing a GAA MOSFET 50 having drain / source regions 52a and 52b extending to different depths D1 and D2 into substrate 54.

[0235] Figure 4 Schematic diagram showing a GAA MOSFET 50 having drain / source regions 52a and 52b extending to a depth D1 into substrate 54, and Figure 5 Schematic diagram showing a GAA MOSFET 50 having drain / source regions 52a and 52b extending to a depth D2 into substrate 54. Depth D1 is greater than depth D2.

[0236] In Figure 4 and Figure 5 In each of the diagrams of and , GAA MOSFET 50 includes MG contacts on each side of silicon channels 58a - 58c, and internal spacers 60a - 60h separating MG contacts 56a - 56d from drain / source regions 52a and 52b.

[0237] In operation, GAA MOSFET 50 having drain / source regions 52a and 52b extending to a depth D1 into substrate 54 has a higher off-state current Ioff (leakage current) than GAA MOSFET 50 having drain / source regions 52a and 52b extending to a depth D2 into substrate 54. Moreover, Figure 4 and Figure 5Each GAA MOSFET 50 has a higher off-current Ioff than a GAA MOSFET having a bottom dielectric layer located under the drain / source regions of the MOSFET, and a higher off-current Ioff than an IGZO transistor.

[0238] In some embodiments, the peripheral circuit 46 including one or more sense amplifiers uses Figure 4 the GAA MOSFET 50. In some embodiments, the peripheral circuit 46 including one or more sense amplifiers uses Figure 5 the GAA MOSFET 50.

[0239] Figure 6 Schematic diagram showing a bit cell 70 of a bit cell memory array 22 according to some embodiments. The bit cell 70 includes an eFuse 72 and an n-channel MOSFET 74, and the n-channel MOSFET 74 is a circuit for programming and reading the eFuse 72. In some embodiments, each other bit cell in the bit cell memory array 22 is similar to the bit cell 70. In some embodiments, the bit cell 70 is an IGZO element. In some embodiments, the n-channel MOSFET 74 is a GAA MOSFET including a bottom dielectric layer. In some embodiments, the eFuse 72 is formed in a metal layer, such as a metal 2 layer.

[0240] One terminal T of the eFuse 72 is configured to be electrically connected to a programming circuit and / or one of the sense amplifiers in the sense circuit 24, for example. The other terminal of the eFuse 72 is electrically connected to one drain / source region of the MOSFET 74. The other drain / source region of the MOSFET 74 is electrically connected to a reference 76, such as ground. The gate of the MOSFET 74 is electrically connected to receive a select signal, such as a word line signal WL.

[0241] In operation, to program the bit cell 70, the word line signal WL is set to a high voltage to bias the MOSFET 74, and a current flows through the eFuse 72 to change the resistance of the eFuse 72 to a high resistance value.

[0242] To read the state of bit cell 70, i.e., to read whether bit cell 70 has been programmed, eFuse 72 is connected to a sense amplifier in sense circuit 24, and word line signal WL is set to a high voltage to select bit cell 70 and bias MOSFET 74. At least some other bit cells in bit cell memory array 22 are connected to the sense amplifier in sense circuit 24; however, other bit cells 70 are not selected, for example, by receiving a low voltage in the word line signal. This turns off the MOSFETs in the unselected bit cells. The state of the selected bit cell 70 is determined by the amount of current flowing through eFuse 72.

[0243] Each unselected bit cell connected to the sense amplifier provides an off-current Ioff, i.e., a leakage current, which is received by the sense amplifier in sense circuit 24. If the selected bit 70 is programmed to a high resistance, i.e., a read-1 resistance, and the sum of the current received by the sense amplifier from the selected bit 70 and the leakage current from other bit cells exceeds the read-1 margin, the sense amplifier generates a read-1 error. Reducing the off-current can avoid a read-1 error.

[0244] Figure 7 and Figure 8 Shows a schematic diagram of MOSFET 74 as a super bottom isolation (SBI) GAA MOSFET 80 and as a flexible bottom isolation (FBI) GAA MOSFET 82 according to some embodiments. Each of GAA MOSFETs 80 and 82 can be used in bit cell 70 of bit cell memory array 22. Moreover, each of GAA MOSFETs 80 and 82 includes a substrate 84 and a bottom dielectric layer 86 located below drain / source regions 88a and 88b of the MOSFET, where bottom dielectric layer 86 includes bottom dielectric layer 86 in SBI GAA MOSFET 80 and bottom dielectric layer segments 86a and 86b in FBI GAA MOSFET 82. Bottom dielectric layer 86 and bottom dielectric layer segments 86a and 86b located below drain / source regions 88a and 88b of the MOSFET reduce the off-current Ioff, i.e., the leakage current, of the MOSFET.

[0245] Advantages of each of SBI GAA MOSFET 80 and FBI GAA MOSFET 82 include a reduction in the off-current Ioff, i.e., a reduction in the leakage current, of bit cell 70, an increase in the read-1 margin, and improved operation at a minimum supply voltage such as VDDmin.

[0246] Figure 7Shows a schematic diagram of an SBI GAA MOSFET 80 according to some embodiments. The SBI GAA MOSFET 80 includes a substrate 84 and a bottom dielectric layer 86 formed on the substrate 84. A first drain / source region 88a is formed on one side of the bottom dielectric layer 86, and a second drain / source region 88b is formed on the other side of the bottom dielectric layer 86. The bottom dielectric layer 86 contacts each of the first drain / source region 88a and the second drain / source region 88b, and extends from the first drain / source region 88a through the gate region of the SBI GAA MOSFET 80 to the second drain / source region 88b.

[0247] The SBI GAA MOSFET 80 includes MG contacts 90a - 90d on each side of the silicon channels 92a - 92c. Internal spacers 94a - 94f separate the MG contacts 90b - 90d from the drain / source regions 88a and 88b.

[0248] In operation, the SBI GAA MOSFET 80 has a lower off - current Ioff than Figure 3 、 Figure 4 and Figure 5 's GAA MOSFET 50, where Figure 3 、 Figure 4 and Figure 5 's GAA MOSFET 50 has drain / source regions 52a and 52b extending into the substrate 54.

[0249] Figure 8 Shows a schematic diagram of an FBI GAA MOSFET 82 according to some embodiments. The FBI GAA MOSFET 82 includes a substrate 84 and bottom dielectric layer segments 86a and 86b formed on the substrate 84. A first drain / source region 88a is formed on the first bottom dielectric layer segment 86a, and a second drain / source region 88b is formed on the second bottom dielectric layer segment 86b. The first bottom dielectric layer segment 86a contacts the first drain / source region 88a, and the second bottom dielectric layer segment 86b contacts the second drain / source region 88b. The first dielectric layer segment 86a and the second dielectric layer segment 86b do not extend through the gate region of the FBI GAA MOSFET 82.

[0250] The FBI GAA MOSFET 82 includes MG contacts 90a - 90d on each side of the silicon channels 92a - 92c. Internal spacers 94a - 94f separate the MG contacts 90b - 90d from the drain / source regions 88a and 88b.

[0251] In operation, the FBI GAA MOSFET 82 has a lower off - current Ioff than Figure 3 、 Figure 4and Figure 5 the GAA MOSFET 50 has a lower off-state current Ioff, where Figure 3 、 Figure 4 and Figure 5 the GAA MOSFET 50 has drain / source regions 52a and 52b extending into the substrate 54.

[0252] Figure 9 Schematic diagram showing a graph of the off-state current Ioff of different GAA MOSFETs according to some embodiments. The GAA MOSFETs are plotted along the x-axis 96, and the off-state current Ioff is plotted on the y-axis 98 on a logarithmic scale. Different GAA MOSFETs include the GAA MOSFET 50 having drain / source regions 52a and 52b that extend deeper into the substrate 54 to a depth D1, as Figure 4 shown in (deeper D / S). The GAA MOSFET 50 having drain / source regions 52a and 52b that extend a nominal distance into the substrate 54 to a depth of D2, as Figure 5 shown (nominal D / S). And the SBI GAA MOSFET 80 includes a bottom dielectric layer 86 as Figure 7 shown.

[0253] As Figure 4 shown, the GAA MOSFET 50 (deeper D / S) having drain / source regions 52a and 52b that extend deeper into the substrate 54 to a depth D1 has an off-state current Ioff of approximately 30,000 atomic units (a.u.). As Figure 5 shown, the GAA MOSFET 50 having drain / source regions 52a and 52b that extend to a depth of D2 in the substrate 54 (nominal D / S) has a reduced off-state current Ioff of approximately 600 a.u., and as Figure 7 shown, the SBI GAA MOSFET 80 including the bottom dielectric layer 86 has a further reduced off-state current Ioff of approximately 20 a.u. In some embodiments, the FBI GAA MOSFET 82 including bottom dielectric layer segments 86a and 86b provides an off-state current Ioff similar to that of the SBI GAA MOSFET 80.

[0254] Figure 10 Schematic diagram showing a bit cell 70 of a stacked IGZO device 100 according to some embodiments. The semiconductor device 20 includes the stacked IGZO device 100 in a bit cell memory array 22, and the peripheral circuit 46 includes similar Figure 3 、 Figure 4 andFigure 5 A transistor with a GAA MOSFET 50 extending into the substrate 54.

[0255] The stacked IGZO device 100 is a 1T1R bit cell device. The stacked IGZO device 100 includes an IGZO transistor 102 electrically connected to an eFuse memory element 104. The IGZO transistor 102 includes a titanium nitride (TiN) gate 106 deposited on an oxide layer 108. A high-k dielectric 110 such as hafnium dioxide (HfO2) is deposited on the TiN gate 106, and an IGZO active region 112 is deposited on the high-k dielectric 110. A TiN layer 114 is deposited and patterned on the IGZO active region 112 to form drain / source regions 116 and 118 of the IGZO transistor 102. The drain / source region 118 is electrically connected to the eFuse memory element 104, such as a metal fuse, through a via 120, a contact layer 122, and a via 124. The eFuse memory element 104 is also electrically connected to another via 126 and a contact layer 128. The drain / source region 116 is electrically connected to a via 130 and a contact layer 132.

[0256] In operation, the stacked IGZO element 100 has a lower off-state current Ioff than Figure 3 , Figure 4 and Figure 5 the GAA MOSFET 50 with drain / source regions 52a and 52b extending into the substrate 54.

[0257] Advantages of the stacked IGZO device 100 include a reduction in the off-state current Ioff, i.e., a reduction in leakage current, an increase in read 1 margin, a smaller area of the bit cell 70, and a higher memory density.

[0258] Figures 11 to 15 Shows schematic diagrams of different embodiments of a bit cell memory array 22 and a sense circuit 24 in a semiconductor device 20 according to some embodiments. The bit cell memory array 22 includes bit cells 150 and the sense circuit 24 includes a sense amplifier 152. In different embodiments, the bit cells 150 and / or the sense amplifier 152 include different transistors. Figure 1

[0259] Figure 11 Figure 7 Shows a schematic diagram of a bit cell 150 according to some embodiments, each bit cell including an Figure 7 SBI GAA MOSFET 80 coupled to a sense amplifier 152. Each bit cell 150 includes an SBI GAA MOSFET 80 electrically connected to an eFuse memory element 154, and the eFuse memory element 154 is electrically connected to the sense amplifier 152. The sense amplifier 152 includes a similarFigure 3 , Figure 4 and Figure 5 n-channel and p-channel GAA MOSFETs of the GAA MOSFET 50 having drain / source regions 52a and 52b extending into the substrate 54. The bit cell 150 is part of the bit cell memory array 22, and the sense amplifier 152 is Figure 1 part of the sensing circuit 24 in the semiconductor device 20. In some embodiments, the eFuse memory element 154 is a metal fuse.

[0260] The sense amplifier 152 includes a bias circuit that includes a first p-channel MOSFET 156, a second p-channel MOSFET 158, a first n-channel MOSFET 160, a second n-channel MOSFET 162, and a third n-channel MOSFET 164. One drain / source region of the first p-channel MOSFET 156 is electrically connected to VDD, and the other drain / source region of the first p-channel MOSFET 156 is electrically connected to one drain / source region of the first n-channel MOSFET 160. The other drain / source region of the first n-channel MOSFET 160 is electrically connected to one end of the bias resistor 166, and the other end of the bias resistor 166 is electrically connected to one drain / source region of the second n-channel MOSFET 162. The other drain / source region of the second n-channel MOSFET 162 is electrically connected to a reference 168, such as ground.

[0261] The gate of the first p-channel MOSFET 156 is electrically connected to the gate of the second p-channel MOSFET 158, and one drain / source region of the second p-channel MOSFET 158 is electrically connected to VDD. The other drain / source region of the second p-channel MOSFET 158 is electrically connected to one drain / source region of the third n-channel MOSFET 164. The other drain / source region of the third n-channel MOSFET 164 is electrically connected to the bit cell 150 and a bit cell circuit including a third p-channel MOSFET 170 and a fourth p-channel MOSFET 172. One drain / source region of the third p-channel MOSFET 170 is electrically connected to VDDQ (1.8 volts), and the other drain / source region of the third p-channel MOSFET 170 is electrically connected to one drain / source region of the fourth p-channel MOSFET 172. The other drain / source region of the fourth p-channel MOSFET 172 is electrically connected to the drain / source region of the third n-channel MOSFET 164 and the bit cell 150. The gates of the third p-channel MOSFET 170 and the fourth p-channel MOSFET 172 receive a gate voltage, such as 1.8 volts.

[0262] The sense amplifier 152 further includes a current mirror circuit, which includes a fifth p-channel MOSFET 174, a sixth p-channel MOSFET 176, a fourth n-channel MOSFET 178, and a fifth n-channel MOSFET 180. One drain / source region of the fifth p-channel MOSFET 174 is electrically connected to VDD, and the other drain / source region of the fifth p-channel MOSFET 174 is electrically connected to one drain / source region and the gate of the fourth n-channel MOSFET 178 and the gate of the fifth n-channel MOSFET 180. The other drain / source region of the fourth n-channel MOSFET 178 is electrically connected to the reference 168. Moreover, one drain / source region of the sixth p-channel MOSFET 176 is electrically connected to VDD, and the other drain / source region of the sixth p-channel MOSFET 176 is electrically connected to one drain / source region of the fifth n-channel MOSFET 180. The other drain / source region of the fifth n-channel MOSFET 180 is electrically connected to the reference 168. The gate of the fifth p-channel MOSFET 174 is electrically connected to the gates of the first p-channel MOSFET 156 and the second p-channel MOSFET 158, and the gate of the sixth p-channel MOSFET 176 is electrically connected to the drain / source region of the second p-channel MOSFET 158.

[0263] The sense amplifier 152 further includes an output circuit, which includes a seventh p-channel MOSFET 182, a sixth n-channel MOSFET 184, a first inverter 186, and a second inverter 188. One drain / source region of the seventh p-channel MOSFET 182 is electrically connected to VDD and the other drain / source region of the seventh p-channel MOSFET 182 is electrically connected to one drain / source region of the sixth n-channel MOSFET 184 and the input of the first inverter 186. The other drain / source region of the sixth n-channel MOSFET 184 is electrically connected to the reference 168. The gate of the seventh p-channel MOSFET 182 is electrically connected to the gates of the first, second, and fifth p-channel MOSFETs 156, 158, and 174, and the gate of the sixth n-channel MOSFET 184 is electrically connected to the drain / source region of the fifth n-channel MOSFET 180.

[0264] The bit cell memory array 22 includes bit cells 150. Each bit cell 150 includes an SBI GAA MOSFET 80 electrically connected to an eFuse memory element 154, and the eFuse memory element 154 is electrically connected to a sense amplifier 152. One end of each eFuse memory element 154 is electrically connected to the drain / source region of a third n-channel MOSFET 164, and the other end of the eFuse memory element 154 is connected to one drain / source region of the SBI GAA MOSFET 80. The other drain / source region of the SBI GAA MOSFET 80 is electrically connected to a reference 168.

[0265] In operation, to read the state of one of the bit cells 150, one of the gates of the SBI GAA MOSFET 80 in the bit cell 150 (e.g., the gate receiving the bit line WL0) is set to a high voltage, e.g., 0.75 volts. This biases the SBI GAA MOSFET 80 in the selected bit cell 150. The other gates of the other SBI GAA MOSFETs 80 in the other bit cells 150 receive a low voltage, e.g., a ground voltage, to bias off the SBI GAA MOSFET 80.

[0266] When sensing the state of the selected bit cell 150, the gates of the first n-channel MOSFET 160, the second n-channel MOSFET 162, and the third n-channel MOSFET 164 each receive a high voltage, e.g., 0.75 volts, to bias across the first, second, and third n-channel MOSFETs 160, 162, and 164. This provides a bias current flowing through the first p-channel MOSFET 156, the first n-channel MOSFET 160, the bias resistor 166, and the second n-channel MOSFET 162. The gate of the second p-channel MOSFET 158 is at the same voltage as the gate of the first p-channel MOSFET 156, and the second p-channel MOSFET 158 is biased to provide a current along the read path through the third n-channel MOSFET 164 and the selected bit cell 150. Also, the second p-channel MOSFET 158 provides a leakage current for the other unselected and biased bit cells 150.

[0267] The gate of the fifth p-channel MOSFET 174 is biased to the gate voltages of the first p-channel MOSFET 156 and the second p-channel MOSFET 158 to provide current in the current mirror circuit, and the gate of the sixth p-channel MOSFET 176 is biased to the voltage at the drain / source region of the second p-channel MOSFET 158. Additionally, the gate of the seventh p-channel MOSFET 182 is biased to the gate voltages of the first p-channel MOSFET 156 and the second p-channel MOSFET 158 to provide current in the output circuit.

[0268] If the selected bit cell 150 is not programmed, it provides a low resistance path through the selected bit cell 150 to the reference 168. The current (in the form of leakage current) provided by the second p-channel MOSFET 158 to the selected bit cell 150 and the unselected bit cell 150 pulls the drain / source region of the second p-channel MOSFET 158 to a low voltage bias on the sixth p-channel MOSFET 176 to provide a high voltage at the drain / source region of the fifth n-channel MOSFET 180. This biases the sixth n-channel MOSFET 184, which provides a low voltage at the input of the first inverter 186, a high voltage at the input of the second inverter 188, and a low voltage at the output OUT (read 0).

[0269] If the selected bit cell 150 is programmed, it provides a high resistance path through the selected bit cell 150 to the reference 168. The current (in the form of leakage current) provided by the second p-channel MOSFET 158 to the selected bit cell 150 and the unselected bit cell 150 is small and pulls the drain / source region of the second p-channel MOSFET 158 to a high voltage bias on the sixth p-channel MOSFET 176 to provide a low voltage at the drain / source region of the fifth n-channel MOSFET 180. This biases off the low voltage at the input of the second inverter 188 and the high voltage at the output OUT (read 1) of the sixth n-channel MOSFET 184a, where the sixth n-channel MOSFET 184a is biased off, thereby pulling the drain / source region of the seventh p-channel MOSFET 182 to a high voltage at the input of the first inverter 186.

[0270] If a programmed high resistance is being read from a selected bit cell 150 and the leakage current of the unselected bit cell 150 is large, the total sense current may exceed the read 1 margin of the sense amplifier 152, resulting in a read 1 error. However, with each bit cell 150 including the SBIGAA MOSFET 80, the leakage current of the unselected bit cell 150 is reduced and the sense amplifier 152 does not provide a read 1 error. Advantages of using the SBI GAA MOSFET 80 in the bit cell 150 include a reduction in the off-current Ioff of the bit cell 150 (i.e., a reduction in leakage current), an increase in the read 1 margin, and improved operation at a minimum supply voltage, such as VDDmin.

[0271] Figure 12 Schematic diagram showing a bit cell 190 according to some embodiments, each bit cell including a Figure 8 FBI GAA MOSFET 82 coupled to the sense amplifier 152. Each bit cell 190 includes an FBI GAA MOSFET 82 electrically connected to the eFuse memory element 154, and the eFuse memory element 154 is electrically connected to the sense amplifier 152. The sense amplifier 152 includes similar Figure 3 , Figure 4 and Figure 5 n-channel and p-channel GAA MOSFETs of the GAA MOSFET 50 having drain / source regions 52a and 52b extending into the substrate 54. The bit cell 190 is part of the bit cell memory array 22, and the sense amplifier 152 is Figure 1 part of the readout circuit 24 in the semiconductor device 20. In some embodiments, the eFuse memory element 154 is a metal fuse.

[0272] The bit cell memory array 22 includes the bit cell 190. Each bit cell 190 includes an FBI GAA MOSFET 82 electrically connected to the eFuse memory element 154, and the eFuse memory element 154 is electrically connected to the sense amplifier 152. One end of each eFuse memory element 154 is electrically connected to the drain / source region of the third n-channel MOSFET 164, and the other end of the eFuse memory element 154 is connected to one drain / source region of the FBI GAA MOSFET 82. The other drain / source region of the FBI GAA MOSFET 82 is electrically connected to the reference 168.

[0273] The sense amplifier 152 is similar to Figure 11 the sense amplifier 152 shown, so the description of the sense amplifier 152 will not be repeated here. Additionally, the sense amplifier 152 operates to read the state of one of the bit cells 190, as described with respect to Figure 11As described for the sense amplifier 152 and the bit cell 150 shown therein, a description of the operation of the sense amplifier 152 will not be repeated here.

[0274] If a programmed high resistance is being read from a selected bit cell 190 and the leakage current of the unselected bit cell 190 is large, the total sense current may exceed the read 1 margin of the sense amplifier 152, resulting in a read 1 error. However, with each bit cell 190 including the FBIGAA MOSFET 82, the leakage current of the unselected bit cell 190 can be reduced and the sense amplifier 152 does not provide a read 1 error. The advantages of using the FBI GAA MOSFET 82 in the bit cell 190 include reducing the off-current Ioff of the bit cell 190, i.e., reducing the leakage current, increasing the read 1 margin, and improving the operation at the minimum supply voltage, such as VDDmin.

[0275] Figure 13 A schematic diagram showing a bit cell memory array 22 including bit cells 150 and 190 electrically connected to a sense amplifier 152 according to some embodiments is shown. Each of the bit cells 150 includes an Figure 7 SBI GAA MOSFET 80 coupled to the sense amplifier 152, and each of the bit cells 190 includes an Figure 8 FBI GAA MOSFET 82 coupled to the sense amplifier 152. The bit cells 190 are used as even-numbered bit cells and the bit cells 150 are used as odd-numbered bit cells.

[0276] Each bit cell 150 includes an SBI GAA MOSFET 80 electrically connected to an eFuse memory element 154, the eFuse memory element 154 is electrically connected to the sense amplifier 152, and each bit cell 190 includes an FBI GAA MOSFET 82 electrically connected to an eFuse memory element 154 is electrically connected to the sense amplifier 152. The sense amplifier 152 includes similar Figure 3 、 Figure 4 and Figure 5 n-channel and p-channel GAA MOSFETs of the GAA MOSFET 50 having drain / source regions 52a and 52b extending into the substrate 54. The bit cells 150 and 190 are part of the bit cell memory array 22, and the sense amplifier 152 is Figure 1 a part of the readout circuit 24 in the semiconductor device 20. In some embodiments, the eFuse memory element 154 is a metal fuse.

[0277] One end of each eFuse memory element 154 is electrically connected to the drain / source region of the third n-channel MOSFET 164, and the other end of the eFuse memory element 154 is connected to one drain / source region of the SBI GAA MOSFET 80 or connected to one drain / source region of the FBIGAA MOSFET 82. The other drain / source regions of the SBI GAA MOSFET 80 and the FBI GAA MOSFET 82 are electrically connected to the reference 168.

[0278] The sense amplifier 152 is similar Figure 11 to the sense amplifier 152 shown, and thus the description of the sense amplifier 152 will not be repeated here. In addition, the sense amplifier 152 operates to read the state of one of the bit cells 150 and 190, as described with respect to Figure 11 the sense amplifier 152 and the bit cell 150 shown, such that the description of the operation of the sense amplifier 152 will not be repeated here.

[0279] If a programmed high resistance is being read from the selected bit cell 150 or 190 and the leakage current of the unselected bit cells 150 and 190 is large, the total sense current may exceed the read 1 margin of the sense amplifier 152, resulting in a read 1 error. However, by using each of the bit cells 150 and 190 including the SBI GAA MOSFET 80 or the FBI GAA MOSFET 82, the leakage current of the unselected bit cells 150 and 190 can be reduced, and the sense amplifier 152 does not provide a read 1 error. The advantages of using the SBI GAA MOSFET 80 and the FBI GAA MOSFET 82 in the bit cells 150 and 190 include reducing the cut-off current Ioff, i.e., reducing the leakage current, increasing the read 1 margin, and improving the operation at the minimum supply voltage (e.g., VDDmin).

[0280] Figure 14 shows a schematic diagram of the bit cell memory array 22, which includes the bit cells 150 and 190 electrically connected to the sense amplifier 152. The sense amplifier 152 includes n-channel GAA MOSFETs 160, 162, 164, 178, 180, and 184, each of which is an SBI GAA MOSFET 80 or an FBI GAA MOSFET 82. Each bit cell 150 includes an SBI GAA MOSFET 80 coupled to the sense amplifier 152 Figure 7 and each bit cell 190 includes an SBI GAA MOSFET 80 coupled to the sense amplifier 152 Figure 8The FBI GAA MOSFET 82. The bit cell 190 is used as the even-numbered bit cell and the bit cell 150 is used as the odd-numbered bit cell. In other embodiments, the bit cell 190 and the bit cell 150 are used in other orders.

[0281] Each bit cell 150 includes an SBI GAA MOSFET 80 electrically connected to an eFuse memory element 154, the eFuse memory element 154 is electrically connected to a sense amplifier 152, and each bit cell 190 includes an FBI GAA MOSFET 82 electrically connected to the eFuse memory element 154, the eFuse memory element 154 is electrically connected to the sense amplifier 152. The sense amplifier 152 includes similar Figure 3 , Figure 4 and Figure 5 The p-channel GAA MOSFET and n-channel GAA MOSFETs 160, 162, 164, 178, 180, and 184 of the GAA MOSFET 50 having drain / source regions 52a and 52b extending into the substrate 54, where each is an SBI GAA MOSFET 80 or an FBI GAA MOSFET 82.

[0282] One end of each eFuse memory element 154 is electrically connected to the drain / source region of the third n-channel MOSFET 164, and the other end of the eFuse memory element 154 is connected to one drain / source region of the SBI GAA MOSFET 80 or connected to one drain / source region of the FBI GAA MOSFET 82. The other drain / source regions of the SBI GAA MOSFET 80 and the FBI GAA MOSFET 82 are electrically connected to the reference 168.

[0283] The sense amplifier 152 is similar to Figure 11 The sense amplifier 152 shown, except that the n-channel GAA MOSFETs 160, 162, 164, 178, 180, and 184 are each an SBI GAA MOSFET 80 or an FBI GAA MOSFET 82. Therefore, the description of the sense amplifier 152 is not repeated here. In addition, the sense amplifier 152 operates to read the state of one of the bit cells 150 and 190, as described with respect to Figure 11 The sense amplifier 152 and the bit cell 150 shown, such that the description of the operation of the sense amplifier 152 is not repeated here.

[0284] If a programmed high resistance is being read from a selected bit cell 150 or 190 and the leakage current of the unselected bit cells 150 and 190 is large, the total sense current may exceed the read 1 margin of the sense amplifier 152, resulting in a read 1 error. However, with each of the bit cells 150 and 190 including an SBI GAA MOSFET 80 or an FBI GAA MOSFET 82, the leakage current of the unselected bit cells 150 and 190 is reduced, and the sense amplifier 152 does not provide a read 1 error. Advantages of using the SBI GAA MOSFET 80 and the FBI GAA MOSFET 82 in the bit cells 150 and 190 include reducing the off-current Ioff, i.e., reducing the leakage current, increasing the read 1 margin, and improving operation at the minimum supply voltage (e.g., VDDmin).

[0285] Figure 15 Schematic diagram showing a stacked IGZO element bit cell 100 coupled to a sense amplifier 152 according to some embodiments. Each bit cell 100 includes an IGZO transistor 102 electrically connected to an eFuse memory element 104, and the eFuse memory element 104 is electrically connected to the sense amplifier 152. The sense amplifier 152 includes similar Figure 3 , Figure 4 and Figure 5 n-channel and p-channel GAA MOSFETs 50 of a GAA MOSFET having drain / source regions 52a and 52b extending into the substrate 54. The bit cell 100 is part of a bit cell memory array 22, and the sense amplifier 152 is Figure 1 part of a readout circuit 24 in a semiconductor device 20. In some embodiments, the eFuse memory element 104 is a metal fuse.

[0286] The bit cell memory array 22 includes the bit cells 100. Each bit cell 100 includes an IGZO transistor 102 electrically connected to an eFuse memory element 104, and the eFuse memory element 104 is electrically connected to the sense amplifier 152. One end of each eFuse memory element 104 is electrically connected to the drain / source region of a third n-channel MOSFET 164, and the other end of the eFuse memory element 104 is connected to one drain / source region of the IGZO transistor 102. The other drain / source region of the IGZO transistor 102 is electrically connected to a reference 168.

[0287] The sense amplifier 152 is similar Figure 11 to the sense amplifier 152 shown, and thus the description of the sense amplifier 152 is not repeated here. In addition, the sense amplifier 152 operates to read the state of one of the bit cells 100, as described with respect to Figure 11As described for the illustrated sense amplifier 152 and bit cell 150, a description of the operation of the sense amplifier 152 will not be repeated here.

[0288] If a programmed high resistance is being read from a selected bit cell 100 and the leakage current of the unselected bit cell 100 is large, the total sense current may exceed the read 1 margin of the sense amplifier 152, resulting in a read 1 error. However, with each bit cell 100 including an IGZO transistor 102, the leakage current of the unselected bit cell 100 is reduced and the sense amplifier 152 does not provide a read 1 error. Advantages of using the IGZO transistor 102 in the bit cell 100 include reducing the off-current Ioff of the bit cell 100, i.e., reducing the leakage current, increasing the read 1 margin, and improving operation at the minimum supply voltage (e.g., VDDmin). Moreover, using the stacked IGZO device bit cell 100 in a stacked memory configuration reduces the area consumed on the semiconductor device, making the stacked memory device a high-density memory.

[0289] Figure 16 A schematic diagram showing a high-density storage device 210 according to some embodiments. The high-density storage device 210 includes bit cells 212 located above a peripheral circuit 214, similar to Figure 1 the illustrated sense circuit 24 including a sense amplifier. Each of the bit cells 212 includes a Figure 10 stacked IGZO device 100 located above the peripheral circuit 214, and the peripheral circuit 214 includes Figure 3 , Figure 4 and / or Figure 5 a GAA MOSFET 50 of Figure 2 . In the manufacturing process of the high-density storage device 210, the peripheral circuit 214 and the bit cells 212 are fabricated in successive process steps, one layer on top of the other. In some embodiments, the peripheral circuit 214 is similar to Figure 1 and / or Figure 2 the illustrated peripheral circuit 46. In some embodiments, the high-density storage device 210 is

[0290] The high-density storage device 210 includes a back-end-of-line (BEOL) wiring 216 formed above the GAA MOSFET 50 and electrically connected to the GAA MOSFET 50. The GAA MOSFET 50 and the BEOL wiring 216 are formed layer by layer. The BEOL wiring 216 is electrically connected to the GAA MOSFET 50 through, for example, via interconnections. A first oxide layer 218 is deposited above the BEOL wiring 216, and in some embodiments, a second oxide layer 220 is deposited on the first oxide layer 218. Moreover, in some embodiments, only one oxide layer, such as the oxide layer 218 or the oxide layer 220, is formed above the BEOL wiring 216 and below the IGZO device 100, and in some embodiments, the oxide layers 218 and 220 are combined to form a single oxide layer above the BEOL wiring 216 and below the IGZO device 100. The stacked IGZO element 100 is formed layer by layer on the first oxide layer 218 and / or the second oxide layer 220. Among them, the GAA MOSFET 50 and the IGZO element 100 are electrically connected through the first and / or second oxide layers 218 and 220, for example, through via interconnections.

[0291] Figure 17 A schematic diagram showing the layout of the high-density storage device 210 according to some embodiments. This layout includes a bit cell 212 located above the peripheral circuit 214. The bit cell 212 includes a Figure 10 stacked IGZO element 100 located above the peripheral circuit 214, and the peripheral circuit 214 includes Figure 3 , Figure 4 and / or Figure 5 GAA MOSFET 50.

[0292] The bit cell 212 is located in a different plane of the semiconductor device 20 from the peripheral circuit 214, and this different plane is located above the peripheral circuit 214. By stacking the bit cell 212 above the peripheral circuit 214, the memory density of the high-density storage device 210 is increased, where the area consumed by the high-density storage device 210 is 50% of the area consumed by the planar semiconductor device.

[0293] Figure 18Schematic diagram showing two transistor anti-fuse bit cells 220 according to some embodiments. The anti-fuse bit cell 220 includes a first n-channel MOSFET 222 and a second n-channel MOSFET 224. One drain / source region of the first n-channel MOSFET 222 is electrically connected to the source (S), and the other drain / source region of the first n-channel MOSFET 222 is electrically connected to one drain / source region of the second n-channel MOSFET 224. The other drain / source region of the second n-channel MOSFET 224 is electrically connected to the bit line (BL). The first n-channel MOSFET 222 is referred to as an anti-fuse transistor (MAF), and the second n-channel MOSFET 224 is referred to as a select transistor (MST). The gate of the first n-channel MOSFET 222 receives a word line (WLP) signal for programming, while the gate of the second n-channel MOSFET 224 receives a bit line (WLR) signal for reading. In some embodiments, Figure 1 the bit cell memory array 22 of the semiconductor device 20 includes anti-fuse bit cells 220.

[0294] In operation, to program a selected anti-fuse bit cell 220, a programming high voltage (PHV) is provided in the WLP signal, and oxide breakdown occurs after energy accumulation. The PHV is typically higher than the I / O power supply voltage. To protect the second n-channel MOSFET 224 from the subsequent high voltage stress caused by the programmed oxide, the WLR signal is connected to the I / O power supply voltage to reduce the drain-to-gate voltage. The bit cell to be programmed has a grounded BL, which is transferred to the source of the first n-channel MOSFET 222 to provide a sufficient gate-to-source voltage difference for programming. The unselected bit cell 220 has a grounded WLP signal and WLR signal and a BL connected to the I / O power supply voltage to prevent the unselected bit cell 220 from being programmed.

[0295] To read a selected anti-fuse bit cell 220, the WLP signal is driven to a read voltage (RV) and the WLR signal is connected to VDD. For a programmed bit cell 220, current flows through the programmed gate oxide to the conductive connection of the second n-channel MOSFET 224 and the BL. The unprogrammed bit cell 220 will not conduct current. Moreover, for a programmed bit cell 220, the gate oxide breakdown location near the channel region creates a higher potential barrier between the gate oxide breakdown region and the channel, so the RV needs to be higher than VDD to overcome this barrier.

[0296] Figure 19 Schematic diagram showing a high-density storage device 230 according to some embodiments. The high-density storage device 230 includes two transistor antifuse bit cells 232 located above the peripheral circuit 234, similar to Figure 1 the sensing circuit 24 including a sense amplifier as shown. Each antifuse bit cell 232 includes two IGZO transistors 102, as Figure 10 shown, which are located above the peripheral circuit 234 including Figure 3 , Figure 4 and / or Figure 5 of the GAA MOSFET 50. In the manufacturing process of the high-density storage device 230, the peripheral circuit 234 and the antifuse bit cells 232 are fabricated in successive process steps, one layer on top of the other. In some embodiments, the peripheral circuit 234 is similar to Figure 2 the peripheral circuit 46 as shown. In some embodiments, the high-density storage device 230 is Figure 1 and / or Figure 2 a part of the semiconductor device 20. In other embodiments, during the manufacturing of the high-density storage device 230, the peripheral circuit 234 and the antifuse bit cells 232 are fabricated separately and then bonded together.

[0297] The high-density storage device 230 includes BEOL wiring 236 formed above the GAA MOSFET 50 and electrically connected to the GAA MOSFET 50. The GAA MOSFET 50 and the BEOL wiring 236 are formed layer by layer. The BEOL wiring 236 is electrically connected to the GAA MOSFET 50, for example, through via interconnects. A first oxide layer 238 is deposited above the BEOL wiring 236, and in some embodiments, a second oxide layer 240 is formed on the first oxide layer 238. Additionally, in some embodiments, only one oxide layer, such as the oxide layer 238 or the oxide layer 240, is formed above the BEOL wiring 236 and below the two transistor antifuse bit cells 232, and in some embodiments, the oxide layers 238 and 240 are combined to form a single oxide layer above the BEOL wiring 236 and below the two transistor antifuse bit cells 232. The two transistor antifuse bit cells 232 are formed layer by layer on the first and / or second oxide layers 238 and 240. Each of the two transistor antifuse bit cells 232 is similar to Figure 18 the two transistor antifuse bit cells 220 of Figure 18connected and operated like the two-transistor antifuse bit cell 220. Further, the GAA MOSFET 50 and the two-transistor antifuse bit cells 232 are electrically connected through the first and / or second oxide layers 238 and 240, e.g., through via interconnects.

[0298] Each antifuse bit cell 232 includes two IGZO transistors 102 electrically connected to each other. Each IGZO transistor 102 includes a TiN gate 242 deposited on the second oxide layer 240. A high-k dielectric 244, e.g., HfO2, is deposited on the TiN gate 242, and an IGZO active region 246 is deposited on the high-k dielectric 244. A TiN layer 248 is deposited on the IGZO active region 246 and patterned to form drain / source regions 250 and 252. One of the drain / source regions 250 is electrically connected to a via 254 and a metal layer segment 256. The other drain / source region 252 is electrically connected to the drain / source region 250 of another IGZO transistor 102 through vias 258 and 260 and a metal layer segment 262. The other drain / source region 252 is electrically connected to a via 264 and a metal layer segment 266.

[0299] In operation, each antifuse bit cell 232 operates like Figure 18 the antifuse bit cell 220. Advantages of the antifuse bit cell 232 include reduced off-current Ioff, i.e., reduced leakage current, increased read-1 margin, and reduced area of the high-density storage device 230.

[0300] Figure 20 A schematic diagram showing the layout of a high-density storage device 230 according to some embodiments. This layout includes antifuse bit cells 232 located above the peripheral circuit 234. Each antifuse bit cell 232 includes Figure 10 the two IGZO transistors 102 shown, which are located above the peripheral circuit 234 fabricated using Figure 3 , Figure 4 and / or Figure 5 the GAA MOSFET 50.

[0301] The antifuse bit cells 232 are located in a different plane of the semiconductor device 20 from the peripheral circuit 234, where the different plane is above the peripheral circuit 234. By stacking the bit cells 232 on top of the peripheral circuit 234, the memory density is increased for the high-density storage device 230, where the area consumed by the high-density storage device 230 is 50% of the area consumed by a planar semiconductor device.

[0302] Figures 21 to 28 A schematic diagram showing the manufacturing process of an IGZO transistor, as Figure 10The IGZO transistor 102 shown. In some embodiments, a manufacturing process is used to fabricate a BEOL thin film IGZO transistor.

[0303] Figure 21 Shows a schematic diagram of the deposition of an oxide layer 270 in a semiconductor device (such as Figure 1 and / or Figure 2 semiconductor device 20) according to some embodiments. In some embodiments, the oxide layer 270 is similar to Figure 10 the oxide layer 108 shown. In some embodiments, the oxide layer 270 is similar to Figure 19 the second oxide layer 240 shown.

[0304] Figure 22 Shows a schematic diagram of TiN deposition and photolithography of TiN deposition to form two TiN gates 242 on the oxide layer 270.

[0305] Figure 23 Shows a schematic diagram of the deposition of a high-k dielectric on the TiN gate 242 and photolithography of the high-k dielectric 244. In some embodiments, the high-k dielectric 244 is HfO2.

[0306] Figure 24 Shows a schematic diagram of the deposition and photolithography of an IGZO active region according to some embodiments to provide an IGZO active region 246 deposited on the high-k dielectric 244.

[0307] Figure 25 Shows a schematic diagram of the deposition of a TiN layer and photolithography to form drain / source regions 250 and 252 in the TiN layer 248. The TiN layer 248 is deposited on the IGZO active region 246 and photolithographed to form drain / source regions 250 and 252.

[0308] Figure 26 Shows a schematic diagram of the deposition of an oxide layer 272 according to some embodiments. Figure 27 Shows a schematic diagram of contact etching through the oxide layer 272 to provide vias 274 to the drain / source regions 250 and 252.

[0309] Figure 28 Shows a schematic diagram of conductive wiring 276 (such as vias and metal layer wiring) contacting the drain / source regions 250 and 252 of the IGZO transistor 102.

[0310] Figure 29 Shows a schematic diagram of a method of manufacturing a semiconductor device according to some embodiments. At 300, the method includes forming a substrate, such as substrate 54 ( Figures 3 to 5as shown in FIG. 0), and at 302, the method includes forming a first GAA transistor, such as GAA MOSFET 50, including forming first drain / source regions extending into the substrate, such as drain / source regions 52a and 52b, where the first GAA transistor is part of at least one sense amplifier, such as Figures 11 to 15 sense amplifier 152 of

[0311] At 304, the method includes forming a second GAA transistor, such as GAA MOSFETs 80 and 82 of Figure 7 and Figure 8 respectively, including forming a bottom dielectric isolation layer, such as bottom dielectric layers 86, 86a, and 86b, and forming second drain / source regions located above the bottom dielectric isolation layer, such as drain / source regions 88a and 88b. In some embodiments, forming the second GAA transistor includes forming the second drain / source regions in contact with the bottom dielectric isolation layer. In some embodiments, forming the second GAA transistor includes forming one of the second drain / source regions (such as drain / source region 88a) above a first segment of the bottom dielectric isolation layer (such as bottom dielectric layer 86a), and forming the other second drain / source region (such as drain / source region 88b) above a second segment of the bottom dielectric isolation layer (such as bottom dielectric layer 86b). In some embodiments, forming the second GAA transistor includes forming one of the second drain / source regions (such as drain / source region 88a) above a first segment of the bottom dielectric isolation layer (such as bottom dielectric layer 86a), and forming the other (such as drain / source region 88b) above a second segment of the bottom dielectric isolation layer (such as bottom dielectric layer 86b). In some embodiments, forming the second GAA transistor includes forming one of the second drain / source regions (such as drain / source region 88a) and the other of the second drain / source regions (such as drain / source region 88b) above a segment of the bottom dielectric isolation layer (such as bottom dielectric layer 86) extending from one of the second drain / source regions to the other. In some embodiments, forming the second GAA transistor includes forming the first of the second drain / source regions (such as drain / source region 88a) above a first segment of the bottom dielectric isolation layer (such as bottom dielectric layer 86a) and the second of the second drain / source regions (such as drain / source region 88b) above a second segment of the bottom dielectric isolation layer (such as bottom dielectric layer 86b), and forming the third of the second drain / source regions (such as drain / source region 88a) and the fourth of the second drain / source regions (such as drain / source region 88b) above a third segment of the bottom dielectric isolation layer (such as bottom dielectric layer 86), where the third segment of the bottom dielectric isolation layer extends from the third of the second drain / source regions to the fourth of the second drain / source regions.

[0312] At 306, the method includes forming fuse memory elements, such as fuse memory elements 72 and 154, such that at least one of the second GAA transistors is connected to at least one of the fuse memory elements.

[0313] Figure 30 A schematic diagram showing another method of manufacturing a semiconductor device (such as semiconductor device 210) according to some embodiments. At 320, the method includes forming a substrate, such as substrate 54 (as Figures 3 to 5 shown).

[0314] At 322, the method includes forming a first GAA transistor (such as GAA MOSFET 50), including forming first drain / source regions (such as drain / source regions 52a and 52b) extending into the substrate, wherein the first GAA transistor is part of at least one sense amplifier (such as Figures 11 to 15 sense amplifier 152). In some embodiments, forming the first GAA transistor includes forming the first GAA transistor on a first plane of the semiconductor device, such as in the peripheral circuit 214 of the semiconductor device (as Figure 17 shown), and forming IGZO transistors on at least one second plane, such as bit cell 212 or the bit cell 232 of the semiconductor device, different from the first plane of the semiconductor device. In some embodiments, at least one second plane is located directly above the first plane.

[0315] At 324, the method includes forming IGZO transistors (such as IGZO transistor 102) in bit cells (such as bit cells 212 and 232) such that each bit cell is connected to at least one sense amplifier (such as Figures 11 to 15 sense amplifier 152), and is configured to store at least one bit of data in a fuse memory element such as eFuse memory element 104, or in an antifuse memory element such as in bit cell 232. In some embodiments, forming the IGZO transistor includes forming at least two IGZO transistors connected in series to provide an antifuse memory element.

[0316] In some embodiments, the method includes forming fuse memory elements (such as eFuse memory element 104) such that each IGZO transistor (such as IGZO transistor 102) is connected to one of the fuse memory elements. In some embodiments, the method includes forming a second GAA transistor (such as respectively Figure 7 and Figure 8GAA MOSFETs 80 and 82), which includes forming a bottom dielectric isolation layer (such as bottom dielectric layers 86, 86a, and 86b) and forming a second drain / source region (such as drain / source regions 88a and 88b) on the bottom dielectric isolation layer, wherein the second GAA transistor is part of at least one sense amplifier (such as Figures 11 to 15 sense amplifier 152).

[0317] Figure 31 Schematic diagram showing an alternative method of manufacturing a semiconductor device (such as semiconductor device 210 or semiconductor device 230) according to some embodiments.

[0318] At 330, the method includes forming the peripheral circuits of the semiconductor device, such as peripheral circuit 214 and peripheral circuit 234. The method includes forming a substrate (such as substrate 54) (as Figures 3 to 5 shown), and forming a first GAA transistor (such as GAA MOSFET 50), which includes forming a first drain / source region (such as drain / source regions 52a and 52b) extending into the substrate, wherein the first GAA transistor is part of at least one sense amplifier (such as Figures 11 to 15 sense amplifier 152). In some embodiments, forming the peripheral circuits includes forming the first GAA transistor on a first plane, such as in peripheral circuit 214 or peripheral circuit 234 of the semiconductor device.

[0319] At 332, the method includes forming the bit cells of the semiconductor device, such as bit cells 212 and 232. This method includes forming an IGZO transistor (such as IGZO transistor 102) in the bit cell, wherein the bit cell is configured to store at least one bit of data in a fuse memory element such as eFuse memory element 104, or in an antifuse memory element such as in bit cell 232. In some embodiments, forming the bit cell includes forming at least two IGZO transistors connected in series to provide an antifuse memory element.

[0320] At 334, the method includes bonding the bit cells formed in step 332 to the peripheral circuits formed in step 330 to form a semiconductor device. The peripheral circuits are formed on a first plane, and the IGZO transistors are formed on a second plane different from the first plane. The first plane and the second plane are bonded together to form a semiconductor device. In some embodiments, the second plane is located directly above the first plane. In some embodiments, the second plane is located directly above the first plane such that each bit cell is connected to at least one sense amplifier, such as Figures 11 to 15 sense amplifier 152.

[0321] In some embodiments, the method includes forming fuse memory elements (e.g., eFuse memory element 104) such that each IGZO transistor (e.g., IGZO transistor 102) is connected to one of the fuse memory elements. In some embodiments, the method includes forming second GAA transistors (e.g., GAA MOSFETs 80 and 82, which are Figure 7 and Figure 8 respectively), which includes forming bottom dielectric isolation layers (e.g., bottom dielectric layers 86 and 86a and 86b) and forming second drain / source regions (such as drain / source regions 88a and 88b) on the bottom dielectric isolation layers, wherein the second GAA transistors are part of at least one sense amplifier (such as sense amplifier 152, which is Figures 11 to 15 ). Figure 7 and Figure 8 In some embodiments, the method includes forming second GAA transistors (e.g., GAA MOSFETs 80 and 82, which are Figure 7 and Figure 8 respectively), which includes forming bottom dielectric isolation layers (e.g., bottom dielectric layers 86 and 86a and 86b) and forming second drain / source regions (such as drain / source regions 88a and 88b) on the bottom dielectric isolation layers, wherein the second GAA transistors are part of at least one sense amplifier (such as sense amplifier 152, which is Figures 11 to 15 ). Figures 11 to 15 In some embodiments, the method includes forming second GAA transistors (e.g., GAA MOSFETs 80 and 82, which are Figure 7 and Figure 8 respectively), which includes forming bottom dielectric isolation layers (e.g., bottom dielectric layers 86 and 86a and 86b) and forming second drain / source regions (such as drain / source regions 88a and 88b) on the bottom dielectric isolation layers, wherein the second GAA transistors are part of at least one sense amplifier (such as sense amplifier 152, which is Figures 11 to 15 ).

[0322] Figure 32 FIG. shows a block diagram exemplifying a computer system 400 configured to provide the presently disclosed semiconductor devices and methods according to some embodiments. Some or all of the design, layout, and fabrication of a semiconductor device (also referred to as a semiconductor circuit) may be performed by or utilize a computer system 400. In some embodiments, the computer system 400 includes an electronic design automation (EDA) system. In some embodiments, the semiconductor device is an IC.

[0323] In some embodiments, the system 400 is a general-purpose computing device including a processor 402 and a non-transitory computer-readable storage medium 404. The computer-readable storage medium 404 may be encoded with, for example, stored computer program code, such as executable instructions 406. Execution of the instructions 406 by the processor 402 provides (at least in part) design tools that implement some or all of the functions of the system 400, such as pre-layout simulation, post-layout simulation, routing, rerouting, and final layout for fabrication. In addition, fabrication tools 408 are included to further layout and physically implement the design and fabrication of the semiconductor device. In some embodiments, execution of the instructions 406 by the processor 402 provides (at least in part) design tools that implement some or all of the functions of the system 400. In some embodiments, the system 400 includes a commercial router. In some embodiments, the system 400 includes an automatic place and route (APR) system.

[0324] The processor 402 is electrically coupled to the computer-readable storage medium 404 via the bus 410 and is electrically coupled to the I / O interface 412 via the bus 410. The network interface 414 is also electrically connected to the processor 402 via the bus 410. The network interface 414 is connected to the network 416 such that the processor 402 and the computer-readable storage medium 404 can be connected to external components using the network 416. The processor 402 is configured to execute the computer program code or instructions 406 encoded in the computer-readable storage medium 404 to cause the system 400 to perform some or all of the functions of the system 400, such as providing the semiconductor devices and methods of the present disclosure and other functions of the system 400. In some embodiments, the processor 402 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0325] In some embodiments, the computer-readable storage medium 404 is an electrical, magnetic, optical, electromagnetic, infrared, and / or semiconductor system, apparatus, or device. For example, the computer-readable storage medium 404 may include semiconductor or solid-state memory, magnetic tape, removable computer floppy disk, random-access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In some embodiments using an optical disk, the computer-readable storage medium 404 may include a compact disk read only memory (CD-ROM), a compact disk read / write memory (CD-R / W), and / or a digital video disc (DVD).

[0326] In some embodiments, the computer-readable storage medium 404 stores computer program code or instructions 406 configured to cause the system 400 to perform some or all of the functions of the system 400. In some embodiments, the computer-readable storage medium 404 also stores messages that facilitate the performance of some or all of the functions of the system 400. In some embodiments, the computer-readable storage medium 404 stores a database 418, and the database 418 includes one or more of a library of components, a library of digital circuit units, and a database.

[0327] System 400 includes an I / O interface 412 coupled to an external circuit. In some embodiments, the I / O interface 412 includes a keyboard, keypad, mouse, trackball, touchpad, touch screen, and / or cursor direction keys for transmitting messages and commands to the processor 402.

[0328] A network interface 414 is coupled to the processor 402 and allows the system 400 to communicate with a network 416 to which one or more other computer systems are connected. The network interface 414 may include: a wireless network interface (such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA) or a wire network interface (such as ETHERNET, USB, or IEEE-1364).

[0329] The system 400 is configured to receive information through the I / O interface 412. Messages received through the I / O interface 412 include one or more of instructions, data, design rules, component and cell libraries, and / or other parameters for processing by the processor 402. This message is transmitted to the processor 402 via the bus 410. In addition, the system 400 is configured to receive messages related to a user interface (UI) through the I / O interface 412. This UI message may be stored as the UI 420 in the computer-readable storage medium 404.

[0330] In some embodiments, some or all of the functions of the system 400 are implemented via a stand-alone software application for execution by the processor. In some embodiments, some or all of the functions of the system 400 are implemented in a software application that is part of an additional software application. In some embodiments, some or all of the functions of the system 400 are implemented as a plug-in of a software application. In some embodiments, at least one function of the system 400 is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the functions of the system 400 are implemented as software applications used by the system 400. In some embodiments, tools such as VIRTEOSO available from CADENCE DESIGN SYSTEMS, Inc. or other suitable layout generation tools are used to generate layout diagrams.

[0331] In some embodiments, routing, layout, and other processing are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / build-in storage or memory units, such as one or more optical discs such as digital video discs or digital versatile discs (DVDs), magnetic disks such as hard disks, semiconductor memories such as ROM and RAM, and memory cards.

[0332] As described above, embodiments of system 400 include fabrication tool 408 for implementing a fabrication process of system 400. For example, based on the final layout, a photolithography mask can be generated for fabricating a semiconductor device by fabrication tool 408.

[0333] In combination Figure 33 Other aspects of device fabrication are disclosed Figure 33 is a block diagram of a semiconductor device fabrication system 422 and an associated semiconductor device fabrication process according to some embodiments. In some embodiments, based on a layout diagram, fabrication system 422 is used to fabricate one or more semiconductor masks and / or at least one part in a layer of a semiconductor device.

[0334] In Figure 33 , semiconductor device fabrication system 422 includes entities such as design house 424, mask house 426, and semiconductor device manufacturer / fab 428 that interact with each other during the design, development, and manufacturing cycle and / or services related to fabricating semiconductor devices (e.g., the semiconductor devices described herein). The entities in system 422 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an internal network and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design house 424, mask house 426, and semiconductor device fab 428 are owned by a single larger company. In some embodiments, two or more of design house 424, mask house 426, and semiconductor device fab 428 coexist in a common facility and use common resources.

[0335] A design house (or design team) 424 generates a semiconductor device design layout 430. The semiconductor device design layout 430 includes various geometric patterns or a semiconductor device layout designed for a semiconductor device. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers of various components that make up the semiconductor structure to be fabricated. The layers are combined to form various semiconductor device characteristics. For example, a portion of the semiconductor device design layout 430 is to be formed in a semiconductor substrate (such as a silicon wafer) and in various material layers disposed on the semiconductor substrate. The design house 424 implements a design process to form the semiconductor device design layout 430. The semiconductor device design layout 430 is presented in one or more data files having geometric pattern messages. For example, the semiconductor device design layout 430 can be expressed in the GDSII file format or the DFII file format. In some embodiments, the design process includes one or more of analog circuit design, digital circuit design, logic circuit design, standard cell circuit design, power distribution network (PDN) design, where PDN design includes power via design, power voltage rail design, reference voltage rail design, placement and routing routines, and physical layout design.

[0336] The mask house 426 includes data preparation 432 and mask fabrication 434. The mask house 426 uses the semiconductor device design layout 430 to fabricate one or more masks 436 for the respective layers to be used in fabricating a semiconductor device or semiconductor structure. The mask house 426 performs mask data preparation 432, in which the semiconductor device design layout 430 is converted into a representative data file (RDF). The mask data preparation 432 provides the RDF to the mask fabrication 434. The mask fabrication 434 includes a mask writer that converts the RDF into an image on a substrate such as a mask (reticle) 436 or a semiconductor wafer 438. The design layout 430 is manipulated by the mask data preparation 432 to conform to the characteristics of the mask writer and / or the standards of the semiconductor device fabrication plant 428. In Figure 33 it, the mask data preparation 432 and the mask fabrication 434 are shown as separate elements. In some embodiments, the mask data preparation 432 and the mask fabrication 434 can be collectively referred to as mask data preparation.

[0337] In some embodiments, mask data preparation 432 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those caused by diffraction, interference, other process effects, etc. OPC adjusts the semiconductor device design layout 430. In some embodiments, mask data preparation 432 includes additional resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, etc. or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0338] In some embodiments, mask data preparation 432 includes a mask rule checker (MRC), which uses a set of mask creation rules to inspect the semiconductor device design layout 430 that has already undergone processing in OPC. The mask creation rules include certain geometric and / or connectivity restrictions to ensure sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the semiconductor device design layout 430 to compensate for limitations during mask manufacturing 434, which may undo some of the modifications performed by OPC to satisfy the mask creation rules.

[0339] In some embodiments, mask data preparation 432 includes lithography process checking (LPC) that simulates the processes to be implemented by semiconductor device fabrication plant 428. LPC simulates the processes based on the semiconductor device design layout 430 to build a simulated fabricated device. The process parameters in the LPC simulation may include parameters associated with various processes of the semiconductor device manufacturing cycle, parameters associated with the tools used to manufacture the semiconductor device, and / or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other appropriate factors, etc. or combinations thereof. In some embodiments, after the simulated fabricated device is built by LPC, if the simulated device is not close enough in shape to meet the design rules, OPC and / or MRC are repeated to further refine the semiconductor device design layout 430.

[0340] For clarity, the above description of mask data preparation 432 has been simplified. In some embodiments, mask data preparation 432 includes additional features such as a logic operation (LOP) to modify the semiconductor device design layout 430 according to manufacturing rules. Additionally, the processes applied to the semiconductor device design layout 430 during mask data preparation 432 can be performed in a variety of different orders.

[0341] After mask data preparation 432 and during mask manufacturing 434, a mask 436 or a set of masks 436 is manufactured based on the modified semiconductor device design layout 430. In some embodiments, mask manufacturing 434 includes performing one or more photolithography exposures based on the semiconductor device design layout 430. In some embodiments, based on the modified semiconductor device design layout 430, a pattern is formed on the mask (photomask or reticle) 436 using an electron beam (e-beam) or an apparatus of multiple electron beams. The mask 436 can be formed by various techniques. In some embodiments, the mask 436 is formed using a binary technique. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, for exposing an image-sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque regions and passes through the transparent regions. In one example, the binary mask version of the mask 436 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, the mask 436 is formed using a phase shift technique. In the phase shift mask (PSM) version of the mask 436, various features in the pattern formed on the phase shift mask are configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask produced by mask manufacturing 434 is used in a variety of processes. For example, such a mask is used in an ion implantation process to form various doped regions in the semiconductor wafer 438, in an etching process to form various etched regions in the semiconductor wafer 438, and / or in other suitable processes.

[0342] The semiconductor device manufacturing factory 428 includes a wafer fabrication 440. The semiconductor device manufacturing factory 428 is a semiconductor device manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different semiconductor device products. In some embodiments, the semiconductor device manufacturing factory 428 is a semiconductor foundry. For example, there may be a manufacturing facility for front end of line (FEOL) manufacturing of multiple semiconductor device products, while a second manufacturing facility can provide BEOL manufacturing for the interconnection and packaging of semiconductor device products, and a third manufacturing facility can provide other services for the foundry business.

[0343] The semiconductor device manufacturing factory 428 uses a mask 436 fabricated by the mask chamber 426 to fabricate the presently disclosed semiconductor structure or semiconductor device 442. Thus, the semiconductor device manufacturing factory 428 at least indirectly uses the semiconductor device design layout 430 to fabricate the presently disclosed semiconductor structure or semiconductor device 442. Further, the semiconductor wafer 438 includes a silicon substrate or other suitable substrate having material layers formed thereon, and the semiconductor wafer 438 also includes one or more of various doped regions, dielectric features, multi-level interconnections, etc. (formed in subsequent manufacturing steps). In some embodiments, the semiconductor wafer 438 is fabricated by the semiconductor device manufacturing factory 428 using the mask 436 to form the presently disclosed semiconductor structure or semiconductor device 442. In some embodiments, semiconductor device fabrication includes performing one or more photolithographic exposures at least indirectly based on the semiconductor device design layout 430.

[0344] Embodiments disclosed herein provide a semiconductor device with improved read 1 margin, where the off-current Ioff of unselected bits is reduced and the read 1 margin is increased. In some embodiments, this semiconductor device includes bit cells, each bit cell having a GAA MOSFET, and this GAA MOSFET has a bottom dielectric layer located below the drain / source regions of the MOSFET, which reduces the off-current Ioff of the GAA MOSFET. In some embodiments, this semiconductor device includes bit cells, each bit cell including an IGZO device, and this IGZO device includes an IGZO transistor with a reduced off-current Ioff connected to a fuse memory element such as a metal fuse. In some embodiments, the semiconductor device includes one or more sense amplifiers, which include GAA transistors having drain / source regions extending into the substrate.

[0345] Further disclosed embodiments provide a semiconductor device that includes a stacked IGZO device over a sense amplifier in a high density memory. In some embodiments, the semiconductor device includes a substrate, at least one sense amplifier that includes a GAA transistor having a plurality of first drain / source regions extending into the substrate, and a bit cell that includes an IGZO transistor, where each bit cell is connected to at least one sense amplifier and is configured to store at least one bit of data in a fuse memory element or an antifuse memory element. In some embodiments, each IGZO transistor is connected to a fuse memory element. In some embodiments, each bit cell includes at least two IGZO transistors connected in series to provide an antifuse bit cell. In some embodiments, each bit cell includes more than two IGZO transistors connected to provide a memory element, such as an antifuse memory element.

[0346] Further disclosed embodiments include semiconductor devices having different layouts or designs and methods of forming the semiconductor devices described herein.

[0347] According to some embodiments, a memory device includes a substrate, a sense amplifier, and a bit cell. The sense amplifier includes a first gate-all-around field effect transistor having a first drain / source region extending into the substrate, and the bit cell includes a fuse memory element and a second gate-all-around field effect transistor. Each bit cell includes a fuse memory element having a first terminal connected to an input of the sense amplifier and a second terminal connected to the second gate-all-around field effect transistor, where the second gate-all-around field effect transistor includes a second drain / source region and a bottom dielectric isolation layer under the second drain / source region.

[0348] In some embodiments, each second wrap-around gate field effect transistor includes a bottom dielectric isolation layer in contact with the second drain / source regions. In some embodiments, the second wrap-around gate field effect transistor includes a first segment of the bottom dielectric isolation layer under one of the second drain / source regions and a second segment of the bottom dielectric isolation layer under the other of the second drain / source regions. In some embodiments, the first segment is in contact with one of the second drain / source regions, and the second segment is in contact with the other of the second drain / source regions. In some embodiments, each second wrap-around gate field effect transistor includes a segment of the bottom dielectric isolation layer extending from one of the second drain / source regions to the other of the second drain / source regions. In some embodiments, the segment is in contact with one of the second drain / source regions and the other of the second drain / source regions. In some embodiments, at least one of the second wrap-around gate field effect transistors includes a first segment of the bottom dielectric isolation layer under a first one of the first drain / source regions and a second segment of the bottom dielectric isolation layer under a second one of the first drain / source regions, and at least another of the second wrap-around gate field effect transistors includes a third segment of the bottom dielectric isolation layer extending from a third one of the second drain / source regions to a fourth one of the second drain / source regions. In some embodiments, the sense amplifier includes a plurality of third wrap-around gate field effect transistors, each third wrap-around gate field effect transistor including a plurality of third drain / source regions and a bottom dielectric isolation layer located under the plurality of third drain / source regions. In some embodiments, the sense amplifier and the bit cells are located on a plane of the semiconductor device.

[0349] According to additional embodiments, a semiconductor device includes a substrate, at least one sense amplifier, and a plurality of bit cells. The at least one sense amplifier includes a plurality of first GAA transistors having a plurality of first drain / source regions extending into the substrate. The bit cells include a plurality of IGZO transistors, each bit cell being connected to the at least one sense amplifier and configured to store at least one bit of data in a fuse or antifuse.

[0350] In some embodiments, each indium gallium zinc oxide transistor is connected to a fuse memory element. In some embodiments, each bit cell includes at least two series-connected indium gallium zinc oxide transistors to provide an antifuse bit cell. In some embodiments, at least one sense amplifier is located on a first plane of the semiconductor device, and these bit cells are located on at least one second plane of the semiconductor device, and the at least one second plane is different from the first plane of the semiconductor device. In some embodiments, the at least one second plane is located directly above the first plane. In some embodiments, at least one sense amplifier includes a plurality of second surround gate field effect transistors, each second surround gate field effect transistor includes a plurality of second drain / source regions and a bottom dielectric isolation layer, and the bottom dielectric isolation layer is located below these second drain / source regions.

[0351] According to a further disclosed aspect, a method of manufacturing a semiconductor device includes forming a substrate; forming a plurality of first GAA transistors, including forming first drain / source regions extending into the substrate, and these first GAA transistors are part of at least one sense amplifier; forming a plurality of second GAA transistors, including forming a bottom dielectric isolation layer and forming a plurality of second drain / source regions above the bottom dielectric isolation layer; and forming a plurality of fuse memory elements such that at least one of these second GAA transistors is connected to at least one of these fuse memory elements.

[0352] In some embodiments, forming these second surround gate field effect transistors includes forming these second drain / source regions in contact with the bottom dielectric isolation layer. In some embodiments, forming these second surround gate field effect transistors includes forming one of these second drain / source regions above a first section of the bottom dielectric isolation layer and forming another of these second drain / source regions above a second section of the bottom dielectric isolation layer. In some embodiments, forming these second surround gate field effect transistors includes forming one of these second drain / source regions and another of these second drain / source regions above a section of the bottom dielectric isolation layer, and the section of the bottom dielectric isolation layer extends from one of these second drain / source regions to another of these second drain / source regions. In some embodiments, forming these second surround gate field effect transistors includes forming a first one of these second drain / source regions above a first section of the bottom dielectric isolation layer and forming a second one of these second drain / source regions above a second section of the bottom dielectric isolation layer, and forming a third one of these second drain / source regions and a fourth one of these second drain / source regions above a third section of the bottom dielectric isolation layer, and the bottom dielectric isolation layer extends from the third one of these second drain / source regions to the fourth one of these second drain / source regions.

[0353] According to a further aspect disclosed, a semiconductor device includes a substrate, a plurality of first surround-gate field-effect transistors, a plurality of second surround-gate field-effect transistors, and a plurality of fuse memory elements. The plurality of first surround-gate field-effect transistors include a plurality of first drain / source regions extending into the substrate, and the first surround-gate field-effect transistors are part of at least one sense amplifier. The plurality of second surround-gate field-effect transistors include a bottom dielectric isolation layer and a plurality of second drain / source regions above the bottom dielectric isolation layer. At least one of the second surround-gate field-effect transistors is connected to at least one of the fuse memory elements.

[0354] According to a further aspect disclosed, a semiconductor device includes a substrate, at least one sense amplifier, and a plurality of bit cells. The sense amplifier includes a plurality of first surround-gate field-effect transistors and a plurality of second surround-gate field-effect transistors. The first surround-gate field-effect transistors have a plurality of first drain / source regions extending into the substrate. Each second surround-gate field-effect transistor includes a plurality of second drain / source regions and a bottom dielectric isolation layer, and the bottom dielectric isolation layer is located below the second drain / source regions. The plurality of bit cells include a plurality of indium gallium zinc oxide transistors, and each bit cell is connected to the sense amplifier and configured to store at least one bit of data in a fuse or antifuse.

[0355] The foregoing has outlined features of multiple embodiments or examples in order that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should recognize that they may readily use the present disclosure as a basis to design or modify other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments or examples introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: a substrate; a sense amplifier including a plurality of first wraparound gate field effect transistors having a plurality of first drain / source regions extending into the substrate; and A plurality of bit cells include a plurality of fuse memory elements and a plurality of second surrounding gate field effect transistors, wherein each of the bit cells includes a fuse memory element having a first terminal and a second terminal, the first terminal being connected to an input of the sense amplifier, the second terminal being connected to a second surrounding gate field effect transistor, the second surrounding gate field effect transistor including a plurality of second drain / source regions and a bottom dielectric isolation layer, and the bottom dielectric isolation layer being located below the plurality of second drain / source regions.

2. The semiconductor device according to claim 1, wherein Each of the second surrounding gate field effect transistors includes the bottom dielectric isolation layer in contact with the plurality of second drain / source regions.

3. The semiconductor device according to claim 1 or 2, wherein: Each of the second wraparound gate field effect transistors includes a first section of the bottom dielectric isolation layer below one of the plurality of second drain / source regions and a second section of the bottom dielectric isolation layer below another of the plurality of second drain / source regions.

4. The semiconductor device according to claim 3, wherein: The first segment contacts one of the plurality of second drain / source regions, and the second segment contacts another one of the plurality of second drain / source regions.

5. The semiconductor device according to claim 1 or 2, wherein: Each of the second wrap-around gate field effect transistors includes a section of the bottom dielectric isolation layer extending from one of the plurality of second drain / source regions to another of the plurality of second drain / source regions.

6. The semiconductor device according to claim 5, wherein: The segment is in contact with one of the plurality of second drain / source regions and another one of the plurality of second drain / source regions.

7. A semiconductor device, characterized in that: Include: a substrate; at least one sense amplifier including a plurality of first wraparound gate field effect transistors and a plurality of second wraparound gate field effect transistors, the plurality of first wraparound gate field effect transistors having a plurality of first drain / source regions extending into the substrate, each of the second wraparound gate field effect transistors including a plurality of second drain / source regions and a bottom dielectric isolation layer, and the bottom dielectric isolation layer is located below the plurality of second drain / source regions; as well as A plurality of bit cells include a plurality of InGaZnO transistors, each of the bit cells is connected to the at least one readout amplifier and is configured to store at least one bit of data in a fuse or an antifuse.

8. The semiconductor device according to claim 7, wherein: Each of the bit cells includes at least two of the plurality of InGaZnO transistors connected in series to provide an anti-fuse bit cell.

9. The semiconductor device according to claim 7 or 8, wherein: The at least one sense amplifier is located on a first plane of the semiconductor device, and the plurality of bit cells are located on at least one second plane of the semiconductor device, the at least one second plane being different from the first plane of the semiconductor device.

10. A semiconductor device, characterized in that: Include: a substrate; a plurality of first wraparound gate field effect transistors including a plurality of first drain / source regions extending into the substrate, wherein the plurality of first wraparound gate field effect transistors are part of at least one sense amplifier; A plurality of second wrap-around gate field effect transistors, comprising a plurality of second drain / source regions and a bottom dielectric isolation layer, wherein the bottom dielectric isolation layer is located below the plurality of second drain / source regions; as well as A plurality of fuse memory elements, wherein at least one of the plurality of second wrap-around gate field effect transistors is connected to at least one of the plurality of fuse memory elements.

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