Semiconductor packaging structure and ink box

Abstract

The utility model provides a semiconductor packaging structure and an ink box, the packaging structure comprises a heat dissipation member, and the heat dissipation member comprises a first conductive pin group and a second conductive pin group; a pin group of the chip array group is connected with the first conductive pin group in a hybrid bonding mode, and the first conductive pin group is electrically connected with the second conductive pin group through a circuit layer; the silicon intermediate layer is located below the circuit layer, the top of the silicon intermediate layer is provided with a rewiring layer, and the second conductive pin group forms heterogeneous interconnection in the rewiring layer; the packaging structure is applied to the circuit board of the ink box. According to the technical scheme, high-density interconnection is achieved by arranging the 2.5 D structures between the core particles, and the pin integration level of a final finished product is improved; and the 3D stacking structures among the core particles are arranged, so that the signal delay is reduced, and the data processing speed of a final finished product is increased.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and particularly to a semiconductor packaging structure and an ink cartridge. Background Art

[0002] As the requirements for the processing speed and the integration degree of input / output pins of ink cartridge chips are getting higher and higher, the traditional wire bonding, 2D, and 2.5D packaging technologies can no longer meet the needs.

[0003] In order to solve the above problems, a technical solution of a 3.5D semiconductor packaging structure is proposed. Summary of the Utility Model

[0004] To overcome the existing problems, this application provides a semiconductor packaging structure, including:

[0005] A heat dissipation component, the heat dissipation component includes a graphene layer and a first conductive pin group and a second conductive pin group that are formed based on the graphene layer and are respectively located on opposite sides of the graphene layer;

[0006] A chip array group, the chips in the chip array group are stacked on the graphene layer through 3D through-silicon vias, the pin group of the chip array group is connected to the first conductive pin group through 3D through-silicon vias, and the first conductive pin group and the second conductive pin group are connected by hybrid bonding through the circuit layer at the bottom in the graphene layer;

[0007] A silicon interposer, the silicon interposer is located below the circuit layer, and a redistribution layer is provided on the top, and the second conductive pin group forms homogeneous or heterogeneous interconnections in the redistribution layer.

[0008] Further, the semiconductor packaging structure further includes a substrate for the 3.5D structure, the substrate is disposed below the silicon interposer and is electrically connected to the silicon interposer through copper pillars or solder balls. Wherein, the silicon interposer is provided with through-silicon vias penetrating the silicon interposer, and the chip array is disposed on the silicon interposer in the horizontal direction and forms an electrical connection with the through-silicon vias.

[0009] Preferably, there are two layers of redistribution layers, and the two layers of redistribution layers are connected through vias.

[0010] Preferably, the thickness of the silicon interposer is 90um.

[0011] Preferably, the copper pillar is a bump structure.

[0012] On the other hand, this application provides an ink cartridge, the ink cartridge includes a circuit board and the above semiconductor packaging structure, and the semiconductor packaging structure is mounted on the circuit board.

[0013] As can be seen from the above technical solutions, compared with the prior art, the present utility model has at least the following advantages and positive effects:

[0014] The 3.5D packaging structure of this application is essentially an integration of the advantages of 2.5D and 3D structures. By setting a silicon interposer with a 2.5D structure, high-density interconnection between die is achieved, improving the pin integration of the final product; a 3D stacking structure between die is also set to optimize the connection performance between die, reduce signal delay, and improve the data processing speed of the final product. On the other hand, a graphene layer with a heat dissipation function is added to this application, enabling the heat dissipated during the operation of the chip to be dissipated, especially in areas where the chip temperature is too high, reducing the hot spot value of the chip, facilitating the stable operation of the chip, and improving the yield and reliability of semiconductor packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The present utility model will be further described below in conjunction with the drawings and embodiments.

[0016] Figure 1 It is a schematic diagram of the overall structure of a semiconductor packaging structure provided by an embodiment of this application;

[0017] Figure 2 It is another schematic diagram of the overall structure of a semiconductor packaging structure provided by an embodiment of this application;

[0018] Figure 3 It is a schematic diagram of the structure of a substrate applied to a semiconductor packaging structure provided by an embodiment of this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] Embodiment 1:

[0020] This embodiment gives a schematic diagram of the overall structure of a semiconductor packaging structure, as Figure 1 shown, including a chip array 10, a heat sink 20, a silicon interposer 30, a substrate 40, a 3D silicon through hole 201, a redistribution layer 301, a 2.5D silicon through hole 302, copper pillars 202, and copper pillars 401.

[0021] Further, the chip array 10 includes a plurality of chips 101, and the chip 101 is a die, that is, a prefabricated wafer with specific functions and can be combined and integrated.

[0022] The chips 101 are stacked in the vertical direction, and 3D silicon through holes 201 (TSV) are formed in the middle of the chips 101, and the punching positions of the chips 101 correspond up and down; by injecting conductive materials into the TSV, the chips 101 achieve hybrid bonding electrical connection at the shortest distance and form a chip array 10 with multiple functional modules. The chips 101 can be homogeneous or heterogeneous.

[0023] Furthermore, the output pin group of the chip array 10 reduces heat accumulation through the heat sink 20 to avoid damaging the chips. The heat sink 20 can be made based on a graphene layer, which can be single-layer or multi-layer. Single-layer graphene has a thermal conductivity as high as 5000 W / mK, and the number of layers of the graphene layer can be set according to the number of chips in the chip array 10.

[0024] Furthermore, the heat sink 20 further includes a first conductive pin group. The first conductive pins are used to connect the output pin group of the chip array 10 to the graphene layer for heat dissipation. After heat dissipation, the pin group of the chip array 10 is connected to the second conductive pin group of the heat sink 20 and enters the circuit layer of the heat sink 20, and hybrid bonding is performed in the circuit layer. By implanting bump-shaped copper pillars 202 on the outer surface of the circuit layer, the second conductive pin group can be connected to the silicon interposer 30; after entering the silicon interposer 30, the solder joints and arrangements of the second conductive pin group can be re-planned on the redistribution layer 301 (RDL) on the top of the silicon interposer according to actual needs, that is, the circuit routing of the chip array is optimized. Preferably, the thickness of the silicon interposer is 80 - 100 um. The second conductive pin group completes the routing reorganization in the redistribution layer 301 and passes through the silicon interposer 30 through the 2.5D through-silicon via 302, and is connected to the substrate 40 through the copper pillar 401. The copper pillar is in a bump shape.

[0025] Embodiment 2:

[0026] This embodiment gives another overall structural schematic diagram of the semiconductor packaging structure, as Figure 2 shown, including a chip array 10, a heat sink 20, a silicon interposer 30, a substrate 40, a 3D through-silicon via 201, a redistribution layer 301, a 2.5D through-silicon via 302, solder balls 203, and solder balls 402.

[0027] Furthermore, the chip array 10 includes a number of chips 101, and the chip 101 is a chiplet, that is, a pre-fabricated wafer with specific functions and combinable integration.

[0028] The chips 101 are stacked in the vertical direction, and 3D through-silicon vias 201 (TSVs) are created in the middle of the chips 101, and the punching positions of the chips 101 correspond up and down; by injecting conductive materials into the TSVs, the chips 101 achieve hybrid bonding electrical connection at the shortest distance and form a chip array 10 with multiple functional modules. The chips 101 can be homogeneous or heterogeneous.

[0029] Further, the output pin group of the chip array 10 reduces heat accumulation through the heat sink 20 to avoid damaging the chips. The heat sink 20 can be made based on a graphene layer, and the graphene layer can be single-layer or multi-layer. Single-layer graphene has a thermal conductivity as high as 5000 W / mK, and the number of layers of the graphene layer can be set according to the number of chips in the chip array 10.

[0030] Further, the heat sink 20 further includes a first conductive pin group. The first conductive pins are used to connect the output pin group of the chip array 10 to the graphene layer for heat dissipation. After heat dissipation, the pin group of the chip array 10 is connected to the second conductive pin group of the heat sink 20 and enters the circuit layer of the heat sink 20, and hybrid bonding is performed in the circuit layer. By implanting solder balls 203 at the end of the second conductive pin group, the second conductive pin group can be connected to the silicon interposer 30; after entering the silicon interposer 30, the solder joints and arrangements of the second conductive pin group can be re-planned in the redistribution layer 301 (RDL) on the top of the silicon interposer according to actual requirements, that is, the circuit routing of the chip array is optimized. Preferably, the thickness of the silicon interposer is 80 - 100 um. The second conductive pin group completes routing reorganization in the redistribution layer 301 and passes through the silicon interposer 30 through the 2.5D through-silicon via 302, and is connected to the substrate 40 through the solder ball 402.

[0031] Embodiment 3:

[0032] This embodiment gives a schematic structural diagram of a substrate applied to a semiconductor packaging structure, as Figure 3 shown, the substrate 40 includes a carrier 400, a dielectric layer 401, a first copper seed layer 402, a second copper seed layer 403, and a sacrificial layer 404. The first copper seed layer 402 and the dielectric layer 401 are fixed on the carrier 400 from top to bottom in sequence, and the first side surface of the dielectric layer 401 is on the side of the dielectric layer 401 away from the first copper seed layer 402.

[0033] On the other hand, when manufacturing the dielectric layer 401, the dielectric layer 401 can be prepared on the sacrificial layer 404 by using PECVD or RF vapor deposition technology to ensure the uniformity of the dielectric layer 401. After the process is completed, mechanical separation is adopted so that the side surface of the dielectric layer 401 in contact with the sacrificial layer 404 is the first side surface.

[0034] The substrate 40 further includes a second copper seed layer 403. The second copper seed layer 403 is provided between the carrier 400 and the dielectric layer 401 to increase the bonding force between the dielectric layer 401 and the carrier 400. Further, the carrier 400 can be made of glass or metal, and the dielectric layer can be made of ABF resin.

[0035] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly illustrating the present utility model, rather than limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all implementation manners here. And the obvious changes or modifications derived therefrom are still within the protection scope of the present utility model.

Claims

1. A semiconductor packaging structure, characterized in that: include: A heat sink, the heat sink comprising a graphene layer at the top and a circuit layer at the bottom, and further comprising a first conductive pin group and a second conductive pin group formed based on the graphene layer and located at opposite sides of the graphene layer; A chip array group, wherein the chips in the chip array group are interconnected through 3D through silicon vias and stacked on the graphene layer, the pin group of the chip array group is connected to the first conductive pin group through 3D through silicon vias, and the first conductive pin group and the second conductive pin group are connected through hybrid bonding of the circuit layer; A silicon interposer is located below the circuit layer and has a redistribution layer on the top. The second conductive pin group is electrically connected to the silicon interposer through copper pillars or solder balls, and forms homogeneous or heterogeneous interconnections in the redistribution layer.

2. The semiconductor package structure according to claim 1, wherein: The semiconductor packaging structure further includes a substrate for a 3.5D structure, wherein the substrate is disposed below the silicon interposer and is electrically connected to the silicon interposer via copper pillars or solder balls.

3. The semiconductor package structure according to claim 1, wherein: The silicon interposer is provided with a 2.5D silicon through via that penetrates the silicon interposer, and the chip array is arranged on the silicon interposer along a horizontal direction and is electrically connected with the silicon through via.

4. The semiconductor package structure according to claim 1, wherein: The redistribution layer has two layers, and the two redistribution layers are connected through vias.

5. The semiconductor package structure according to claim 1, wherein: The thickness of the silicon interposer is 90 um.

6. The semiconductor package structure according to claim 1 or 2, characterized in that: The copper column is a bump structure.

7. An ink cartridge, characterized in that: The ink cartridge comprises a circuit board and a semiconductor package structure as claimed in any one of claims 1 to 6, wherein the semiconductor package structure is mounted on the circuit board.

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