Package substrate
By embedded conductive traces in the insulating layer, the ultra-thin line width/line distance specifications are formed, and the thinning and yield problems caused by large line width/line distance and multi-layer lines in the prior art are solved, and high-density wiring and high-yield packaging substrates are realized.
Patent Information
- Application Number
- CN202421738586.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2024-07-16
- Filing Date
- 2024-07-22
- Publication Date
- 2025-07-01
- Estimated Expiration
- 2034-07-22
AI Technical Summary
In the existing packaging substrate manufacturing method, due to the limitations of traditional manufacturing processes, the line width/line distance is large, which is difficult to meet the needs of thinning and high-density wiring, and the multi-layer circuit structure leads to a lower yield.
By embedded conductive traces in the insulating layer and forming conductive traces of ultra-fine line width/line distance specifications, combined with conductive vias, the number of lines is reduced to improve wiring density and yield.
The ultra-thin line width/line distance specification is realized, which reduces the total number of wiring layers, meets product functions and thinning needs, and improves yield.
Smart Images
Figure CN223052145U_ABST
Abstract
Description
Technical Field
[0001] This application relates to a packaging substrate, especially a packaging substrate that can meet the thinning requirements and its manufacturing method. Background Art
[0002] With the booming development of the electronics industry, electronic products tend to be thinner, lighter, shorter and smaller in form, and are developed towards high performance, high functionality and high speed in terms of functions. Therefore, in order to meet the requirements of high integration and miniaturization of semiconductor devices, in the packaging process, packaging substrates with designs such as thinning, low warpage and high-density wiring are often used.
[0003] Figures 1A to 1E It is a cross-sectional schematic diagram of the manufacturing method of the existing packaging substrate 1.
[0004] As Figure 1A shown, a core layer 10 is provided, and metal layers 11 are disposed on both the upper and lower sides thereof.
[0005] As Figure 1B shown, a funnel-shaped through hole 100 penetrating the core layer 10 and the metal layer 11 is formed on the core layer 10, and then a conductive layer 12 is formed on the metal layer 11 and the hole wall of the through hole 100.
[0006] As Figure 1C shown, a resist layer 19 having a patterned opening 190 is formed on the conductive layer 12 on the metal layer 11, and then a wiring layer 14 is formed in the opening 190, and a conductive via 13 electrically connecting the wiring layer 14 is formed in the through hole 100, and the line width / line pitch of the wiring layer 14 is 20 μm / 20 μm.
[0007] As Figure 1D shown, the resist layer 19 and the conductive layer 12 and the metal layer 11 thereunder are removed.
[0008] As Figure 1E shown, a circuit structure 15 electrically connecting each wiring layer 14 is formed on both the upper and lower sides of the core layer 10, and then a solder mask layer 16 is formed on each circuit structure 15. Among them, the circuit structure 15 includes a dielectric layer 150 and a circuit layer 151 electrically connecting the wiring layer 14, and the line width / line pitch of the circuit layer 151 is 20 μm / 20 μm.
[0009] However, in the manufacturing method of the existing packaging substrate, due to the limitation of forming wiring layers 14 with relatively large line width / line pitch on both the upper and lower sides of the core layer 10 in the traditional process, when meeting the fine circuit requirements of product functions, it is necessary to form the circuit structure 15 on both the upper and lower sides of the core layer 10, resulting in difficulty in reducing the number of wiring layers (such as eight layers in total for the upper and lower sides) of the existing packaging substrate 1 and unable to meet the thinning requirements.
[0010] In addition, in the existing packaging substrate 1, multiple wiring layers 151 need to be fabricated on the core layer 10 to achieve the required product functions. However, there is a yield loss for each layer during the build-up process of the packaging substrate. Therefore, as the number of layers of the wiring layer 151 increases, the yield becomes lower, making it difficult to improve the yield when fabricating the wiring structure 15.
[0011] Therefore, how to overcome the various problems of the above-mentioned prior art has actually become an urgent issue to be solved currently. Summary of the Utility Model
[0012] In view of the above-mentioned various deficiencies of the prior art, the present application provides a packaging substrate, including: an insulating layer having at least one conductive through-hole penetrating the insulating layer; and conductive traces embedded in the insulating layer and electrically connected to the conductive through-hole.
[0013] The present application also provides a method for manufacturing a packaging substrate, including: providing a plurality of carriers having a metal layer; forming conductive traces on the metal layer to form a substrate structure; bonding a plurality of the substrate structures to opposite sides of an insulating layer with their metal layers, so that the conductive traces are embedded in the insulating layer; removing the carriers to expose the conductive traces; and forming at least one conductive through-hole penetrating the insulating layer on the conductive traces to electrically connect the conductive through-hole to the conductive traces.
[0014] In the foregoing packaging substrate and its manufacturing method, the line width / line pitch of the conductive traces is 7 μm / 10 μm.
[0015] In the foregoing packaging substrate and its manufacturing method, it further includes removing a part of the material of the conductive traces when removing the metal layer, so that the surface of the conductive traces is lower than the surface of the insulating layer to form a recess.
[0016] In the foregoing packaging substrate and its manufacturing method, it further includes forming a pad portion stacked on the conductive traces at the end of the conductive through-hole.
[0017] In the foregoing packaging substrate and its manufacturing method, it further includes forming a wiring structure on the insulating layer that is electrically connected to the conductive traces or the conductive through-holes. For example, the wiring structure includes at least one dielectric layer and a wiring layer that is electrically connected to the conductive traces or the conductive through-holes. Further, the line width / line pitch of the conductive traces is smaller than that of the wiring layer. Alternatively, it may include forming an insulating protective layer on the wiring structure.
[0018] As can be seen from the above, for the encapsulation substrate and its manufacturing method of the present application, the conductive traces are mainly embedded in the insulating layer, which is conducive to manufacturing conductive traces with ultra-fine line widths / line pitches, and thus is conducive to increasing the wiring density according to the requirements of product functions. That is, the circuit structure can be configured or not configured according to the requirements. Therefore, compared with the prior art, the encapsulation substrate of the present application can significantly reduce the total number of wiring layers to simultaneously meet the requirements of product functions and thinning.
[0019] Furthermore, even if the circuit structure is configured, the number of circuit layers can be less than that of the existing circuit layers. Therefore, compared with the prior art, even if the circuit structure is added to the encapsulation substrate of the present application, the total number of wiring layers can be significantly reduced to simultaneously meet the requirements of product functions and thinning.
[0020] Also, the encapsulation substrate of the present application can achieve the required product functions with fewer total wiring layers on the insulating layer. Therefore, compared with the prior art, the manufacturing method of the present application can significantly improve the yield rate when manufacturing the circuit structure. Description of the Drawings
[0021] Figures 1A to 1E It is a schematic cross-sectional view of the manufacturing method of the existing encapsulation substrate.
[0022] Figures 2A to 2H It is a schematic cross-sectional view of the manufacturing method of the encapsulation substrate of the present application.
[0023] Figure 3 It is a schematic cross-sectional view of another aspect of the encapsulation substrate of the present application.
[0024] Description of the Main Component Symbols
[0025] 1, 2, 3 Encapsulation Substrate
[0026] 10 Core Layer
[0027] 100, 200 Through-Holes
[0028] 11, 92 Metal Layers
[0029] 12, 22 Conductive Layers
[0030] 13, 23 Conductive Through-Holes
[0031] 14 Wiring Layer
[0032] 15, 35 Circuit Structures
[0033] 150, 350 Dielectric Layers
[0034] 151, 351 Circuit Layers
[0035] 16 Solder Mask Layer
[0036] 19, 29 Barrier Layers
[0037] 190,290 opening
[0038] 2a substrate structure
[0039] 20 insulating layer
[0040] 21 conductive trace
[0041] 210 recess
[0042] 24 pad portion
[0043] 36 insulating protective layer
[0044] 9 carrier
[0045] 90 plate body
[0046] 91 release layer. Detailed implementation manners
[0047] The following illustrates the implementation manners of the present application through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification.
[0048] It should be noted that the structures, ratios, sizes, etc. shown in the attached drawings of this specification are only used to cooperate with the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limited conditions that the present application can be implemented. Therefore, they do not have any technical substance. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects that the present application can produce and the purposes that can be achieved, should still fall within the scope that the technical content disclosed in the present application can cover. At the same time, the terms such as "upper", "first", "second", "one", etc. cited in this specification are only for the convenience of clear narration, and are not used to limit the scope that the present application can be implemented. The change or adjustment of their relative relationships, without substantial change in the technical content, should also be regarded as the scope that the present application can be implemented.
[0049] Figures 2A to 2H It is a schematic cross-sectional view of the manufacturing method of the packaging substrate 2 of the present application.
[0050] As Figure 2A shown, a plurality of carriers 9 are provided (for simplicity of illustration, only a single carrier 9 is shown in this embodiment), which include a plate body 90, a release layer 91 provided on one side of the plate body 90, and a metal layer 92 provided on the release layer 91.
[0051] In this embodiment, the plate body 90 is a temporary carrier, and the metal layer 92 is a copper foil.
[0052] As Figure 2BAs shown, a patterned wiring process is performed through the metal layer 92 to form a conductive trace 21 on the metal layer 92, thereby forming a substrate structure 2a.
[0053] In this embodiment, the metal layer 92 serves as a seed layer for electroplating copper material to be used as the conductive trace 21.
[0054] Furthermore, the conductive trace 21 has an ultra-fine line width / line pitch specification, such as a line width / line pitch of 7 μm / 10 μm.
[0055] As Figure 2C shown, a plurality of substrate structures 2a are bonded to opposite sides of an insulating layer 20 through their metal layers 92.
[0056] In this embodiment, each substrate structure 2a is bonded to the insulating layer 20 by a pressing method, such that the conductive trace 21 is embedded in the insulating layer 20 to form an embedded circuit.
[0057] Furthermore, the insulating layer 20 is a dielectric material such as Prepreg (PP), Polybenzoxazole (PBO), Polyimide (PI), or others.
[0058] As Figure 2D shown, the plate body 90 is removed through the release layer 91, leaving the metal layer 92 on opposite sides of the insulating layer 20.
[0059] As Figure 2E shown, the metal layer 92 is removed to expose the surface of the insulating layer 20 and the conductive trace 21.
[0060] In this embodiment, the metal layer 92 is removed by etching, slightly etching a part of the material of the conductive trace 21 such that the surface of the conductive trace 21 is lower than the surface of the insulating layer 20 to form a recess 210.
[0061] As Figure 2F shown, corresponding to the conductive trace 21, at least one through hole 200 penetrating the insulating layer 20 is formed on the conductive trace 21, and then a conductive layer 22 is formed on the conductive trace 21, the insulating layer 20, and the hole wall of the through hole 200.
[0062] In this embodiment, the conductive layer 22 is fabricated by a copper plating process, and the through hole 200 can be formed by a laser method, and its shape is not particularly limited. For example, the through hole 200 can be in a straight cylindrical shape, a conical shape, or a funnel shape as Figure 2F shown.
[0063] As Figure 2GAs shown, a resist layer 29 with a patterned opening 290 is formed on the conductive layer 22 on the conductive trace 21 and the insulating layer 20, so that a part of the surface of the conductive layer 22 is exposed outside the opening 290, and then a conductive via 23 electrically connecting the conductive trace 21 is formed in the via 200.
[0064] In this embodiment, the opening 290 exposes the via 200 and the conductive layer 22 around it, so that the end of the conductive via 23 forms a pad portion 24 stacked on the conductive trace 21 around the via 200. For example, the conductive via 23 and its pad portion 24 are made by electroplating copper.
[0065] As Figure 2H shown, the resist layer 29 and the conductive layer 22 thereunder are removed to expose the surface of the insulating layer 20 and the conductive trace 21, so as to obtain the packaging substrate 2.
[0066] Please refer to Figure 3 , in this embodiment, a circuit structure 35 electrically connecting the conductive trace 21 or the conductive via 23 can be formed on opposite sides of each insulating layer 20 as required, and an insulating protective layer 36 such as a solder mask is formed on each circuit structure 35 to obtain another packaging substrate 3.
[0067] In this embodiment, the circuit structure 35 includes at least one dielectric layer 350 and a circuit layer 351 electrically connecting the conductive trace 21 or the conductive via 23. For example, the circuit layer 351 is made of copper and is in the specification of a redistribution layer (RDL).
[0068] Furthermore, the line width / line pitch of the conductive trace 21 is smaller than that of the circuit layer 351. For example, the line width / line pitch of the circuit layer 351 is 20 microns / 20 microns.
[0069] Also, the dielectric layer 350 is formed of materials such as Ajinomoto build-up film (ABF), polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or other dielectric materials, and the insulating protective layer 36 can be green paint.
[0070] Therefore, the manufacturing method of the present application mainly first manufactures the conductive trace 21 with an ultra-fine line width / line pitch specification, and embeds the conductive trace 21 in opposite surfaces of the insulating layer 20, which is beneficial to improving the wiring density according to the requirements of product functions, and the circuit structure 35 can be selectively configured as required. Therefore, compared with the prior art, the packaging substrate 2 of the present application can greatly reduce the total number of wiring layers (such asFigure 2H There are two layers, upper and lower as shown, to simultaneously meet the requirements of product function and thinning.
[0071] Furthermore, even if the circuit structure 35 is configured, the number of circuit layers 351 (such as two layers, upper and lower) is less than the number of existing circuit layers 151 (such as six layers, upper and lower). Therefore, compared with the prior art, even if the circuit structure 35 is added to the packaging substrate 3 of the present application, the total number of wirings (including the conductive traces 21 and the circuit layers 351) can be significantly reduced (such as Figure 3 There are four layers, upper and lower as shown, to simultaneously meet the requirements of product function and thinning.
[0072] Also, the packaging substrate 3 of the present application can achieve the required product function with a smaller total number of wiring layers (such as Figure 3 There are four layers, upper and lower as shown). Therefore, compared with the prior art, when manufacturing the circuit structure 35 with fewer layers, the yield of the manufacturing method of the present application can be significantly improved.
[0073] The present application also provides a packaging substrate 2, 3, including: an insulating layer 20 and at least one conductive trace 21.
[0074] The insulating layer 20 has at least one conductive via 23 penetrating through the insulating layer 20.
[0075] The conductive trace 21 is embedded in the insulating layer 20 and is electrically connected to the conductive via 23.
[0076] In one embodiment, the line width / line pitch of the conductive trace 21 is 7 μm / 10 μm.
[0077] In one embodiment, the surface of the conductive trace 21 is lower than the surface of the insulating layer 20 to form a recess 210.
[0078] In one embodiment, a pad portion 24 stacked on the conductive trace 21 is formed at the end of the conductive via 23.
[0079] In one embodiment, the packaging substrate 3 further includes a circuit structure 35 formed on the insulating layer 20, which is electrically connected to the conductive trace 21 or the conductive via 23. For example, the circuit structure 35 includes at least one dielectric layer 350 and at least one circuit layer 351 electrically connected to the conductive trace 21 or the conductive via 23. Further, the line width / line pitch of the conductive trace 21 is smaller than the line width / line pitch of the circuit layer 351. Alternatively, the packaging substrate 3 further includes an insulating protective layer 36 formed on the circuit structure 35.
[0080] In summary, for the packaging substrate and its manufacturing method of the present application, by mainly fabricating conductive traces with an ultra-fine line width / line pitch specification and embedding the conductive traces in the insulating layer, it is beneficial to increase the wiring density according to the requirements of product functions. Therefore, the packaging substrate of the present application can significantly reduce the number of total wiring layers to simultaneously meet the requirements of product functions and thinning.
[0081] Furthermore, even if the circuit structure is configured, the number of circuit layers is less than that of the existing circuit layers. Therefore, even if the circuit structure is added to the packaging substrate of the present application, the number of total wiring layers can be significantly reduced to simultaneously meet the requirements of product functions and thinning.
[0082] Also, the packaging substrate of the present application can achieve the required product functions with a smaller number of total wiring layers on the insulating layer. Therefore, when manufacturing the circuit structure by the manufacturing method of the present application, the yield can be significantly improved.
[0083] The above embodiments are used to exemplarily illustrate the principles and effects of the present application, rather than to limit the present application. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the present application. Therefore, the scope of the claimed protection of the present application shall be as set forth in the claims.
Claims
1. A packaging substrate, characterized in that: include: an insulating layer, wherein at least one conductive through hole is formed through the insulating layer; as well as The conductive trace is embedded in the insulating layer and electrically connected to the conductive through hole. A pad portion stacked on the conductive trace is formed at the end of the conductive through hole.
2. The packaging substrate according to claim 1, wherein: The line width / line spacing of the conductive trace is 7 microns / 10 microns.
3. The packaging substrate according to claim 1, wherein: The surface of the conductive trace is lower than the surface of the insulating layer to form a recess.
4. The packaging substrate according to claim 1, wherein: Also included is a circuit structure formed on the insulating layer, which is electrically connected to the conductive trace or conductive through hole.
5. The packaging substrate according to claim 4, characterized in that The circuit structure includes at least one dielectric layer and at least one circuit layer electrically connected to the conductive trace or the conductive through hole.
6. The packaging substrate according to claim 5, characterized in that The line width / line spacing of the conductive trace is smaller than the line width / line spacing of the circuit layer.
7. The packaging substrate according to claim 4, wherein: The packaging substrate also includes an insulating protection layer formed on the circuit structure.