Flip chip packaging structure

Abstract

A flip chip package structure includes a semiconductor chip and a carrier having a plurality of electrical connection pads, and the semiconductor chip is connected to a second solder on the electrical connection pads of the carrier through a first solder, the thickness of the insulation protection layer on the surface of the bearing part is changed according to the thickness of the first welding flux, the thickness of the second welding flux and the thickness of the electric connecting pad, so that the insulation protection layer has a certain thickness to avoid the bridging problem of the welding flux, and meanwhile, the problem that holes are formed in the welding flux due to the over-high thickness can be avoided.

Description

Technical Field

[0001] This application relates to a semiconductor package structure, particularly a flip-chip package structure. Background Art

[0002] A flip-chip ball grid array (FCBGA) semiconductor package is one in which the active surface of a chip is electrically connected to a surface of a substrate through a plurality of solders, and a plurality of solder balls serving as input / output (I / O) terminals are implanted on the other surface of the substrate; this semiconductor package can significantly reduce the volume, and at the same time eliminate the design of existing wires, thereby reducing impedance and improving electrical performance to avoid signal decay during transmission. Therefore, it has indeed become the mainstream packaging technology for next-generation chips.

[0003] However, as Figure 1A shown, if the height of the dielectric layer 110 on the surface of the substrate 11 of the aforementioned semiconductor package 1 is designed too low, solder overflow may occur, causing electrical bridging problems between adjacent solders; correspondingly, as Figure 1B shown, if the height of the dielectric layer 110 on the surface of the substrate 11 of the aforementioned semiconductor package 1 is designed too high, holes V will be formed between the solder 13 and the side wall of the opening of the dielectric layer 110.

[0004] Therefore, how to overcome the problems of the above-mentioned prior art has actually become an urgent issue to be solved currently. Summary of the Utility Model

[0005] In view of the above-mentioned various deficiencies of the prior art, this application provides a flip-chip package structure, including: a carrier, including: a body; a plurality of electrical connection pads formed on a surface of the body; and an insulating protective layer formed on the surface of the body and on the electrical connection pads, and exposing the plurality of electrical connection pads outside the insulating protective layer; and an electronic component having opposite active and non-active surfaces, and a plurality of first solders are provided on the active surface, and a plurality of second solders are provided on the plurality of electrical connection pads of the carrier for the electronic component to be placed on the plurality of second solders of the carrier with the plurality of first solders; wherein, the thickness H of the insulating protective layer of the carrier satisfies the following conditions: (a + b) * 0.4 + c ≤ H ≤ (a + b) * 0.6 + c, the thickness of the first solder is a, the thickness of the second solder is b, and the thickness of the electrical connection pad is c.

[0006] In the aforementioned flip-chip package structure, a plurality of conductive bumps are provided on the active surface, and the plurality of first solders are provided on the plurality of conductive bumps.

[0007] In the above flip-chip package structure, the body is provided with a circuit layer.

[0008] In the above flip-chip package structure, the plurality of electrical connection pads are electrically connected to the circuit layer.

[0009] In the above flip-chip package structure, the carrier is a substrate, a circuit structure or an interposer.

[0010] By implementing this application, it mainly makes the thickness of the insulating protective layer of the carrier match the thickness of the first solder at the electronic component end and the thickness of the second solder at the carrier end, as well as the thickness of the electrical connection pads on the carrier, and changes it to have a certain thickness as a barrier wall to avoid the problem of adjacent solder bridging. At the same time, it can also avoid the problem of solder holes caused by too high a thickness. At the same time, the above flip-chip package structure can solve the existing technical problems in the industry without adding new development processes and materials or purchasing machines, so there will be no large amount of additional cost expenditure. Moreover, the flip-chip package structure of this application can solve the existing problems without adding or reducing components, so it has a high acceptance rate among customers and the market. Brief Description of the Drawings

[0011] Figure 1A and Figure 1B is a cross-sectional schematic view of an existing flip-chip ball grid array semiconductor package.

[0012] Figure 2 is a cross-sectional schematic view of the flip-chip package structure of this application.

[0013] Main Component Symbol Description

[0014] 1 Semiconductor Package

[0015] 11 Substrate

[0016] 110 Dielectric Layer

[0017] 13 Solder

[0018] 2 Flip-Chip Package Structure

[0019] 21 Carrier

[0020] 22 Electronic Component

[0021] 210 Body

[0022] 211 Electrical Connection Pad

[0023] 212 Insulating Protective Layer

[0024] 2101 Circuit Layer

[0025] 22 Electronic Component

[0026] 220 Conductive Bump

[0027] 221 Active surface

[0028] 222 Non - active surface

[0029] 231 First solder

[0030] 232 Second solder

[0031] a, b, c, H Thickness

[0032] S Electrical bridging

[0033] V Hole Specific implementation mode

[0034] The following uses specific embodiments to illustrate the implementation mode of the present application. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification.

[0035] It should be noted that the structures, ratios, sizes, etc. shown in the attached drawings of this specification are only used to cooperate with the content disclosed in the specification for those skilled in the art to understand and read, and are not used to limit the limiting conditions for the implementation of the present application. Therefore, they do not have technical substantive significance. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects that the present application can produce and the purposes that can be achieved, should still fall within the scope covered by the technical content disclosed in the present application. At the same time, the terms such as "upper", "first", "second", and "one" cited in this specification are only for the convenience of clear narration and are not used to limit the scope for the implementation of the present application. The change or adjustment of their relative relationships, without substantial change in the technical content, should also be regarded as the scope for the implementation of the present application.

[0036] Figure 2 It is a cross - sectional schematic diagram of the flip - chip package structure 2 of the present application. The flip - chip package structure includes a carrier 21 and an electronic component 22. Among them, the electronic component 22 is flip - chip placed and electrically connected to the carrier 21.

[0037] The aforementioned carrier 21 is, for example, a substrate with a core layer and a circuit structure or a circuit structure without a core layer. The circuit structure forms a circuit layer on a dielectric material, such as a redistribution layer (RDL for short). Additionally, the carrier 21 can also be an interposer.

[0038] In this embodiment, the carrier 21 includes a body 210; a plurality of electrical connection pads 211 formed on a surface of the body 210; and an insulating protective layer 212 formed on the surface of the body 210 and on the plurality of electrical connection pads 211, with the plurality of electrical connection pads 211 exposed from the insulating protective layer 212.

[0039] The body 210 is provided with a circuit layer 2101. The plurality of electrical connection pads 211 are electrically connected to the circuit layer 2101, and the insulating protective layer 212 is, for example, a dielectric material, green paint, ink, or solder resist material.

[0040] The aforementioned electronic component 22 is placed on the carrier 21 and electrically connected to the plurality of electrical connection pads 211. The electronic component 22 can be an active component, a passive component, or a combination thereof. The active component can be a semiconductor chip such as an application processor (AP) for mobile devices such as mobile phones or other computing chips, and the passive components are, for example, resistors, capacitors, and inductors.

[0041] In this embodiment, the electronic component 22 is a semiconductor chip having opposite active surfaces 221 and non-active surfaces 222, and a plurality of conductive bumps 220 are provided on the active surface 221. The conductive bumps 220 are, for example, copper pillars.

[0042] When the electronic component 22 is flip-chip placed on the carrier 21, a plurality of first solders 231 are mainly provided on the plurality of conductive bumps 220 of the electronic component 22, and a plurality of second solders 232 are provided on the plurality of electrical connection pads 211 of the carrier 21 for the electronic component 22 to be placed on the second solders 232 of the carrier 21 through the first solders 231.

[0043] In this embodiment, the thickness of the first solder 231 is a, the thickness of the second solder 232 is b, and the thickness of the electrical connection pad 211 is c. Then, the thickness H of the insulating protective layer 212 provided on the body 210 of the carrier 21 needs to meet the following conditions: (a + b) * 0.4 + c ≤ H ≤ (a + b) * 0.6 + c, so that the thickness H of the insulating protective layer 212 is appropriate to avoid problems of being too low or too high.

[0044] Therefore, the flip-chip package structure of the present application mainly varies the thickness of the insulating protective layer of the carrier in coordination with the thickness of the first solder at the electronic component end, the thickness of the second solder at the carrier end, and the thickness of the electrical connection pads on the carrier, so that it has a certain thickness as a barrier wall according to the actual situation to avoid the problem of adjacent solders bridging, and at the same time, it can also avoid the problem of solder holes caused by excessive thickness.

[0045] In addition, the foregoing flip-chip package structure can solve the problems of the existing technologies in the industry without adding new development processes and materials or purchasing machines, so there will be no substantial additional cost expenditures. Moreover, the flip-chip package structure of the present application can solve the existing problems without adding or reducing components, and has a high acceptance rate among customers and the market.

[0046] The above embodiments are only used to exemplarily illustrate the principles and effects of the present application, rather than to limit the present application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of the present application. Therefore, the scope of the patent protection of the present application shall be as listed in the following patent application scope.

Claims

1. A flip chip packaging structure, characterized in that: include: The carrier comprises: ontology; A plurality of electrical connection pads formed on a surface of the body; and an insulating protection layer formed on the surface of the body and the electrical connection pads, and the plurality of electrical connection pads are exposed outside the insulating protection layer; and The electronic component has an active surface and an inactive surface opposite to each other, and a plurality of first solders are disposed on the active surface, and a plurality of second solders are disposed on the plurality of electrical connection pads of the carrier, so that the electronic component is connected to the plurality of second solders of the carrier by the plurality of first solders; Among them, the thickness of the insulating protection layer of the carrier is H, which meets the following conditions: (a+b)*0.4+c≦H≦(a+b)*0.6+c, the thickness of the first solder is a, the thickness of the second solder is b, and the thickness of the electrical connection pad is c.

2. The flip chip package structure according to claim 1, wherein: The active surface is provided with a plurality of conductive bumps, and the plurality of first solders are arranged on the plurality of conductive bumps.

3. The flip chip package structure according to claim 1, wherein: The main body is provided with a circuit layer.

4. The flip chip package structure according to claim 3, characterized in that: The plurality of electrical connection pads are electrically connected to the circuit layer.

5. The flip chip package structure according to claim 1, wherein: The carrier is a substrate, a circuit structure or an intermediate board.

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