Power-on reset circuit based on negative pressure system
Through the power-on reset circuit based on the negative voltage system, the NMOS capacitor and the transient reverse circuit are used to accurately control the issuance time of the power-on reset signal, solving the problem of inaccurate thresholds of the traditional power-on reset circuit and achieving high-precision chip reset.
Patent Information
- Application Number
- CN202422252786.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-13
- Publication Date
- 2025-07-01
- Estimated Expiration
- 2034-09-13
AI Technical Summary
Traditionally, the threshold of the electrical reset circuit is difficult to accurately control and cannot meet the chip's high-precision reset needs when powering on and off, especially when process and temperature changes are large.
A power-on reset circuit based on a negative voltage system is designed. Through the NMOS capacitor and a transient reverse circuit, combined with the current control circuit, the issuance time of the power-on reset signal is accurately controlled, and the charging time and discharge process of the NMOS capacitor are used to achieve high-precision reset signal output.
It realizes accurate reset signal output when powering on and off power, reduces the area of the power-on reset circuit, and can meet the power-on reset time requirements of different chips.
Smart Images
Figure CN223053008U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of chip power-on reset, and particularly relates to a power-on reset circuit based on a negative pressure system. Background Art
[0002] A power-on reset circuit (POR) is used to generate a reset signal when the chip is powered on and off. The generated reset signal is used to turn on and reset digital and analog modules, ensuring the safe startup and operation of the chip.
[0003] The principle of the traditional power-on reset circuit is that when the power supply is powered up to a certain threshold, the power-on reset circuit will output a reset signal. However, the threshold value for flipping is greatly affected by chip process and temperature changes, and it is difficult to directly use it as a high-precision reset signal.
[0004] A common solution is to delay the initial POR signal until the Vdd supply voltage is powered up through clock counting, but this is difficult to meet the requirements of chips with a wide power-on time range and strict initialization time requirements. Summary of the Utility Model
[0005] In view of this, the problem to be solved by the utility model is to provide a power-on reset circuit based on a negative pressure system, which can accurately adjust the power-on reset time and meet the power-on reset requirements of the chip.
[0006] To solve the above technical problems, the technical solution adopted by the utility model is:
[0007] A power-on reset circuit based on a negative pressure system includes a port VDD for providing negative pressure and a port VSS of 0V. A transient reverse circuit connected to the reset port POR is connected in series between the port VDD and the port VSS;
[0008] A resistor R1 is connected in series between the port VSS and the D pole of the PMOS transistor M1. A resistor R2 is connected in series between the G pole of the PMOS transistor M1 and the port VDD. A port A is provided at the S pole of the PMOS transistor M1. The port A and the port VSS are directly connected in series with the NMOS capacitor M9;
[0009] A current control circuit is connected in series between the port A and the port VDD to control the charging time of the NMOS capacitor M9.
[0010] Further, the current control circuit includes PMOS transistors M2, M3, and M8. The G pole and D pole of the PMOS transistor M2 and the G pole of the PMOS transistor M3 are all connected to the port A. The S pole of the MOS transistor M2 is connected to the D pole of the PMOS transistor M3. The S pole of the PMOS transistor M3 is connected to the port VDD;
[0011] The port VDD is connected to the S pole of the PMOS transistor M8. The D pole and the G pole of the PMOS transistor M8 are short - circuited. A resistor R3 is connected in series between the D pole of the PMOS transistor M8 and the port A.
[0012] Further, the transient reverse connection circuit includes an NMOS transistor M4 and a PMOS transistor M5. The G poles of the NMOS transistor M4 and the PMOS transistor M5 are both connected to the port A. The S pole of the NMOS transistor M4 is connected to the port VSS. The S pole of the PMOS transistor M5 is connected to the port VDD. The D poles of the NMOS transistor M4 and the PMOS transistor M5 are both connected to the reset port POR.
[0013] Further, the transient reverse connection circuit includes an NMOS transistor M4, a PMOS transistor M5, an NMOS transistor M6 and a PMOS transistor M7. The G poles of the NMOS transistor M4 and the PMOS transistor M5 are both connected to the port A. The S pole of the NMOS transistor M4 is connected to the port VSS. The S pole of the PMOS transistor M5 is connected to the port VDD. The D poles of the NMOS transistor M4 and the PMOS transistor M5 are both connected to the G poles of the NMOS transistor M6 and the PMOS transistor M7;
[0014] The S pole of the NMOS transistor M6 is connected to the port VSS. The S pole of the PMOS transistor M7 is connected to the port VDD. The D poles of the NMOS transistor M6 and the PMOS transistor M7 are both connected to the reset port POR.
[0015] The advantages and positive effects of the present utility model are:
[0016] By setting the NMOS capacitor M9 to be connected to the transient reverse connection circuit, when the NMOS capacitor M9 is full or charged to a preset voltage, the transient reverse connection circuit can be turned on, and a high - voltage pulse signal is output to enable the chip to achieve power - on reset. Moreover, the NMOS capacitor M9 replaces the conventional capacitor, which can greatly reduce the area of the power - on reset circuit.
[0017] By setting the current control circuit composed of the PMOS transistor M2, the PMOS transistor M3, the PMOS transistor M8 and the resistor R3, by setting the size of the resistor R3 and the voltage difference between the branches where the PMOS transistor M2 and the PMOS transistor M3 are located, the magnitude of the current flowing between the port VSS and the port VDD is controlled, and further the charging time of the NMOS capacitor M9 is controlled, so as to accurately control the emission time of the power - on reset signal after the power supply is turned on to meet the power - on reset time requirement of the chip. Description of the Drawings
[0018] The drawings are used to provide a further understanding of the present utility model, and constitute a part of the specification. Together with the embodiments of the present utility model, they are used to explain the present utility model, and do not constitute a limitation to the present utility model. In the drawings:
[0019] Figure 1 This is the overall circuit diagram of a power-on reset circuit based on a negative pressure system of the present utility model. Specific embodiments
[0020] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments. Based on the embodiments in the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.
[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present utility model belongs. The terms used in the specification of the present utility model herein are only for the purpose of describing specific embodiments, and are not intended to limit the present utility model. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.
[0022] The present utility model provides a power-on reset circuit based on a negative pressure system, as Figure 1 shown. This reset circuit operates under a negative pressure circuit and includes a port VSS, a port VDD, and a reset port POR. The voltage of the port VSS is 0V, the voltage of the port VDD is negative, and the reset port POR is connected to the reset pin of the chip to cause the chip to perform power-on and power-off reset actions.
[0023] A resistor R1 is connected in series between the D pole of the PMOS transistor M1 and the port VSS. A resistor R2 is connected in series between the G pole of the PMOS transistor M1 and the port VDD. A port A is provided at the S pole of the PMOS transistor M1. An NMOS capacitor M9 is connected in series between the port A and the port VSS. A current control circuit is connected in series between the port A and the port VDD.
[0024] After the power is turned on, the voltage value of the port VDD drops to a preset negative value. The pressure difference between the port VDD and the port VSS causes the PMOS transistor M1 and the current control circuit to conduct, and the NMOS capacitor M9 starts to charge. During the charging process of the NMOS capacitor M9, the voltage value of the port A gradually decreases (the voltage is negative and gradually moves away from 0V). When the NMOS capacitor M9 is fully charged or charged to a preset voltage, the voltage at the port A causes the current control circuit to disconnect.
[0025] A transient reverse circuit connected in series between port VDD and port VSS and connected to the reset port POR. The transient reverse circuit includes NMOS transistor M4 and PMOS transistor M5. The gates of NMOS transistor M4 and PMOS transistor M5 are both connected to port A. The source of NMOS transistor M4 is connected to port VSS, the source of PMOS transistor M5 is connected to port VDD, and the drains of NMOS transistor M4 and PMOS transistor M5 are both connected to the reset port POR.
[0026] When the current control circuit is disconnected, since current cannot flow between port VDD and port VSS, the NMOS capacitor M9 discharges to turn on NMOS transistor M4. Since port VSS is 0V, current flows from the drain of NMOS transistor M4 to the source. Therefore, when NMOS transistor M4 is turned on, a high voltage greater than 0V is generated at the reset port POR. The voltages of the reset port POR and port A immediately turn on PMOS transistor M5, and the voltage of the reset port POR is pulled down to a negative value.
[0027] Due to the voltage difference between port VDD and port VSS, PMOS transistor M1 is turned on and PMOS transistor M5 remains turned on, forming a current loop, and the voltage of the reset port POR remains pulled down. And because PMOS transistor M1 and PMOS transistor M5 are always turned on, the NMOS capacitor M9 is always in a full state, and the current control circuit remains disconnected.
[0028] When the above circuit is powered on, it can make the reset port POR output a transient high-voltage pulse to output the power-on reset signal required by the chip.
[0029] When the power supply stops supplying power, the voltage of port VDD returns to 0V, causing PMOS transistor M5 and PMOS transistor M1 to disconnect. At this time, the NMOS capacitor M9 discharges to turn on NMOS transistor M4. Since port VSS is 0V, the voltage of the drain of NMOS transistor M4 is pulled up to greater than 0V, and the reset port POR outputs a transient high voltage again to output the power-down reset signal required by the chip.
[0030] The current control circuit includes PMOS transistor M2, PMOS transistor M3, and PMOS transistor M8. The gate and drain of PMOS transistor M2 and the gate of PMOS transistor M3 are all connected to port A. The source of MOS transistor M2 is connected to the drain of PMOS transistor M3, and the source of PMOS transistor M3 is connected to port VDD; a resistor R3 is connected in series between the drain of PMOS transistor M8 and port A. The drain and gate of PMOS transistor M8 are short-circuited, and the source of PMOS transistor M8 is connected to port VDD.
[0031] For the branch where PMOS transistor M2 and PMOS transistor M3 are located, the voltage difference between port A and port VDD is V GS (M2)+V GS(M3), the branch of PMOS transistor M8 and resistor R3, the voltage difference between its port A and port VDD is V GS (M8) + V(R3). According to Thevenin's equivalent, the current I generated by them can be obtained as I = ((V GS (M2) + V GS (M3)) - V GS (M8)) / R3. By changing the size of resistor R3 or the voltage of the branch where PMOS transistors M2 and M3 are located (adjusting the size of V GS on this branch or the number of PMOS transistors), the current flowing between port VDD and port VSS can be adjusted, thereby controlling the charging duration of NMOS capacitor M9 and controlling the emission time of the power-on reset signal after the power is turned on.
[0032] It is also possible to adjust the size of NMOS capacitor M9 to control its charging duration and precisely control the emission time of the power-on reset signal after the power is turned on.
[0033] To increase the driving ability of the transient reverse circuit, the transient reverse circuit includes NMOS transistor M4, PMOS transistor M5, NMOS transistor M6, and PMOS transistor M7. The G poles of NMOS transistor M4 and PMOS transistor M5 are both connected to port A. The S pole of NMOS transistor M4 is connected to port VSS, and the S pole of PMOS transistor M5 is connected to port VDD. The D poles of NMOS transistor M4 and PMOS transistor M5 are both connected to the G poles of NMOS transistor M6 and PMOS transistor M7; the S pole of NMOS transistor M6 is connected to port VSS, the S pole of PMOS transistor M7 is connected to port VDD, and the D poles of NMOS transistor M6 and PMOS transistor M7 are both connected to the reset port POR.
[0034] The above circuit structure forms a two-stage transient reverse circuit. Set the D pole of NMOS transistor M4 as port B. The circuit operation process is as follows: Power on - M4 conducts and pulls up the voltage of port B (greater than 0v) - M5 conducts and pulls down the voltage of port B9 (less than 0v) - M6 conducts and pulls up the voltage of the reset port POR (greater than 0v) - M7 conducts and pulls down the voltage of the reset port POR (less than 0v).
[0035] During the power-down process: Power down (gradually becomes 0v) - M1, M5, and M7 are disconnected simultaneously - M4 conducts and pulls up the voltage of port B (greater than 0v) - M5 conducts and pulls down the voltage of port B9 (port VDD has not dropped to 0v yet) - M6 conducts and pulls up the voltage of the reset port POR (greater than 0v).
[0036] To enable the two-stage transient reverse circuit to achieve power-down reset, when the power is down, the time period required for the voltage of port VDD to return to 0v is longer than the discharge time of NMOS capacitor M9, ensuring that PMOS transistor M5 can conduct when the power is down.
[0037] The embodiments of the present utility model have been described in detail above. However, the above content is only the preferred embodiment of the present utility model and should not be considered as limiting the scope of implementation of the present utility model. Any equivalent changes and improvements made within the scope of the present utility model should still fall within the scope covered by this patent.
Claims
1. A power-on reset circuit based on a negative pressure system, characterized in that: It includes a port VDD for providing negative voltage and a port VSS of 0V, wherein a transient reverse circuit connected to a reset port POR is connected in series between the port VDD and the port VSS; A resistor R1 is connected in series between the port VSS and the D pole of the PMOS tube M1, a resistor R2 is connected in series between the G pole of the PMOS tube M1 and the port VDD, a port A is provided at the S pole of the PMOS tube M1, and the port A and the port VSS are directly connected in series with an NMOS capacitor M9; A current control circuit is connected in series between the port A and the port VDD to control the charging time of the NMOS capacitor M9.
2. A power-on reset circuit based on a negative pressure system according to claim 1, characterized in that: The current control circuit comprises a PMOS tube M2, a PMOS tube M3 and a PMOS tube M8, wherein the G pole and the D pole of the PMOS tube M2 and the G pole of the PMOS tube M3 are connected to the port A, the S pole of the MOS tube M2 is connected to the D pole of the PMOS tube M3, and the S pole of the PMOS tube M3 is connected to the port VDD; The port VDD is connected to the S pole of the PMOS tube M8 , the D pole and the G pole of the PMOS tube M8 are short-circuited , and a resistor R3 is connected in series between the D pole of the PMOS tube M8 and the port A .
3. The power-on reset circuit based on a negative pressure system according to claim 1, characterized in that: The transient reverse circuit includes an NMOS tube M4 and a PMOS tube M5, wherein the G poles of the NMOS tube M4 and the PMOS tube M5 are both connected to the port A, the S pole of the NMOS tube M4 is connected to the port VSS, the S pole of the PMOS tube M5 is connected to the port VDD, and the D poles of the NMOS tube M4 and the PMOS tube M5 are both connected to the reset port POR.
4. The power-on reset circuit based on a negative pressure system according to claim 1, characterized in that: The transient reverse circuit comprises an NMOS tube M4, a PMOS tube M5, an NMOS tube M6 and a PMOS tube M7, the G poles of the NMOS tube M4 and the PMOS tube M5 are both connected to the port A, the S pole of the NMOS tube M4 is connected to the port VSS, the S pole of the PMOS tube M5 is connected to the port VDD, and the D poles of the NMOS tube M4 and the PMOS tube M5 are both connected to the G poles of the NMOS tube M6 and the PMOS tube M7; The S pole of the NMOS tube M6 is connected to the port VSS, the S pole of the PMOS tube M7 is connected to the port VDD, and the D poles of the NMOS tube M6 and the PMOS tube M7 are both connected to the reset port POR.