Circuit for inhibiting squeal of capacitor and improved printed circuit board thereof

Abstract

The utility model provides a circuit for suppressing capacitor squeal and an improved printed circuit board thereof, and the improved printed circuit board comprises a circuit substrate which is provided with a first surface and a second surface opposite to the first surface; the one or more capacitor mounting positions are formed on the first surface of the circuit substrate, each capacitor mounting position comprises a first capacitor bonding pad and a second capacitor bonding pad which are spaced from each other, and the capacitor mounting positions are used for mounting capacitors; the one or more first via holes are formed in the periphery of the first capacitor bonding pad and penetrate through the circuit substrate; the second via holes are formed in the periphery of the second capacitor bonding pad and penetrate through the circuit substrate. Compared with the prior art, the chip capacitor provided by the utility model adopts a PCB wiring mode of adding the via holes at the capacitor bonding pads at the two ends of the chip capacitor and removing the copper sheet at the capacitor non-GND end of the chip capacitor, so that the surface of the PCB does not have integrity when the chip capacitor generates mechanical vibration, the vibration amplitude can be reduced, and the effect of reducing capacitor howling is achieved.

Description

Technical Field

[0001] The utility model relates to the technical field of circuit design, and particularly relates to a circuit for suppressing capacitor crosstalk and an improved printed circuit board thereof.

Background Art

[0002] In an automotive electrical system, there may be a situation where an alternating voltage is superimposed on the input power supply side. A ripple voltage of a certain frequency will appear in the entire operating system along with the automotive input power supply, such as Figure 1 shown, which is a waveform diagram of the input power supply with a superimposed alternating voltage in an embodiment. When the chip capacitors in the circuit are subjected to an alternating voltage, they will exhibit a special physical phenomenon. They will be deformed by an external force in a certain direction. When the frequency of the alternating voltage reaches a certain value, mechanical vibration will be generated, thus making a sound, that is, the capacitor crosstalk phenomenon. Please refer to Figure 2 shown, which is a circuit schematic diagram of a filter circuit with capacitors in an embodiment. Due to the existence of filter capacitors C1, C2, C3, C4, C5, C6, and C7, when there is a situation where an alternating voltage is superimposed on the input power supply VIN, a ripple voltage of a certain frequency will appear in the entire operating system along with the input power supply VIN, and the chip capacitors will generate mechanical vibration, thus making a sound.

[0003] During the use of the product, the occurrence of capacitor crosstalk will affect the user experience during use. Especially in the automotive field, the occurrence of abnormal noise during driving by the driver will affect the driver's attention and may pose a risk of causing traffic accidents.

[0004] Currently, there are the following solutions for capacitor crosstalk: ①. Support the capacitor by means of a bracket, and use the elastic effect of the metal terminal to relieve stress, thereby reducing the degree of capacitor crosstalk. Specifically, as Figure 3 shown, which is a structural schematic diagram of an anti-crosstalk capacitor in the prior art. ②. Place the same-specification chip capacitors symmetrically at the same positions on the front and back sides of the PCB board, and reduce the crosstalk degree by the vibration cancellation of the two capacitors. Specifically, as Figure 4 shown, which is a structural schematic diagram of another anti-crosstalk capacitor in the prior art.

[0005] Among them, the disadvantage of the prior art solution ① is that using a bracket capacitor has a high cost and a large package size. The disadvantage of the prior art solution ② is that the degree of reducing capacitor crosstalk is limited, and it is related to the soldering process, chip symmetry degree, etc., and there may be a situation where the capacitor crosstalk cannot be effectively reduced.

[0006] Therefore, it is necessary to propose a new technical solution to solve the above problems.

Content of the Utility Model

[0007] One of the objectives of the present utility model is to provide a circuit for suppressing capacitor crosstalk and an improved printed circuit board thereof, which can effectively reduce capacitor crosstalk by improving the wiring method of the printed circuit board.

[0008] According to one aspect of the present utility model, an improved printed circuit board is provided, which includes: a circuit substrate having a first surface and a second surface opposite to the first surface; one or more capacitor mounting positions formed on the first surface of the circuit substrate, the capacitor mounting positions including a first capacitor pad and a second capacitor pad spaced apart from each other, and the capacitor mounting positions being used for mounting capacitors; one or more first vias formed around the first capacitor pad and passing through the circuit substrate; and one or more second vias formed around the second capacitor pad and passing through the circuit substrate.

[0009] Furthermore, the first capacitor pad is a ground pad, and the second capacitor pad is a non-ground pad; there are multiple first vias, and the multiple first vias are arranged around the first capacitor pad with no gap between adjacent first vias, there are multiple second vias, and the multiple second vias are arranged around the second capacitor pad with a gap between adjacent second vias.

[0010] Furthermore, the diameters of the first vias and the second vias are greater than or equal to 0.5 millimeters.

[0011] Furthermore, the improved printed circuit board further includes a metal layer covering the first surface of the circuit substrate and surrounding the capacitor mounting positions; a part of the metal layer around the second capacitor pad is removed.

[0012] Furthermore, the metal layer within a range with a radius of R centered on the second capacitor pad is removed.

[0013] Furthermore, the R is greater than or equal to 1.5 millimeters.

[0014] Furthermore, the improved printed circuit board further includes an inductor mounting position formed on the first surface of the circuit substrate; the inductor mounting position includes a first inductor pad and a second inductor pad spaced apart from each other; and the inductor mounting position is used for mounting an inductor.

[0015] Furthermore, multiple capacitor mounting positions are arranged side by side on one side of the inductor mounting position, and multiple other capacitor mounting positions are arranged side by side on the other side of the inductor mounting position; the first capacitor pads of adjacent capacitor mounting positions are adjacent, and the second capacitor pads of adjacent capacitor mounting positions are adjacent.

[0016] According to another aspect of the present utility model, the present utility model provides a circuit for suppressing capacitor whistling, which includes: an improved printed circuit board as described in the present utility model; and a capacitor mounted on the capacitor mounting position.

[0017] Further, the capacitor is a chip capacitor.

[0018] Compared with the prior art, the present utility model adopts a PCB wiring method of adding vias at the capacitor pads at both ends of the chip capacitor and removing copper foil at the non-GND end of the capacitor, so that the PCB surface is not complete when the chip capacitor generates mechanical vibration, thereby reducing the vibration amplitude and achieving the effect of reducing capacitor whistling.

Description of the Drawings

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings. Among them:

[0020] Figure 1 It is a waveform diagram of the input power supply with superimposed AC voltage in one embodiment;

[0021] Figure 2 It is a circuit schematic diagram of a functional circuit with a capacitor in one embodiment;

[0022] Figure 3 It is a structural schematic diagram of an anti-whistling capacitor in the prior art;

[0023] Figure 4 It is a structural schematic diagram of another anti-whistling capacitor in the prior art;

[0024] Figure 5 It is a wiring schematic diagram of a printed circuit board with a filter circuit installed in one embodiment of the prior art;

[0025] Figure 6 It is a wiring schematic diagram of an improved printed circuit board with a filter circuit installed in one embodiment of the present utility model;

[0026] Figure 7 For a printed circuit board with a filter circuit installed as shown in Figure 5 in one embodiment, it is a schematic diagram of noise test data when there is a superimposed AC voltage on the input power supply side;

[0027] Figure 8 For a printed circuit board with a filter circuit installed as shown in Figure 6Schematic diagram of noise test data when an improved printed circuit board equipped with a filter circuit has an overlapping AC voltage on the input power supply side.

Detailed implementation manners

[0028] To make the above-mentioned objects, features and advantages of the present utility model more obvious and understandable, the present utility model will be further described in detail below with reference to the accompanying drawings and specific implementation manners.

[0029] As used herein, the term "one embodiment" or "embodiment" refers to a specific feature, structure or characteristic that may be included in at least one implementation manner of the present utility model. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it an individual or alternative embodiment that is mutually exclusive with other embodiments. Unless otherwise specified, the terms indicating electrical connection such as "coupled", "connected", "linked", "joined" in this article all mean directly or indirectly connected. For example, when A is connected to B, it includes both A and B being directly electrically connected, and also A being connected to B through electrical components or circuits.

[0030] In the description of the present utility model, it should be understood that the orientation or positional relationships indicated by the terms "upper", "lower", "front", "rear", "front", "back", "left", "right", "vertical", "perpendicular", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the accompanying drawings. These are only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present utility model.

[0031] Please refer to Figure 5 As shown, it is a schematic diagram of the traces of a printed circuit board (PCB, Printed Circuit Board) equipped with a filter circuit in an embodiment of the prior art. Please refer to Figure 6 As shown, it is a schematic diagram of the traces of an improved printed circuit board equipped with a filter circuit in an embodiment of the present utility model.

[0032] Figure 5 and Figure 6The filter circuits shown all include capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C7, and inductor L1. Among them, one end of the inductor L1 is connected to the input power supply terminal VIN, and the other end is connected to the output power supply terminal VOUT; one end of the capacitor C1 is connected to the input power supply terminal VIN (or one end of the inductor L1), and the other end is grounded; one end of the capacitor C2 is connected to the input power supply terminal VIN (or one end of the inductor L1), and the other end is grounded; one end of the capacitor C3 is connected to the input power supply terminal VIN (or one end of the inductor L1), and the other end is grounded; one end of the capacitor C4 is connected to the output power supply terminal VOUT (or the other end of the inductor L1), and the other end is grounded; one end of the capacitor C5 is connected to the output power supply terminal VOUT (or the other end of the inductor L1), and the other end is grounded; one end of the capacitor C6 is connected to the output power supply terminal VOUT (or the other end of the inductor L1), and the other end is grounded; one end of the capacitor C7 is connected to the output power supply terminal VOUT (or the other end of the inductor L1), and the other end is grounded. Among them, the capacitors C1, C2, C3, C4, C5, C6, and C7 can be chip capacitors.

[0033] Figure 5 and Figure 6 The printed circuit boards shown all include a circuit substrate 510 and capacitor mounting positions. Among them, the circuit substrate 510 has a first surface (not labeled) and a second surface (not labeled) opposite to the first surface.

[0034] In Figure 5 and Figure 6In the specific embodiment shown, seven capacitor mounting positions are formed on the first surface of the circuit board 510. Among them, the first capacitor mounting position includes a first capacitor pad A11 and a second capacitor pad A12 spaced apart from each other. One end of the capacitor C1 is soldered to the first capacitor pad A11, and the other end is soldered to the second capacitor pad A12. That is to say, the capacitor C1 is mounted on the first capacitor mounting position; the second capacitor mounting position includes a first capacitor pad A21 and a second capacitor pad A22 spaced apart from each other. One end of the capacitor C2 is soldered to the first capacitor pad A21, and the other end is soldered to the second capacitor pad A22. That is to say, the capacitor C2 is mounted on the second capacitor mounting position; the third capacitor mounting position includes a first capacitor pad A31 and a second capacitor pad A32 spaced apart from each other. One end of the capacitor C3 is soldered to the first capacitor pad A31, and the other end is soldered to the second capacitor pad A32. That is to say, the capacitor C3 is mounted on the third capacitor mounting position; the fourth capacitor mounting position includes a first capacitor pad A41 and a second capacitor pad A42 spaced apart from each other. One end of the capacitor C4 is soldered to the first capacitor pad A41, and the other end is soldered to the second capacitor pad A42. That is to say, the capacitor C4 is mounted on the fourth capacitor mounting position; the fifth capacitor mounting position includes a first capacitor pad A51 and a second capacitor pad A52 spaced apart from each other. One end of the capacitor C5 is soldered to the first capacitor pad A51, and the other end is soldered to the second capacitor pad A52. That is to say, the capacitor C5 is mounted on the fifth capacitor mounting position; the sixth capacitor mounting position includes a first capacitor pad A61 and a second capacitor pad A62 spaced apart from each other. One end of the capacitor C6 is soldered to the first capacitor pad A61, and the other end is soldered to the second capacitor pad A62. That is to say, the capacitor C6 is mounted on the sixth capacitor mounting position; the seventh capacitor mounting position includes a first capacitor pad A61 and a second capacitor pad A62 spaced apart from each other. One end of the capacitor C6 is soldered to the first capacitor pad A61, and the other end is soldered to the second capacitor pad A62. That is to say, the capacitor C6 is mounted on the sixth capacitor mounting position; the seventh capacitor mounting position includes a first capacitor pad A71 and a second capacitor pad A72 spaced apart from each other. One end of the capacitor C7 is soldered to the first capacitor pad A71, and the other end is soldered to the second capacitor pad A72. That is to say, the capacitor C7 is mounted on the seventh capacitor mounting position.

[0035] It should be particularly noted that in other embodiments, the capacitor mounting positions formed on the first surface of the circuit board 510 can be one or more. Among them, each capacitor mounting position includes a first capacitor pad and a second capacitor pad spaced apart from each other, and the capacitor mounting position is used to mount the corresponding capacitor.

[0036] Compared with Figure 5 Figure 6The improved printed circuit board shown further includes one or a first via 520 and one or more second vias 530.

[0037] Among them, one or more first vias 520 are formed around the first capacitor pads A11, A21, A31, A41, A51, A61, A71 and penetrate through the circuit substrate 510. Figure 6 In the specific embodiment shown, the first capacitor pads A11, A21, A31, A41, A51, A61, A71 are ground pads; there are multiple first vias 520, and the multiple first vias 520 are arranged around the first capacitor pads A11, A21, A31, A41, A51, A61, A71, and there is no gap between adjacent first vias 520. The specific number of drilled holes is related to the capacitor package. Taking the 0805 package capacitor as an example, three first vias 520 are drilled at the end parallel to the first capacitor pads, and two first vias 520 are drilled at the end perpendicular to the first capacitor pads.

[0038] Among them, one or more second vias 530 are formed around the second capacitor pads A12, A22, A32, A42, A52, A62, A72 and penetrate through the circuit substrate 510. Figure 6 In the specific embodiment shown, the second capacitor pads A12, A22, A32, A42, A52, A62, A72 are non-ground pads; there are multiple second vias 530, and the multiple second vias 530 are arranged around the second capacitor pads A12, A22, A32, A42, A52, A62, A72, and there is a gap between adjacent second vias 530. The specific number of drilled holes is related to the capacitor package. Taking the 0805 package capacitor as an example, two second vias 530 are drilled at the end parallel to the second capacitor pads, and no second via 530 is drilled at the end perpendicular to the second capacitor pads.

[0039] In a specific embodiment of the present utility model, the aperture of the first via 520 and the second via 530 is greater than or equal to 0.5 millimeters.

[0040] Figure 5 and Figure 6 The printed circuit board shown also includes a metal layer (for example, a copper layer) 540, and the metal layer 540 covers the first surface of the circuit substrate 510 and surrounds each capacitor mounting position. In PCB design, in order to improve the current conduction ability, reduce the ground impedance, and play a role in protecting the circuit, etc., copper cladding operations are performed on the PCB.

[0041] Compared with Figure 5 In Figure 6In the improved printed circuit board shown, a part of the metal layer 540 around the second capacitor pads A12, A22, A32, A42, A52, A62, A72 is removed. Specifically, it is related to the capacitor package. Taking the 0805 package as an example, with the centers of the second capacitor pads A12, A22, A32, A42, A52, A62, A72 as the origin, the metal layer 540 within a range with a radius of R needs to be removed, where R is greater than or equal to 1.5 millimeters.

[0042] Figure 5 and Figure 6 The printed circuit board shown also includes an inductor mounting position, which is formed on the first surface of the circuit substrate 510. The inductor mounting position includes a first inductor pad B11 and a second inductor pad B12 that are spaced apart from each other. One end of the inductor L1 is soldered to the first inductor pad B11, and the other end is soldered to the second inductor pad B12. In other words, the inductor L1 is mounted on the first inductor mounting position, or the inductor mounting position is used to mount the corresponding inductor.

[0043] In Figure 5 and Figure 6In the specific embodiment shown, the capacitance mounting positions of capacitors C1, C2, and C3 are arranged side by side on one side of the inductance mounting position of inductor L1; the capacitance mounting positions of capacitors C4, C5, C6, and C7 are arranged side by side on the other side of the inductance mounting position of inductor L1; the first capacitance pads A11, A21, and A31 of the capacitance mounting positions of adjacent capacitors C1, C2, and C3 are adjacent; the second capacitance pads A12, A22, and A32 of the capacitance mounting positions of adjacent capacitors C1, C2, and C3 are adjacent; the first capacitance pads A41, A51, A61, and A71 of the capacitance mounting positions of adjacent capacitors C4, C5, C6, and C7 are adjacent; the second capacitance pads A42, A52, A62, and A72 of the capacitance mounting positions of adjacent capacitors C4, C5, C6, and C7 are adjacent; the first capacitance pads A11, A21, and A31 of the capacitance mounting positions of capacitors C1, C2, and C3 are grounded, and the second capacitance pads A12, A22, and A32 of the capacitance mounting positions of capacitors C1, C2, and C3 are electrically connected to the second inductance pad B12 of the inductance mounting position of inductor L1; the first capacitance pads A41, A51, A61, and A71 of the capacitance mounting positions of capacitors C4, C5, C6, and C7 are grounded, and the second capacitance pads A42, A52, A62, and A72 of the capacitance mounting positions of capacitors C4, C5, C6, and C7 are connected to the first inductance pad B11 of the inductance mounting position of inductor L1. That is to say, multiple capacitance mounting positions are arranged side by side on one side of the inductance mounting position, and multiple other capacitance mounting positions are arranged side by side on the other side of the inductance mounting position; the first capacitance pads of adjacent capacitance mounting positions are adjacent, and the second capacitance pads of adjacent capacitance mounting positions are adjacent.

[0044] The following is a specific introduction Figure 6 The principle of suppressing capacitor crosstalk by the improved printed circuit board routing method shown.

[0045] When vias 520 and 530 are not added at the capacitance pads (for example, the first capacitance pads A11, A21, A31, A41, A51, A61, A71 and the second capacitance pads A12, A22, A32, A42, A52, A62, A72), since the PCB board at both ends of the capacitance pads is complete. When the capacitor generates mechanical vibration due to the superimposed AC voltage, the vibration plane is complete, so the vibration amplitude will be relatively large, the vibration range will be relatively far, and the vibration process is complete.

[0046] When vias 520 and 530 are added at the capacitor pads (e.g., the first capacitor pads A11, A21, A31, A41, A51, A61, A71 and the second capacitor pads A12, A22, A32, A42, A52, A62, A72), and the copper is removed from the non-GND end of the capacitor (i.e., the second capacitor pads A12, A22, A32, A42, A52, A62, A72), since the integrity of the PCB at both ends of the capacitor pad is damaged, the vibration amplitude can be effectively reduced, and the vibration range will also be reduced.

[0047] The above solution is described like the drumhead of a drum. When the drumhead is intact, the amplitude formed by the vibration of the drumhead is relatively large, and the vibration range is also relatively far. After several holes are drilled in the drumhead, the amplitude formed by the vibration of the drumhead is relatively reduced, and the vibration range will also be reduced.

[0048] Please refer to Figure 7 as shown, which is a schematic diagram of the noise test data when there is an overlapping AC voltage on the input power supply side of a printed circuit board installed with a filter circuit as shown in Figure 5 an embodiment. Please refer to Figure 8 as shown, which is a schematic diagram of the noise test data when there is an overlapping AC voltage on the input power supply side of an improved printed circuit board installed with a filter circuit as shown in Figure 6 an embodiment. Comparing the test data of Figure 7 and Figure 8 it can be concluded that the improved printed circuit board wiring scheme as shown in Figure 6 can reduce the noise by about 3.5 dB and can reduce the degree of capacitor squeal.

[0049] According to another aspect of the present invention, the present invention provides a circuit for suppressing capacitor squeal, which further includes: an improved printed circuit board as described in the present invention, and a capacitor installed on the capacitor mounting position of the improved printed circuit board. In a specific embodiment, the capacitor installed on the capacitor mounting position of the improved printed circuit board is a chip capacitor.

[0050] In summary, in the circuit for suppressing capacitor crosstalk and the improved printed circuit board provided by the present utility model, vias 520 and 530 are added at capacitor pads (for example, the first capacitor pads A11, A21, A31, A41, A51, A61, A71 and the second capacitor pads A12, A22, A32, A42, A52, A62, A72), and the PCB trace routing method of removing copper on the non-GND end of the capacitor (i.e., the second capacitor pads A12, A22, A32, A42, A52, A62, A72) is adopted, so that the PCB surface is not intact when the surface-mounted capacitor generates mechanical vibration. Therefore, no additional components are required, the circuit cost is not increased, the vibration amplitude can be reduced, and the degree of capacitor crosstalk can be effectively reduced.

[0051] It should be noted that any modification made by those skilled in the art to the specific implementation manners of the present utility model does not depart from the scope of the claims of the present utility model. Correspondingly, the scope of the claims of the present utility model is not limited solely to the foregoing specific implementation manners.

Claims

1. An improved printed circuit board, characterized in that: It includes: a circuit substrate having a first surface and a second surface opposite to the first surface; One or more capacitor mounting positions, which are formed on the first surface of the circuit substrate, the capacitor mounting positions include a first capacitor pad and a second capacitor pad spaced apart from each other, and the capacitor mounting positions are used to mount a capacitor; One or more first vias, which are formed around the first capacitor pad and pass through the circuit substrate; One or more second via holes are formed around the second capacitor pad and pass through the circuit substrate.

2. The improved printed circuit board according to claim 1, characterized in that: The first capacitor pad is a ground pad, and the second capacitor pad is a non-ground pad; There are a plurality of first via holes, and the plurality of first via holes are arranged around the first capacitor pad, and there is no gap between adjacent first via holes. There are a plurality of the second via holes, and the plurality of the second via holes are arranged around the second capacitor pad, and there are gaps between adjacent second via holes.

3. The improved printed circuit board according to claim 2, characterized in that: The diameters of the first via hole and the second via hole are greater than or equal to 0.5 mm.

4. The improved printed circuit board according to claim 1, characterized in that: It also includes a metal layer, The metal layer covers the first surface of the circuit substrate and surrounds the capacitor mounting position; A portion of the metal layer around the second capacitor pad is removed.

5. The improved printed circuit board according to claim 4, characterized in that: The metal layer within a radius R with the center of the second capacitor pad as the origin is removed.

6. The improved printed circuit board according to claim 5, characterized in that: R is greater than or equal to 1.5 mm.

7. The improved printed circuit board according to claim 1, characterized in that: It also includes the inductor mounting position, The inductor mounting position is formed on the first surface of the circuit substrate; The inductor mounting position includes a first inductor pad and a second inductor pad spaced apart from each other; The inductor mounting position is used for mounting an inductor.

8. The improved printed circuit board according to claim 7, characterized in that: A plurality of the capacitor mounting positions are arranged side by side on one side of the inductor mounting position, and another plurality of the capacitor mounting positions are arranged side by side on the other side of the inductor mounting position; The first capacitor pads of adjacent capacitor mounting positions are adjacent to each other, and the second capacitor pads of adjacent capacitor mounting positions are adjacent to each other.

9. A circuit for suppressing capacitor howling, characterized in that: It includes: An improved printed circuit board as claimed in any one of claims 1 to 8; A capacitor installed on the capacitor installation position.

10. The circuit for suppressing capacitor howling according to claim 9, characterized in that: The capacitor is a chip capacitor.

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