Multi-chip stacking packaging structure
By setting up a heat dissipation dam body and a heat dissipation tank between the chips, the heat dissipation medium flows to derive heat, which solves the problem of heat accumulation in multi-chip stacking, and achieves better heat dissipation effect and chip thermal reliability.
Patent Information
- Application Number
- CN202422095113.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-27
- Publication Date
- 2025-07-04
- Estimated Expiration
- 2034-08-27
AI Technical Summary
Multi-chip stacking leads to heat accumulation, difficulty in dissipating heat, and affects the thermal reliability of the chip.
A heat dissipation dam body is arranged between adjacent chips, and a heat dissipation groove is formed on the upper surface of the heat dissipation dam body to fill the heat dissipation medium, and the heat of the chip is derived through the flow of the heat dissipation medium to form a sealed heat dissipation channel to improve the heat dissipation effect.
Effective heat dissipation medium flows to lead to the chip heat, avoid heat accumulation, improve the heat dissipation effect of multi-chip stacking, and enhance the thermal reliability of chips.
Smart Images
Figure CN223066164U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of chips, in particular to a multi-chip stacked packaging structure. Background Art
[0002] With the slowdown of Moore's Law, in order to continue to improve chip performance, the industry has turned to 3D chip stacking interconnection technology. In this way, both the bandwidth between chips can be increased and the computing performance can be improved. However, due to the increase in the number of stacked chips, the size of the heat dissipation structure increases, and the heat of the internal chips is difficult to dissipate due to the stacking of multiple chips, resulting in heat accumulation and a large heat flux density per unit area. If effective means cannot be used for heat dissipation, it will inevitably lead to problems with the thermal reliability of the chips. How to dissipate heat from multi-chip stacking has become an urgent problem to be solved. Summary of the Utility Model
[0003] The purpose of the utility model is to provide a multi-chip stacked packaging structure to solve the problem of heat accumulation caused by multi-chip stacking.
[0004] To achieve the above purpose, the utility model provides the following technical solutions:
[0005] A multi-chip stacked packaging structure, comprising:
[0006] At least two chips stacked vertically;
[0007] A welding structure located between two adjacent chips for supporting the chips;
[0008] A heat dissipation dam body is arranged between two adjacent chips and at the surface edge of the chips. The heat dissipation dam body supports two adjacent chips. The upper surface of the heat dissipation dam body has heat dissipation grooves, and a first sealed heat dissipation channel is formed between the heat dissipation grooves of the heat dissipation dam body and the chips. The heat dissipation grooves are filled with a heat dissipation medium;
[0009] A glue filling layer is arranged in the area enclosed by two adjacent chips and the heat dissipation dam body, and the glue filling layer wraps the welding structure.
[0010] As an implementable manner, the head end of the heat dissipation groove has a liquid inlet, and the tail end of the heat dissipation groove has a liquid outlet.
[0011] As an implementable manner, the heat dissipation dam body is provided with a glue filling layer injection opening.
[0012] As an implementable manner, the welding structure includes a plurality of micro bumps, the micro bumps are arranged at intervals, and the micro bumps connect two adjacent chips and achieve electrical connection.
[0013] As an implementable manner, a buffer layer is provided on the lower surface of the chip, the buffer layer wraps the edge of the micro bump, and a first sealed heat dissipation channel is formed between the buffer layer and the heat dissipation groove of the heat dissipation dam body.
[0014] As an implementable manner, a heat dissipation adhesive layer and a heat dissipation cover located on the side wall of the heat dissipation adhesive layer are provided on the side surface of the at least two chips stacked up and down. The heat dissipation adhesive layer is provided with communication holes at the liquid inlet and outlet of the heat dissipation dam body. The heat dissipation cover has a second sealed heat dissipation channel, and one end of the second sealed heat dissipation channel is respectively connected to the communication holes of the heat dissipation adhesive layer, and the other end of the second sealed heat dissipation channel is provided with corresponding liquid outlet through holes and / or liquid inlet through holes at the top or bottom of the heat dissipation cover.
[0015] As an implementable manner, the size of the communication holes of the heat dissipation adhesive layer is larger than the size of the liquid inlet and / or liquid outlet.
[0016] As an implementable manner, the heat dissipation cover also covers the top surface of the topmost chip.
[0017] As an implementable manner, a transfer board is further included, and the chip at the bottommost is connected to the transfer board;
[0018] The transfer board is provided with a liquid inlet channel and a liquid outlet channel for the heat dissipation medium to pass through, and the liquid inlet channel and the liquid outlet channel are communicated with the liquid outlet through holes and the liquid inlet through holes of the heat dissipation cover.
[0019] As an implementable manner, a heat dissipation dam body is further provided between the bottom edge of the chip at the bottommost and the transfer board. The heat dissipation dam body supports the adjacent chips and the transfer board. The upper surface of the heat dissipation dam body has a heat dissipation groove. A first sealed heat dissipation channel is formed between the heat dissipation groove of the heat dissipation dam body and the chip. The head end of the heat dissipation groove has a liquid inlet, the tail end of the heat dissipation groove has a liquid outlet, and the heat dissipation medium is filled in the heat dissipation groove.
[0020] As an implementable manner, the corners of the heat dissipation groove are set to be arc-shaped.
[0021] As an implementable manner, the head end and the tail end of the heat dissipation groove are on the same side of the chip; or, the head end and the tail end of the heat dissipation groove are on both sides of the chip.
[0022] As an implementable manner, when the head end and the tail end of the heat dissipation groove are on both sides of the chip, an inclination angle is formed at the connection between the liquid inlet of the heat dissipation groove and the filling adhesive layer, which is inclined towards the filling adhesive layer.
[0023] Compared with the prior art, the beneficial effects of the present utility model are:
[0024] By arranging a heat dissipation dam body between two adjacent chips, the heat dissipation dam body can support the chips. In addition, a heat dissipation groove is formed on the upper surface of the heat dissipation dam body. The head end of the heat dissipation groove has a liquid inlet, and the tail end of the heat dissipation groove has a liquid outlet. The heat dissipation groove is used to fill a heat dissipation medium. The heat dissipation medium enters the heat dissipation groove from the liquid inlet and then flows out of the heat dissipation groove from the liquid outlet. The heat generated by the chips is absorbed by the heat dissipation medium, and the heat of a single chip is exported through the flow of the heat dissipation medium, improving the heat dissipation effect of multiple chips and thus avoiding heat accumulation caused by the stacking of multiple chips. Description of the Drawings
[0025] Figure 1 Schematic diagram of the first multi-chip stacking and packaging structure disclosed in the embodiment of the present invention;
[0026] Figure 2 is Figure 1 Schematic diagram of another perspective;
[0027] Figure 3 is Figure 2 Cross-sectional view taken along A-A in
[0028] Figure 4 is Figure 2 Cross-sectional view taken along B-B in
[0029] Figure 5 Cross-sectional view of the second multi-chip stacking and packaging structure disclosed in the embodiment of the present invention;
[0030] Figure 6 Cross-sectional view of the third multi-chip stacking and packaging structure disclosed in the embodiment of the present invention;
[0031] Figure 7 Cross-sectional view of the fourth multi-chip stacking and packaging structure disclosed in the embodiment of the present invention.
[0032] In the figure: 1. Chip; 2. Welding structure; 21. Micro bump; 3. Heat dissipation dam body; 31. Heat dissipation groove; 311. Liquid inlet; 312. Liquid outlet; 313. Corner; 32. Glue filling layer injection opening; 4. Glue filling layer; 5. Buffer layer; 6. Interconnection board; 7. Solder ball; 8. Heat dissipation glue layer; 81. Communication hole; 9. Heat dissipation cover; 91. Heat dissipation channel; 92. Through hole; 10. Liquid inlet channel; 11. Liquid outlet channel. Detailed Embodiments
[0033] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0034] In this text, terms such as "upper, lower, inner, outer" are established based on the positional relationships shown in the drawings. Depending on the different drawings, the corresponding positional relationships may also change accordingly. Therefore, they should not be understood as absolute limitations on the scope of protection. Moreover, relational terms such as "first" and "second" are only used to distinguish one component with the same name from another, and do not necessarily require or imply any such actual relationship or order between these components.
[0035] The multi-chip stacked packaging structure disclosed by the present utility model can be applicable to the production and manufacturing of chips for various articles: for example, terminal devices with display interfaces such as mobile phones, TVs, monitors, tablet computers, in-vehicle computers, etc., or intelligent display wearable devices such as smart watches and smart bracelets, or communication devices such as servers, memories, base stations, or smart cars, etc.
[0036] Embodiment 1
[0037] As Figures 1-3 shown, the multi-chip stacked packaging structure disclosed in this embodiment includes at least two chips 1 stacked up and down, a welding structure 2, a heat dissipation dam body 3, and a glue filling layer 4; the welding structure 2 is located between two chips 1 and is used for electrical connection between the chips; the heat dissipation dam body 3 is arranged between adjacent two chips 1 and is located at the surface edge of the chips, and the heat dissipation dam body 3 supports the adjacent two chips 1; the upper surface of the heat dissipation dam body 3 has heat dissipation grooves 31, and a first sealed heat dissipation channel is formed between the heat dissipation grooves 31 of the heat dissipation dam body 3 and the chips 1, and the heat dissipation grooves 31 are filled with a heat dissipation medium; the glue filling layer 4 is arranged in the area enclosed by adjacent upper and lower chips 1 and the heat dissipation dam body 3, and the glue filling layer 4 wraps the welding structure 2.
[0038] In an implementable manner, the heat dissipation dam body 3 is made of organic glue, and the organic glue is arranged to avoid the pads between the chips 1 to prevent interference with the pads.
[0039] Specifically, by arranging the heat dissipation dam body 3 between adjacent two chips 1, and the heat dissipation dam body 3 can support the chips 1; in addition, a part of the upper surface of the heat dissipation dam body 3 forms heat dissipation grooves 31, the head end of the heat dissipation grooves 31 has a liquid inlet 311, the tail end of the heat dissipation grooves 31 has a liquid outlet 312, the heat dissipation grooves 31 are filled with a heat dissipation medium, the heat dissipation medium enters the heat dissipation grooves 31 from the liquid inlet 311 and then flows out of the heat dissipation grooves 31 from the liquid outlet 312. The heat generated by the chips 1 is absorbed by the heat dissipation medium, and the heat of a single chip 1 is exported through the flow of the heat dissipation medium, improving the heat dissipation effect of multiple chips, thereby avoiding heat accumulation caused by multiple chips being stacked.
[0040] It can be understood that the head end and the tail end refer to the two ends of the heat dissipation groove 31. The head end and the tail end are relative concepts and are specifically selected according to the actual situation. When multiple chips 1 are stacked in the same way, the head ends and the tail ends of the heat dissipation grooves 31 of different chips are unified.
[0041] Furthermore, as Figure 4 shown, the heat dissipation dam body 3 is provided with a glue filling layer injection opening 32, and the glue filling layer injection opening 32 is used to form a glue filling layer 4 between two adjacent chips 1.
[0042] Furthermore, as Figure 3 shown, the welding structure 2 includes a plurality of microbumps 21. The microbumps 21 are arranged at intervals, and the microbumps 21 connect two adjacent chips 1 and realize the electrical connection between two adjacent chips 1.
[0043] Furthermore, a buffer layer 5 is arranged on the lower surface of the chip 1. The buffer layer 5 wraps the edge of the microbump 21. A first sealed heat dissipation channel is formed between the buffer layer 5 and the heat dissipation groove 31 of the heat dissipation dam body 3. By arranging the buffer layer 5 to seal the heat dissipation groove 31, the first sealed heat dissipation channel is formed to prevent the diffusion of the heat dissipation medium. Of course, the arrangement of the buffer layer 5 is not necessary, and the chip 1 can also play the role of sealing the heat dissipation groove 31. It can be understood that the buffer layer 5 is an organic buffer layer 5. The buffer layer 5 does not completely cover the lower surface of the chip 1, and the solder pads of the chip 1 are in an exposed state. The microbumps 21 are connected to the solder pads of the chip 1. By arranging the buffer layer 5 to wrap the edge of the microbump 21, part of the stress of the microbump 21 is reduced to prevent cracks from occurring in the microbump 21. In addition, the height of the heat dissipation dam body 3 is equal to or slightly less than the minimum distance between two adjacent chips 1. After the heat dissipation dam body 3 is cured or semi-cured, it can provide good support for two adjacent chips 1, maintain the balance of the chips 1 and the distance between the chips 1, reduce the influence of stress on the microbumps 21, and improve the yield.
[0044] Even further, the thickness of the buffer layer 5 is 1 / 5 - 1 / 4 of the height of the microbump 21. By this setting, it is prevented that the buffer layer 5 is too thin to play a buffering role.
[0045] Furthermore, as Figure 4 and Figure 5 shown, in order to facilitate the flow of the heat dissipation medium, the corner 313 of the heat dissipation groove 31 is set to be arc-shaped.
[0046] Furthermore, as Figure 5 shown, the heat dissipation groove 31 is a complete structure, and the head end and the tail end of the heat dissipation groove 31 are located on the same side of the chip 1; or, as Figure 4As shown, there are two heat dissipation grooves 31. The head and tail ends of the heat dissipation grooves 31 are located on both sides of the chip 1. At this time, the head ends of the two heat dissipation grooves 31 are connected through the liquid inlet 311, and the tail ends of the two heat dissipation grooves 31 are connected through the liquid outlet 312. It can be understood that the specific structure of the heat dissipation groove 31 is selected according to the actual situation and is not limited here.
[0047] Furthermore, as Figure 4 shown, in order for the heat dissipation medium to smoothly enter the heat dissipation groove 31 and improve the convenience of the heat dissipation medium entering the heat dissipation groove 31, when the head and tail ends of the heat dissipation groove 31 are located on both sides of the chip 1, the connection between the liquid inlet 311 of the heat dissipation groove 31 and the encapsulant layer 4 forms an inclination angle towards the encapsulant layer 4, so as to increase the size of the liquid inlet 311 and conduct drainage and guidance for the heat dissipation medium.
[0048] Furthermore, in the actual production process, the number of stacked chips, the arrangement pattern of the chips, the size of the chips, and the types of different chips are not specifically limited and are selected according to actual needs.
[0049] Embodiment Two
[0050] For the parts in this embodiment that are the same as those in Embodiment One, the same reference numerals are given and the same textual descriptions are omitted.
[0051] Compared with Embodiment One, the multi-chip stacked package structure provided in this embodiment also has the following different structural designs:
[0052] As Figure 6 and Figure 7 shown, the multi-chip stacked package structure further includes an interposer 6, a heat dissipation adhesive layer 8, and a heat dissipation cover 9. The lowermost chip 1 is connected to the interposer 6 through a welding structure 2 to achieve electrical connection. An encapsulant layer 4 is provided between the lowermost chip 1 and the interposer 6 to wrap the welding structure 2. A plurality of solder balls 7 are provided at intervals at the bottom of the interposer 6. Liquid inlet channels 10 and / or liquid outlet channels 11 for the heat dissipation medium to pass through are formed on the interposer 6. A heat dissipation adhesive layer 8 is provided on the side surfaces of the plurality of chips 1, and communication holes 81 are provided at the liquid inlet 311 and / or the liquid outlet 312 of the heat dissipation dam body 3 in the heat dissipation adhesive layer 8. At this time, the heat dissipation medium enters the communication holes 81 of the heat dissipation adhesive layer 8 from the liquid inlet 311 and / or the liquid outlet 312, and the heat dissipation adhesive layer 8 disperses the heat to improve the heat dissipation performance. A heat dissipation cover 9 is located outside the heat dissipation adhesive layer 8. The bottom of the heat dissipation cover 9 is connected to the interposer 6. A second sealed heat dissipation channel 91 is provided inside the heat dissipation cover 9. A plurality of through holes 92 corresponding to the communication holes 81 of the heat dissipation adhesive layer 8 are provided on the side wall of the heat dissipation cover 9. Liquid outlet through holes and / or liquid inlet through holes corresponding to the liquid outlet channels 11 and / or the liquid inlet channels 10 of the interposer 6 are provided at the bottom of the heat dissipation cover 9, and the through holes 92 are connected to the second sealed heat dissipation channel 91.
[0053] Specifically, the heat dissipation medium enters the second sealed heat dissipation channel 91 through the liquid inlet channel 10, then enters the liquid inlet 311 of each individual chip 1 respectively, flows in the heat dissipation groove 31 to the liquid outlet 312 of the individual chip 1, then enters the second sealed heat dissipation channel 91 of the heat dissipation cover 9, and finally flows out through the liquid outlet channel 11, realizing the circulation of the heat dissipation medium, and undergoing multiple heat dissipations through the heat dissipation cover 9 and the heat dissipation adhesive layer 8 to enhance the heat dissipation effect.
[0054] It can be understood that only the liquid inlet channel 10 or the liquid outlet channel 11 can be opened on the adapter board 6, or both channels can be opened simultaneously, without specific restrictions, and it can be selected according to the actual situation.
[0055] It can be understood that one end of the second sealed heat dissipation channel 91 is respectively connected to the communication hole of the heat dissipation adhesive layer 8, and the other end of the second sealed heat dissipation channel 91 is provided with corresponding liquid outlet through holes and / or liquid inlet through holes at the top or bottom of the heat dissipation cover 9. The liquid outlet through holes and / or liquid inlet through holes can be located on the same side of the chip or on the opposite sides of the chip. The liquid outlet through holes and / or liquid inlet through holes can be located at the top of the heat dissipation cover 9 or at the bottom of the heat dissipation cover 9, corresponding to the liquid inlet channel 10 or the liquid outlet channel 11 of the adapter board 6.
[0056] Furthermore, in order to improve the heat dissipation effect between the lowermost chip 1 and the adapter board 6, a heat dissipation dam body 3 is further provided between the bottom edge of the chip 1 at the lowermost end and the adapter board 6, and the heat dissipation dam body between the chip and the adapter board is used to dissipate heat from the lowermost chip.
[0057] It can be understood that as Figure 7 shown, in order to further enhance the heat dissipation effect, the heat dissipation cover 9 also covers the top surface of the uppermost chip.
[0058] Furthermore, in order to ensure that the communication hole 81 of the heat dissipation adhesive layer 8 can be aligned with the liquid inlet 311 and / or the liquid outlet 312, reducing the alignment difficulty, the size of the communication hole 81 is larger than the size of the liquid inlet 311 and / or the liquid outlet 312.
[0059] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combinations of these technical features do not conflict, they should all be considered as within the scope described in this specification.
Claims
1. A multi-chip stacked packaging structure, characterized in that, Comprising: At least two chips stacked vertically; A welding structure located between two adjacent chips for supporting the chips; A heat dissipation dam body disposed between two adjacent chips and at the surface edge of the chips. The heat dissipation dam body supports two adjacent chips. The upper surface of the heat dissipation dam body has heat dissipation grooves. A first sealed heat dissipation channel is formed between the heat dissipation grooves of the heat dissipation dam body and the chips. The heat dissipation grooves are filled with a heat dissipation medium; A glue filling layer disposed in the area enclosed by two adjacent chips and the heat dissipation dam body. The glue filling layer wraps the welding structure.
2. The multi-chip stacked package structure according to claim 1, wherein The head end of the heat dissipation groove has a liquid inlet, and the tail end of the heat dissipation groove has a liquid outlet.
3. The multi-chip stacked package structure according to claim 1, wherein The heat dissipation dam body is provided with a glue filling layer injection opening.
4. The multi-chip stacked package structure according to claim 1, characterized in that The welding structure includes a plurality of microbumps which are spaced apart. The microbumps connect two adjacent chips and achieve electrical connection.
5. The multi-chip stacked packaging structure according to claim 4, wherein, A buffer layer is disposed on the lower surface of the chip. The buffer layer wraps the edge of the microbumps. A first sealed heat dissipation channel is formed between the buffer layer and the heat dissipation grooves of the heat dissipation dam body.
6. The multi-chip stacked package structure according to claim 2, wherein, A heat dissipation glue layer and a heat dissipation cover located on the side wall of the heat dissipation glue layer are disposed on the side surface of the at least two vertically stacked chips. The heat dissipation glue layer is provided with communication holes at the liquid inlet and liquid outlet of the heat dissipation dam body. The heat dissipation cover has a second sealed heat dissipation channel. One end of the second sealed heat dissipation channel is respectively connected to the communication holes of the heat dissipation glue layer. The other end of the second sealed heat dissipation channel is provided with corresponding liquid outlet through holes and / or liquid inlet through holes at the top or bottom of the heat dissipation cover.
7. The multi-chip stacked packaging structure according to claim 6, wherein The size of the communication holes of the heat dissipation glue layer is larger than the size of the liquid inlet and / or liquid outlet.
8. The multi-chip stacked packaging structure according to claim 6, wherein The heat dissipation cover also covers the top surface of the topmost chip.
9. The multi-chip stacked packaging structure according to claim 6, wherein Further comprising an adapter board. The chip at the lowermost end is connected to the adapter board; The adapter board is provided with a liquid inlet channel and a liquid outlet channel for the heat dissipation medium to pass through. The liquid inlet channel and the liquid outlet channel are communicated with the liquid outlet through holes and liquid inlet through holes of the heat dissipation cover.
10. The multi-chip stacked package structure according to claim 9, wherein, A heat dissipation dam body is further disposed between the bottom edge of the chip at the lowermost end and the adapter board. The heat dissipation dam body supports the adjacent chip and the adapter board. The upper surface of the heat dissipation dam body has heat dissipation grooves. A first sealed heat dissipation channel is formed between the heat dissipation grooves of the heat dissipation dam body and the chip. The head end of the heat dissipation groove has a liquid inlet, and the tail end of the heat dissipation groove has a liquid outlet. The heat dissipation grooves are used for filling a heat dissipation medium.
11. The multi-chip stacked package structure according to claim 1, wherein The corners of the heat dissipation grooves are set to be arc-shaped.
12. The multi-chip stacked packaging structure according to claim 2, wherein The head end and the tail end of the heat dissipation groove are located on the same side of the chip; or, the head end and the tail end of the heat dissipation groove are located on both sides of the chip.
13. The multi-chip stacked packaging structure according to claim 12, wherein When the head end and the tail end of the heat dissipation groove are located on both sides of the chip, an inclination angle inclined towards the glue filling layer is formed at the connection between the liquid inlet of the heat dissipation groove and the glue filling layer.