Delay reset circuit

Abstract

The utility model provides a time-delay reset circuit, which can effectively prevent the abnormal phenomenon of chip latching caused by the jitter of a relay contact, and ensures that the circuit can work normally after a surge suppression chip is reset. The surge suppression circuit comprises a surge suppression chip IC1, the surge suppression chip IC1 is an SW4356MF surge suppression chip, the outside of the surge suppression chip IC1 is connected with an input voltage Vin + through a peripheral circuit, an SHDN pin of the surge suppression chip IC1 is connected with an ON / OFF switch signal sent by an external control signal through the peripheral circuit, the SHDN pin of the surge suppression chip IC1 is connected with a delay reset circuit, and the delay reset circuit is connected with the surge suppression chip IC1. When the input voltage Vin + is lower than the threshold voltage 12V, a reset signal for controlling the surge suppression chip IC1 is generated through the delay reset circuit, and the delay time of the reset signal is set to be 10ms and is greater than the jitter time of an external relay, so that the surge suppression chip IC1 is in a reset state.

Description

Technical Field

[0001] The utility model relates to the technical field of power protection circuits, and particularly relates to a delay reset circuit. Background Art

[0002] In the actual application process of a surge suppression circuit, as one of the commonly used chips for a power supply, the SHDN pin of the SW4356MF surge suppression chip is externally connected to an electromagnetic relay for receiving and sending switch signals to control the on / off of the chip. However, during the power-on startup or power supply switching process, the relay element is prone to jitter when it is energized, that is, the contacts of the electromagnetic relay generate jitter, which easily leads to the instability of the input power supply voltage. The instability of the input power supply voltage is likely to cause the chip to lock up, resulting in the chip being locked in the off state all the time. Since the SHDN pin also has a reset function, it is difficult for it to work properly, thus affecting the normal operation of the circuit. Content of the Utility Model

[0003] Aiming at the problem that during the power-on startup or power supply switching process of the existing power supply, the contacts of the relay generate jitter, causing the input power supply chip to lock up and the device to be in the off state, thus affecting the normal operation of the circuit, the utility model provides a delay reset circuit, which can effectively prevent the abnormal phenomenon of chip latching caused by the jitter of the relay contacts, ensure the reset function of the chip, and enable the circuit to work normally.

[0004] Its technical solution is as follows: a delay reset circuit, which includes a surge suppression chip IC1. The surge suppression chip IC1 is an SW4356MF surge suppression chip. The outside of the surge suppression chip IC1 is connected to the input voltage Vin+ through a peripheral circuit. The SHDN pin of the surge suppression chip IC1 is connected to the ON / OFF switch signal sent by an external relay through a peripheral circuit. It is characterized in that: the SHDN pin of the surge suppression chip IC1 is connected to the delay reset circuit. When the input voltage Vin+ is lower than the threshold voltage of 12V, a reset signal for controlling the surge suppression chip IC1 is generated through the delay reset circuit. The delay time of this reset signal is set to 10ms and is greater than the jitter time of the external relay, so that the surge suppression chip IC1 is in the reset state.

[0005] It is further characterized in that: the delay reset circuit includes a triode Q1 and a comparator Q2. The base of the triode Q1 is connected to one end of a resistor R1 and one end of a resistor R4. The other end of the resistor R4 is connected to one end of a resistor R5 and the cathode of the comparator Q2. The collector of the triode Q1 is connected to one end of a resistor R3, one end of a capacitor C5, the collector of a triode Q3, and the SHDN reset pin of the surge suppression chip IC1. The reference pole of the comparator Q2 is connected to one end of a capacitor C3, one end of a resistor R6, and one end of a resistor R2. The emitter of the triode Q1, the other end of the resistor R1, the anode of the comparator Q2, the other end of the capacitor C3, the other end of the resistor R2, and the other end of the capacitor C5 are connected and then grounded. The other end of the resistor R5, the other end of the resistor R6, and the other end of the resistor R3 are connected to the input voltage Vin+. The base of the triode Q3 is connected to one end of a resistor RS. The other end of the resistor RS is connected to one end of a capacitor C4, one end of a resistor R15, one end of a resistor R16, and the ON / OFF switch signal terminal. The emitter of the triode Q3, the other end of the capacitor C4, and the other end of the resistor R15 are connected and then grounded. The other end of the resistor R16 is connected to the input voltage Vin+;

[0006] Both the triode Q1 and the triode Q3 adopt NPN triodes MMST5551, and the comparator Q2 adopts a TL431 zener diode.

[0007] After adopting the above structure, by connecting a delay reset circuit to the SHDN reset pin of the surge suppression chip IC1, when the input voltage Vin+ connected to the surge suppression chip IC1 is lower than the threshold voltage of 12V and the reset delay time is 10ms, which is greater than the jitter time of the relay, a reset signal for controlling the surge suppression chip IC1 is generated, causing the surge suppression chip IC1 to reset. Thus, it can effectively prevent the abnormal phenomenon of chip latching caused by contact jitter of the relay externally connected to the surge suppression chip IC1 and ensure the normal operation of the circuit. Description of the Drawings

[0008] Figure 1 It is the circuit schematic diagram of the present invention. Detailed Embodiment

[0009] A delay reset circuit, which includes a surge suppression chip IC1. The surge suppression chip IC1 is an SW4356MF surge suppression chip. The outside of the surge suppression chip IC1 is connected to the input voltage Vin+ through a peripheral circuit. The SHDN pin of the surge suppression chip IC1 is connected to the ON / OFF switch signal sent by an external relay through a peripheral circuit. The SHDN pin of the surge suppression chip IC1 is connected to the delay reset circuit. When the input voltage Vin+ is lower than the threshold voltage of 12V, a reset signal for controlling the surge suppression chip IC1 is generated through the delay reset circuit. The delay time of this reset signal is set to 10ms, and it is greater than the jitter time of the external relay (the jitter time is generally less than 5ms), so that the surge suppression chip IC1 is reset.

[0010] Specifically, the delay reset circuit includes a triode Q1 and a comparator Q2. The base of the triode Q1 is connected to one end of a resistor R1 and one end of a resistor R4. The other end of the resistor R4 is connected to one end of a resistor R5 and the cathode of the comparator Q2. The collector of the triode Q1 is connected to one end of a resistor R3, one end of a capacitor C5, the collector of a triode Q3, and the SHDN reset pin of the surge suppression chip IC1. The reference pole of the comparator Q2 is connected to one end of a capacitor C3, one end of a resistor R6, and one end of a resistor R2. The emitter of the triode Q1, the other end of the resistor R1, the anode of the comparator Q2, the other end of the capacitor C3, the other end of the resistor R2, and the other end of the capacitor C5 are connected together and grounded. The other end of the resistor R5, the other end of the resistor R6, and the other end of the resistor R3 are connected to the input voltage Vin+. The base of the triode Q3 is connected to one end of a resistor RS. The other end of the resistor RS is connected to one end of a capacitor C4, one end of a resistor R15, one end of a resistor R16, and the ON / OFF switch signal terminal. The emitter of the triode Q3, the other end of the capacitor C4, and the other end of the resistor R15 are connected together and grounded. The other end of the resistor R16 is connected to the input voltage Vin+. Among them, both the triode Q1 and the triode Q3 use NPN triodes MMST5551, and the comparator Q2 uses a TL431 voltage reference.

[0011] The threshold voltage of the input voltage Vin+ is set to 12V, so (R6 + R2) / R2 * 2.495 = 12

[0012] Select R2 as 24.9kΩ. After calculation, R6 = 94.86kΩ, so R6 is selected as 93.1 kΩ.

[0013] Among them, the capacitor C3 plays a role in delaying. When the input is 28V, the delay time when the capacitor C3 is charged to 2.495 is designed to be 10ms (the jitter time of the electromagnetic relay is generally less than 5ms). Therefore, for the capacitor C3:

[0014]

[0015] Where R = R1 / / R2 = 19.55 kΩ, after calculation, C3 is 0.9515 uF, and 1 uF is selected here.

[0016] During operation, when the contacts of the externally connected electromagnetic relay jitter, resulting in fluctuations in the input voltage, and when it is lower than the threshold voltage of 12V and the voltage applied to the REF pin of the comparator Q2 is lower than 2.495V, the NPN transistor Q1 conducts, and the SHDN pin of the SW4356MF is always in the low-level state, and the surge suppression chip is always in the reset state; when the input voltage is working normally and the voltage applied to the REF pin of the comparator Q2 is higher than 2.495V, the output (Cathode pin) of the comparator Q2 is at a low voltage, the NPN transistor Q1 is cut off, the SHDN pin of the SW4356MF is pulled high, and the SW4356MF works normally.

[0017] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those familiar with the technology within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A delay reset circuit, which includes a surge suppression chip IC1. The surge suppression chip IC1 is a SW4356MF surge suppression chip. The outside of the surge suppression chip IC1 is connected to the input voltage Vin+ through a peripheral circuit. The SHDN pin of the surge suppression chip IC1 is connected to the ON / OFF switch signal sent by an external relay through a peripheral circuit. It is characterized in that: The SHDN pin of the surge suppression chip IC1 is connected to the delay reset circuit. When the input voltage Vin+ is lower than the threshold voltage of 12V, a reset signal for controlling the surge suppression chip IC1 is generated through the delay reset circuit. The delay time of this reset signal is set to 10ms, and it is greater than the jitter time of the external relay, so that the surge suppression chip IC1 is in a reset state.

2. The delay reset circuit according to claim 1, wherein: The delay reset circuit includes a triode Q1 and a comparator Q2. The base of the triode Q1 is connected to one end of a resistor R1 and one end of a resistor R4. The other end of the resistor R4 is connected to one end of a resistor R5 and the cathode of the comparator Q2. The collector of the triode Q1 is connected to one end of a resistor R3, one end of a capacitor C5, the collector of a triode Q3, and the SHDN reset pin of the surge suppression chip IC1. The reference pole of the comparator Q2 is connected to one end of a capacitor C3, one end of a resistor R6, and one end of a resistor R2. The emitter of the triode Q1, the other end of the resistor R1, the anode of the comparator Q2, the other end of the capacitor C3, the other end of the resistor R2, and the other end of the capacitor C5 are connected together and grounded. The other end of the resistor R5, the other end of the resistor R6, and the other end of the resistor R3 are connected to the input voltage Vin+. The base of the triode Q3 is connected to one end of a resistor RS. The other end of the resistor RS is connected to one end of a capacitor C4, one end of a resistor R15, one end of a resistor R16, and the ON / OFF switch signal terminal. The emitter of the triode Q3, the other end of the capacitor C4, and the other end of the resistor R15 are connected together and grounded. The other end of the resistor R16 is connected to the input voltage Vin+.

3. The delay reset circuit according to claim 2, wherein: Both the triode Q1 and the triode Q3 use the NPN triode MMST5551, and the comparator Q2 uses the TL431 voltage reference.

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