Isolation circuit, isolation chip and isolation device

Abstract

The utility model discloses an isolation circuit, an isolation chip and an isolation device, and relates to the technical field of electronic circuits, the isolation circuit is provided with an isolation strip, one side of the isolation strip is provided with a signal input module, and the other side of the isolation strip is provided with a signal output module; the signal input module comprises an input unit, a radio frequency transmitting unit and an antenna transmitting unit which are electrically connected in sequence, and the signal output module comprises an antenna receiving unit, a radio frequency receiving unit and an output unit which are electrically connected in sequence. The utility model aims to improve the data transmission performance of the isolation comparator.

Description

Technical Field

[0001] The utility model relates to the technical field of electronic circuits, and particularly relates to an isolation circuit, an isolation chip and an isolation device. Background Art

[0002] With the rapid development of electronic circuit technology, users have put forward higher requirements for the data transmission performance of isolation comparators.

[0003] Traditional isolation comparators usually adopt a capacitive coupling isolation scheme. Although this scheme has a simple structure, it has obvious disadvantages, such as low signal transmission rate, large transmission delay, and poor isolation withstand voltage ability and CMTI (Common Mode Transient Immunity) due to process limitations, which makes the isolation comparator vulnerable to influence in the face of high voltage and complex electromagnetic environment, further weakening the data transmission performance of the isolation comparator.

[0004] Therefore, how to improve the data transmission performance of isolation comparators is a technical problem that needs to be solved urgently at present. Summary of the Utility Model

[0005] The main object of the utility model is to propose an isolation circuit, an isolation chip and an isolation device, aiming to improve the data transmission performance of isolation comparators.

[0006] To achieve the above object, the utility model proposes an isolation circuit, and the isolation circuit includes:

[0007] The isolation circuit is provided with an isolation belt, and a signal input module is arranged on one side of the isolation belt, and a signal output module is arranged on the other side of the isolation belt;

[0008] The signal input module includes an input unit, a radio frequency transmitting unit and an antenna transmitting unit which are electrically connected in sequence, and the signal output module includes an antenna receiving unit, a radio frequency receiving unit and an output unit which are electrically connected in sequence.

[0009] In an embodiment, the input unit at least includes a signal input interface, a voltage comparison sub-unit and a first logic sub-unit which are electrically connected in sequence;

[0010] The voltage comparison sub-unit includes a first comparator and a second comparator;

[0011] The positive input terminals of the first comparator and the second comparator are electrically connected to form the signal input interface;

[0012] The negative input terminal of the first comparator is electrically connected to the positive reference voltage terminal, the negative input terminal of the second comparator is electrically connected to the negative reference voltage terminal, the output terminals of the first comparator and the second comparator are respectively electrically connected to the first logic sub-unit, and the first logic sub-unit is electrically connected to the radio frequency transmitting unit.

[0013] In one embodiment, the first logic sub-unit includes a first NOT gate, a second NOT gate, a first AND gate, a second AND gate, and an OR gate;

[0014] The output terminal of the first comparator is respectively electrically connected to the input terminal of the first NOT gate and the first input terminal of the second AND gate, and the output terminal of the second comparator is respectively electrically connected to the input terminal of the second NOT gate and the second input terminal of the first AND gate;

[0015] The output terminal of the first NOT gate is electrically connected to the first input terminal of the first AND gate, the output terminal of the second NOT gate is electrically connected to the second input terminal of the second AND gate, the output terminal of the first AND gate is electrically connected to the first input terminal of the OR gate, the output terminal of the second AND gate is electrically connected to the second input terminal of the OR gate, and the output terminal of the OR gate is electrically connected to the radio frequency transmitting unit.

[0016] In one embodiment, the first comparator is a positive voltage comparator, and the second comparator is a negative voltage comparator.

[0017] In one embodiment, the output unit includes a second logic sub-unit, a power switch device, and a signal output sub-unit, and the second logic sub-unit is a third NOT gate;

[0018] The input terminal of the third NOT gate is electrically connected to the radio frequency receiving unit, the output terminal of the third NOT gate is electrically connected to the control terminal of the power switch device, the first path terminal of the power switch device is electrically connected to the signal output sub-unit, and the second path terminal of the power switch device is grounded.

[0019] In one embodiment, the power switch device is an N-type MOS transistor.

[0020] In one embodiment, the signal output sub-unit is a pull-up resistor;

[0021] The first end of the pull-up resistor is electrically connected to a preset power supply terminal;

[0022] The second end of the pull-up resistor and the first path terminal of the power switch device form a signal output interface.

[0023] In one embodiment, the RF transmitting unit is an RF transmitting circuit, the antenna transmitting unit is a transmitting antenna, the RF receiving unit is an RF receiving circuit, and the antenna receiving unit is a receiving antenna.

[0024] In addition, the present utility model also proposes an isolation chip, which at least includes the isolation circuit described in any one of the above.

[0025] In addition, the present utility model also proposes an isolation device, which at least includes the above-mentioned isolation chip.

[0026] The isolation circuit provided by the present utility model significantly improves the data transmission performance of the isolation comparator by introducing RF technology and millimeter-wave wireless technology. Specifically, the isolation circuit provided in this application is structurally provided with an isolation band, so that the signal input module and the signal output module can be separated, ensuring the isolation of signal transmission. In the signal input module, the input unit converts the original signal into an RF signal suitable for RF transmission form, and then through the electrical connection between the RF transmitting unit and the antenna transmitting unit, the antenna transmitting unit converts the RF signal into a millimeter-wave wireless signal for wireless transmission. At this time, the antenna receiving unit in the signal output module restores the captured millimeter-wave wireless signal emitted by the antenna transmitting unit into an RF signal and sends it to the RF receiving unit. After the RF receiving unit restores the RF signal into the original signal form, it is output to the output unit for processing, which not only greatly improves the signal transmission rate and reduces the transmission delay, but also effectively improves the isolation withstand voltage ability and CMTI through wireless transmission, making the isolation comparator applied to this isolation circuit show higher stability and reliability in the face of high voltage and complex electromagnetic environment, and significantly improving the data transmission performance. Description of the Drawings

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on the structures shown in these drawings.

[0028] Figure 1 It is a schematic structural diagram of an embodiment of the isolation circuit provided by the present utility model;

[0029] Figure 2 It is a schematic diagram of the voltage comparison sub-unit involved in the embodiment of the present utility model;

[0030] Figure 3 It is a schematic diagram of the first logic sub-unit involved in the embodiment of the present utility model;

[0031] Figure 4 Schematic diagram of the isolation circuit structure according to an embodiment of the present utility model;

[0032] Figure 5 Timing diagram of the isolation circuit according to an embodiment of the present utility model.

[0033] Explanation of the reference numerals in the drawings:

[0034] 10. Isolation strip; 20. Signal input module; 30. Signal output module; 201. Input unit; RF_TX. Radio frequency transmitting unit; ANT1. Antenna transmitting unit; ANT2. Antenna receiving unit; RF_RX. Radio frequency receiving unit; 301. Output unit; 201. Input unit; input. Signal input interface; 21. Voltage comparison sub-unit; Logic1. First logic sub-unit; CMP1. First comparator; CMP2. Second comparator; F1. First NOT gate; F2. Second NOT gate; A1. First AND gate; A2. Second AND gate; OR1. OR gate; Logic2. Second logic sub-unit; R1. Pull-up resistor; output. Signal output interface; Q1. Power switch device.

[0035] The realization, functional features and advantages of the purpose of the present utility model will be further described with reference to the embodiments and the accompanying drawings. Specific embodiments

[0036] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without creative efforts shall fall within the protection scope of the present utility model.

[0037] It should be noted that if there are directional indications (such as up, down, left, right, front, back...) involved in the embodiments of the present utility model, the directional indications are only used to explain the relative positional relationship and movement conditions between components in a specific posture. If the specific posture changes, the directional indications will also change accordingly.

[0038] In addition, if the descriptions such as "first", "second", etc. are involved in the embodiments of the present utility model, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be construed as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first", "second" may explicitly or implicitly include at least one such feature. In addition, if "and / or" or "and / or" appears throughout the text, its meaning includes three parallel scenarios. Taking "A and / or B" as an example, it includes Scenario A, or Scenario B, or the scenario where both A and B are satisfied simultaneously. In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present utility model.

[0039] Traditional isolation comparators tend to adopt capacitive coupling isolation schemes. Although this scheme appears relatively simple in structure, it exposes significant deficiencies in practical applications. First, the low signal transmission rate becomes one of the key factors restricting its performance and cannot meet the requirements of modern high-speed data transmission. Second, due to the large transmission delay, this isolation scheme performs poorly in systems that require fast response. More seriously, limited by manufacturing processes and material characteristics, traditional capacitive coupling isolation schemes perform poorly in terms of isolation withstand voltage and CMTI (Common Mode Transient Immunity), resulting in being easily affected in the face of high voltages and complex electromagnetic environments, further weakening the data transmission performance of the isolation comparator. These drawbacks limit the wide application of isolation comparators in high-speed, high-precision, and high-reliability applications, making it difficult for their data transmission performance to meet the requirements of modern electronic systems.

[0040] In summary, in order to solve the above technical defects and improve the data transmission performance of the isolation comparator, the present utility model proposes an isolation circuit, an isolation chip, and an isolation device.

[0041] In an embodiment of the present utility model, please refer to Figure 1 , Figure 1 which is a schematic structural diagram of an embodiment of the isolation circuit provided by the present utility model. The isolation circuit is provided with an isolation strip 10, and a signal input module 20 is arranged on one side of the isolation strip 10, and a signal output module 30 is arranged on the other side of the isolation strip 10;

[0042] The signal input module 20 includes an input unit 201, a radio frequency transmitting unit RF_TX, and an antenna transmitting unit that are electrically connected in sequence. The signal output module 30 includes an antenna receiving unit, a radio frequency receiving unit, and an output unit 301 that are electrically connected in sequence.

[0043] In this embodiment, the utility model is configured to effectively isolate the signal input module 20 and the signal output module 30 by providing an isolation band 10 in the isolation circuit, avoiding possible interference and mutual influence. The signal input module 20 uses a radio frequency transmitting unit RF_TX and an antenna transmitting unit to convert the original signal into a radio frequency signal and wirelessly convert it into a millimeter-wave wireless signal for transmission. This not only greatly speeds up the signal transmission rate but also significantly reduces the transmission delay. At this time, the signal output module 30 captures the radio frequency signal through the antenna receiving unit, and after being processed by the radio frequency receiving unit and the antenna transmitting unit, it is restored to the original signal and output to the output unit 301 for processing. This isolation circuit design based on radio frequency technology and millimeter-wave technology not only ensures the isolation of data transmission but also significantly improves the isolation withstand voltage and common-mode transient immunity (i.e., CMTI), enabling the isolation comparator applied to this isolation circuit to maintain a stable working state in the face of high voltage and complex electromagnetic environments, thus significantly enhancing the data transmission performance of the isolation comparator.

[0044] Further, in some feasible embodiments, referring to Figure 2 , Figure 2 is a schematic diagram of the voltage comparison sub-unit 21 involved in the embodiment of the present utility model. The input unit 201 includes at least a signal input interface input, a voltage comparison sub-unit 21, and a first logic sub-unit Logic1 that are electrically connected in sequence;

[0045] The voltage comparison sub-unit 21 includes a first comparator CMP1 and a second comparator CMP2;

[0046] The positive input terminals of the first comparator CMP1 and the second comparator CMP2 are electrically connected to form the signal input interface input;

[0047] The negative input terminal of the first comparator CMP1 is electrically connected to the positive reference voltage terminal, the negative input terminal of the second comparator CMP2 is electrically connected to the negative reference voltage terminal, the output terminals of the first comparator CMP1 and the second comparator CMP2 are respectively electrically connected to the first logic sub-unit Logic1, and the first logic sub-unit Logic1 is electrically connected to the radio frequency transmitting unit RF_TX.

[0048] In this embodiment, after an input signal (i.e., the Input signal) is applied to the positive input terminals of the first comparator CMP1 and the second comparator CMP2, when the Input signal is greater than the +Vref voltage applied to the negative input terminal of the first comparator CMP1, the output terminal of the first comparator CMP1 outputs a high level; otherwise, it outputs a low level. When the Input signal is greater than the -Vref voltage applied to the negative input terminal of the second comparator CMP2, the output terminal of the second comparator CMP2 outputs a high level; otherwise, it outputs a low level. Next, the first logic sub-unit Logic1 converts the dual-channel output signal into a single-channel signal through exclusive-OR processing and inputs it to the radio frequency transmitting unit RF_TX.

[0049] It should be noted that the +Vref voltage refers to the positive comparison voltage threshold, which can be customized according to application requirements; the -Vref voltage refers to the negative comparison voltage threshold, which can also be customized according to application requirements.

[0050] In this embodiment, the dual-channel comparator system (i.e., the first comparator CMP1 and the second comparator CMP2) provided in this application realizes precise threshold detection of the input signal (Input signal). When the Input signal exceeds the set +Vref voltage, the first comparator CMP1 outputs a signal Out_CMP1 representing a high level; otherwise, it outputs a signal Out_CMP1 representing a low level. When the Input signal is lower than the set -Vref voltage, the second comparator CMP2 outputs a signal Out_CMP2 representing a high level; otherwise, it outputs a signal Out_CMP2 representing a low level. This dual-channel design makes the threshold detection of the signal more flexible and precise, and is suitable for application scenarios that require precise determination of the upper and lower limits of the signal. By performing exclusive-OR processing on these two channels of signals through the first logic sub-unit Logic1, not only the design of the subsequent circuit is simplified, but also the dual-channel signal is successfully converted into a single-channel signal, facilitating the processing and transmission of the subsequent radio frequency transmitting unit RF_TX, thereby improving the signal processing efficiency and accuracy while enhancing the stability and reliability of the system.

[0051] Further, in some feasible embodiments, referring to Figure 3 , Figure 3 is a schematic diagram of the first logic sub-unit Logic1 according to an embodiment of the present invention. The first logic sub-unit Logic1 includes a first NOT gate F1, a second NOT gate F2, a first AND gate A1, a second AND gate A2, and an OR gate OR1;

[0052] The output terminal of the first comparator CMP1 is electrically connected to the input terminal of the first NOT gate F1 and the first input terminal of the second AND gate A2 respectively. The output terminal of the second comparator CMP2 is electrically connected to the input terminal of the second NOT gate F2 and the second input terminal of the first AND gate A1 respectively;

[0053] The output terminal of the first NOT gate F1 is electrically connected to the first input terminal of the first AND gate A1. The output terminal of the second NOT gate F2 is electrically connected to the second input terminal of the second AND gate A2. The output terminal of the first AND gate A1 is electrically connected to the first input terminal of the OR gate OR1. The output terminal of the second AND gate is electrically connected to the second input terminal of the OR gate OR1. The output terminal of the OR gate OR1 is electrically connected to the radio frequency transmitting unit RF_TX.

[0054] In this embodiment, the first logic sub-unit Logic1 provided in the present application realizes the exclusive OR processing of the output signals of the dual comparators (i.e., Figures 2 to 3 the shown signal Out_CMP1 and signal Out_CMP2) by skillfully combining the first NOT gate F1, the second NOT gate F2, the first AND gate A1, the second AND gate A2, and the OR gate OR1. Specifically, the output terminals of the first comparator CMP1 and the second comparator CMP2 are respectively connected to the input terminals of the corresponding NOT gates and AND gates, forming two parallel logic processing paths. The NOT gate is used to invert the output signal of the comparator, while the AND gate is used to combine the signals under specific conditions. Finally, the output terminals of the two AND gates perform a logical OR operation through the OR gate OR1 to generate a single-path signal and transmit it to the radio frequency transmitting unit RF_TX. This design not only simplifies the circuit structure, improves the efficiency of signal processing, but also realizes the exclusive OR processing of the dual-path signals through logical operations, enhancing the flexibility and reliability of the system.

[0055] Furthermore, in some other feasible embodiments, the first comparator CMP1 is a positive voltage comparator, and the second comparator CMP2 is a negative voltage comparator.

[0056] Furthermore, in some feasible embodiments, referring to Figure 4 , Figure 4 is a schematic diagram of the isolation circuit structure involved in the embodiment of the present invention. The output unit 301 includes a second logic sub-unit Logic2, a power switch device Q1, and a signal output sub-unit. The second logic sub-unit Logic2 is a third NOT gate;

[0057] The input terminal of the third NOT gate is electrically connected to the RF receiving unit, the output terminal of the third NOT gate is electrically connected to the control terminal of the power switch device Q1, the first path terminal of the power switch device Q1 is electrically connected to the signal output sub-unit, and the second path terminal of the power switch device Q1 is grounded.

[0058] Further, in some other feasible embodiments, the power switch device Q1 is an N-type MOS transistor.

[0059] Further, in some feasible embodiments, the signal output sub-unit is a pull-up resistor R1;

[0060] The first terminal of the pull-up resistor R1 is electrically connected to a preset power supply terminal;

[0061] The second terminal of the pull-up resistor R1 and the first path terminal of the power switch device Q1 form a signal output interface output.

[0062] In this embodiment, when both the first comparator CMP1 and the second comparator CMP2 provided in this application output a low level (or a high level), the first logic sub-unit Logic1 can convert the signals of the low level (or high level) output in parallel in a dual path into a single-path signal representing a low level through the first logic sub-unit Logic1. After being processed by the RF transmitting unit RF_TX, the antenna transmitting unit, the antenna receiving unit, and the RF receiving unit, at this time, the output unit 301 inverts the single-path signal through the third NOT gate and then drives the N-type MOS transistor, enabling the N-type MOS transistor to be turned on by accessing the VDD2 voltage that powers the signal output module 30 through the pull-up resistor R1, and outputting a signal Output representing a high level.

[0063] It should be noted that the power switch device Q1 provided in this application adopts an open-drain connection method and needs an external pull-up resistor R1 to output a high level; Figure 4 The shown VDD1 voltage powers the signal input module 20, Figure 4 The shown VDD2 voltage powers the signal output module 30.

[0064] Further, in some other feasible embodiments, the RF transmitting unit RF_TX is an RF transmitting circuit, the antenna transmitting unit ANT1 is a transmitting antenna, the RF receiving unit RF_RX is an RF receiving circuit, and the antenna receiving unit ANT2 is a receiving antenna.

[0065] In yet another embodiment, referring to Figure 5 , Figure 5This is the timing diagram of the isolation circuit involved in the embodiment of the present utility model. When the Input signal is greater than the +Vref voltage and less than the -Vref voltage, or when the Input signal is less than the +Vref voltage and greater than the -Vref voltage, the Output will output a low level. In other cases, the Output outputs a high level.

[0066] In summary, this application uses millimeter-wave technology to achieve isolation between the input and output of an isolation comparator applied to an isolation circuit. Millimeter-wave isolation supports high-bandwidth and low-latency data transmission. At the same time, the isolation distance of the isolation band 10 can also be defined according to requirements, and can even reach the centimeter level, thereby achieving extremely high isolation withstand voltage capabilities. As the isolation distance increases, the parasitic capacitance decreases accordingly, and the CMTI ability will also be greatly improved.

[0067] The present utility model also proposes an isolation chip, which at least includes the above-mentioned isolation circuit. The specific structure of this isolation circuit refers to the above-mentioned embodiment. Since the isolation chip adopts all the technical solutions of the above-mentioned all embodiments, it at least has all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, and will not be elaborated here one by one.

[0068] The present utility model also proposes an isolation device, which at least includes the above-mentioned isolation chip. The specific structure of this isolation device refers to the above-mentioned embodiment. Since the isolation device adopts all the technical solutions of the above-mentioned all embodiments, it at least has all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, and will not be elaborated here one by one.

[0069] It should be noted that the isolation device can be an isolation comparator.

[0070] The above is only an exemplary embodiment of the present utility model, and does not limit the patent scope of the present utility model. All equivalent structural transformations made under the technical concept of the present utility model by using the content of the specification and drawings of the present utility model, or directly / indirectly applied in other related electronic circuit technical fields are included in the patent protection scope of the present utility model.

Claims

1. An isolation circuit, characterized in that, The isolation circuit is provided with an isolation belt, a signal input module is provided on one side of the isolation belt, and a signal output module is provided on the other side of the isolation belt; The signal input module includes an input unit, a radio frequency transmitting unit, and an antenna transmitting unit that are electrically connected in sequence. The signal output module includes an antenna receiving unit, a radio frequency receiving unit, and an output unit that are electrically connected in sequence; The input unit at least includes a signal input interface, a voltage comparison sub-unit, and a first logic sub-unit that are electrically connected in sequence; The voltage comparison sub-unit includes a first comparator and a second comparator; The positive input terminal of the first comparator and the positive input terminal of the second comparator are electrically connected to form the signal input interface; The negative input terminal of the first comparator is electrically connected to the positive reference voltage terminal, the negative input terminal of the second comparator is electrically connected to the negative reference voltage terminal, the output terminals of the first comparator and the second comparator are respectively electrically connected to the first logic sub-unit, and the first logic sub-unit is electrically connected to the radio frequency transmitting unit; The output unit includes a second logic sub-unit, a power switch device, and a signal output sub-unit. The second logic sub-unit is a third NOT gate; The input terminal of the third NOT gate is electrically connected to the radio frequency receiving unit, the output terminal of the third NOT gate is electrically connected to the control terminal of the power switch device, the first path terminal of the power switch device is electrically connected to the signal output sub-unit, and the second path terminal of the power switch device is grounded.

2. The isolation circuit according to claim 1, wherein The first logic sub-unit includes a first NOT gate, a second NOT gate, a first AND gate, a second AND gate, and an OR gate; The output terminal of the first comparator is respectively electrically connected to the input terminal of the first NOT gate and the first input terminal of the second AND gate. The output terminal of the second comparator is respectively electrically connected to the input terminal of the second NOT gate and the second input terminal of the first AND gate; The output terminal of the first NOT gate is electrically connected to the first input terminal of the first AND gate, the output terminal of the second NOT gate is electrically connected to the second input terminal of the second AND gate, the output terminal of the first AND gate is electrically connected to the first input terminal of the OR gate, the output terminal of the second AND gate is electrically connected to the second input terminal of the OR gate, and the output terminal of the OR gate is electrically connected to the radio frequency transmitting unit.

3. The isolation circuit according to claim 1, wherein The first comparator is a positive voltage comparator, and the second comparator is a negative voltage comparator.

4. The isolation circuit according to claim 1, characterized in that, The power switch device is an N-type MOS transistor.

5. The isolation circuit according to claim 1, wherein The signal output sub-unit is a pull-up resistor; The first end of the pull-up resistor is electrically connected to a preset power supply terminal; The second end of the pull-up resistor and the first path terminal of the power switch device form a signal output interface.

6. The isolation circuit according to claim 1, wherein The radio frequency transmitting unit is a radio frequency transmitting circuit, the antenna transmitting unit is a transmitting antenna, the radio frequency receiving unit is a radio frequency receiving circuit, and the antenna receiving unit is a receiving antenna.

7. An isolation chip, characterized in that, The isolation chip at least includes the isolation circuit according to any one of claims 1 to 6.

8. An isolation device, characterized in that, The isolation device at least includes the isolation chip according to claim 7.

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