Thermal test chip

Abstract

The utility model discloses a thermal test chip, which comprises a first substrate, a second substrate and a packaging layer, and is characterized in that the first substrate comprises a first substrate, a heating layer and a plurality of first solder balls, the heating layer and the plurality of first solder balls are sequentially stacked on the first side of the first substrate, and the heating layer comprises a plurality of heating units; each heating unit is electrically connected with at least two first solder balls which are overlapped with the orthographic projection of the heating unit; the second substrate comprises a second substrate and a plurality of conductive connecting pieces penetrating through the second substrate; each conductive connecting piece is electrically connected with the first solder ball which is overlapped with the orthographic projection of the conductive connecting piece; the conductive connecting piece and the first solder ball are used for supplying power to the heating unit; the packaging layer is located between the first substrate and the second substrate. The packaging layer is used for fixedly connecting the first side of the first substrate and the second substrate. For the thermal test chip with the structure, a heating layer, a rewiring layer, a solder ball and the like do not need to be sequentially manufactured on the substrate, so that the manufacturing process of the thermal test chip can be simplified, the manufacturing period of the thermal test chip can be shortened, and the thermal test efficiency of the chip can be improved.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and particularly to a thermal test chip. Background Art

[0002] With the improvement of chip packaging integration and power density, the thermal management problem of chips has increasingly become a bottleneck restricting their development. Therefore, during the chip R & D stage, a thermal test chip is used to simulate the chip's heat generation to characterize and analyze the chip's package thermal design and thermal characteristics, identify the thermal risks faced by the chip, and formulate optimization strategies to reduce the chip's thermal risks.

[0003] Current thermal test chips simulate the chip's package structure by sequentially fabricating a heating layer, a redistribution layer, and solder balls on a substrate. Among them, the redistribution layer and the solder balls are used to supply power to the heating layer to drive the heating layer to generate heat. However, this will result in a relatively complex manufacturing process and a long manufacturing cycle for the thermal test chip, leading to a low thermal test efficiency of the chip. Utility Model Content

[0004] This application discloses a thermal test chip to simplify the manufacturing process of the thermal test chip, shorten the manufacturing cycle of the thermal test chip, and improve the thermal test efficiency of the chip.

[0005] In a first aspect, this application discloses a thermal test chip, including: a first substrate, the first substrate includes a first substrate and a heating layer and a plurality of first solder balls that are sequentially stacked on a first side of the first substrate. The heating layer includes a plurality of heating units. The orthographic projection of each heating unit on the first substrate overlaps with the orthographic projections of at least two of the first solder balls on the first substrate, and each heating unit is electrically connected to at least two first solder balls whose orthographic projections overlap with it; a second substrate, the second substrate includes a second substrate and a plurality of conductive connectors that penetrate the second substrate; the orthographic projection of each conductive connector on the second substrate overlaps with the orthographic projection of one of the first solder balls on the second substrate, and each conductive connector is electrically connected to the first solder ball whose orthographic projection overlaps with it; the conductive connectors and the first solder balls are used to supply power to the heating units to drive the heating units to generate heat; a packaging layer located between the first substrate and the second substrate, the packaging layer is used to fixedly connect the first side of the first substrate and the second substrate and at least wrap a plurality of first solder balls located on the first side of the first substrate.

[0006] For a thermal test chip with such a structure, the first substrate and the second substrate can be fabricated separately first, and then the first substrate and the second substrate can be fixed by using a packaging layer to form the thermal test chip. By electrically connecting the first solder balls electrically connected to the heating units on the first substrate to the conductive connectors on the second substrate, a power supply path for driving the heating units to generate heat is formed. Thus, it is no longer necessary to sequentially fabricate a heating layer, a redistribution layer, solder balls, etc. on the substrate, which can simplify the manufacturing process of the thermal test chip, shorten the manufacturing cycle of the thermal test chip, and improve the thermal test efficiency of the chip. Moreover, by dividing the heating layer into multiple heating units, different heating units can simulate the heat generation of different chip regions. Thus, based on the temperatures of different heating units, the heat generation deviation between different chip regions can be analyzed to guide the optimization of chip design and risk identification.

[0007] In some embodiments of the present application, the conductive connector at least includes a first conductive layer on one side of the second substrate, a second conductive layer on the opposite side of the second substrate, and a via penetrating the second substrate, and the first conductive layer is electrically connected to the second conductive layer through the via.

[0008] For a thermal test chip with such a structure, when designing the second substrate, only the positions of the multiple conductive connectors on the second substrate need to be designed corresponding to the positions of the multiple first solder balls on the first substrate, and the design compatibility and reusability are relatively good.

[0009] In some embodiments of the present application, the second substrate further includes multiple second solder balls; the multiple second solder balls are located on the side of the second substrate facing away from the first substrate, and the multiple second solder balls are electrically connected to the multiple conductive connectors respectively.

[0010] For a thermal test chip with such a structure, its electrical connection with a printed circuit board can be achieved through multiple second solder balls, so that the printed circuit board can supply power to the thermal test chip, etc., to drive the thermal test chip to perform thermal testing.

[0011] In some embodiments of the present application, the heating unit includes a heating resistance wire, a first pad, and a second pad; the first pad and the second pad are electrically connected to both ends of the heating resistance wire respectively, and the first pad and the second pad are electrically connected to different first solder balls respectively.

[0012] In some embodiments of the present application, the heating resistance wire is bent and arranged in the length direction or the width direction of the first substrate.

[0013] For a thermal test chip with such a structure, a sufficient number of heating resistance wires can be distributed in each heating unit so that the resistance value of the heating resistance wires in each heating unit meets the requirements.

[0014] In some embodiments of the present application, the width of the heating resistance wire is greater than or equal to 100 μm.

[0015] For the thermal test chip with such a structure, the normal operation of the heating resistance wire can be ensured.

[0016] In some embodiments of the present application, the wire pitch of the heating resistance wire is greater than or equal to 100 μm.

[0017] For the thermal test chip with such a structure, the normal operation of the heating resistance wire can be ensured.

[0018] In some embodiments of the present application, the first substrate further includes a plurality of temperature-measuring diodes, the plurality of temperature-measuring diodes are respectively arranged in the plurality of heating units, and the temperature-measuring diodes are used to measure the temperature of the heating units.

[0019] For the thermal test chip with such a structure, the temperature of each heating unit can be accurately obtained in real time, and then the heating analysis can be performed on the chip area corresponding to each heating unit.

[0020] In some embodiments of the present application, the first substrate further includes a third pad, a fourth pad, a fifth pad and a sixth pad; the third pad and the fourth pad are respectively electrically connected to the positive electrode and the negative electrode of the temperature-measuring diode; the fifth pad and the sixth pad are electrically connected to the third pad and the fourth pad respectively, and the fifth pad and the sixth pad are respectively electrically connected to different first solder balls.

[0021] For the thermal test chip with such a structure, the temperature measurement result of the temperature-measuring diode can be output through the first solder ball, the conductive connection member, the third pad, the fourth pad, the fifth pad and the sixth pad.

[0022] In some embodiments of the present application, the temperature-measuring diode is arranged in the middle area of the heating unit, and the heating resistance wire is arranged around the temperature-measuring diode.

[0023] For the thermal test chip with such a structure, the temperature-measuring diode can measure the temperature of the heating unit more accurately. Description of the Drawings

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background art, the following will describe the drawings required to be used in the embodiments of the present application or the background art.

[0025] Figure 1 It is a schematic cross-sectional structure diagram of a current thermal test chip.

[0026] Figure 2 It is a schematic cross-sectional structure diagram of a thermal test chip disclosed in the embodiments of the present application.

[0027] Figure 3 Schematic cross-sectional structure diagram of a first substrate disclosed in an embodiment of the present application.

[0028] Figure 4 Schematic plan structure diagram of a first substrate disclosed in an embodiment of the present application.

[0029] Figure 5 Schematic cross-sectional structure diagram of a second substrate disclosed in an embodiment of the present application.

[0030] Figure 6 Schematic structure diagram of a heating resistance wire with a smaller width disclosed in an embodiment of the present application.

[0031] Figure 7 Schematic structure diagram of a heating resistance wire with a larger width disclosed in an embodiment of the present application.

[0032] Figure 8 Schematic structure diagram of a heating resistance wire with a smaller length disclosed in an embodiment of the present application.

[0033] Figure 9 Schematic cross-sectional structure diagram of another thermal test chip disclosed in an embodiment of the present application.

[0034] Figure 10 Schematic plan structure diagram of another first substrate disclosed in an embodiment of the present application. Detailed implementation manners

[0035] Next, the technical solutions in the embodiments of the present application will be described with reference to the accompanying drawings in the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0036] As Figure 1 shown, Figure 1 is a schematic cross-sectional structure diagram of a current thermal test chip, which includes a substrate 10, a heating layer 11, a redistribution layer 12, solder balls 13, etc. During the process of manufacturing the thermal test chip, it is necessary to sequentially manufacture the heating layer 11, the redistribution layer 12, and the solder balls 13 on the substrate 10. Moreover, the redistribution layer 12 needs to be electrically connected to the heating layer 11 through vias, and the solder balls 13 need to be electrically connected to the redistribution layer 12 through vias and connection lines. However, because the structural design accuracy of the thermal test chip is relatively high, for example, the positions of the vias need to be accurately designed, etc., the manufacturing process of the thermal test chip is relatively complex and the manufacturing cycle is relatively long, resulting in a relatively low thermal test efficiency of the chip.

[0037] Based on this, the present application discloses a thermal test chip, which is fixed by two independent substrates, so as to simplify the manufacturing process of the thermal test chip, shorten the manufacturing cycle of the thermal test chip, and improve the thermal test efficiency of the chip.

[0038] As an optional implementation of the disclosed content of the present application, an embodiment of the present application discloses a thermal test chip, as Figure 2 shown. Figure 2 FIG. is a schematic cross-sectional structure diagram of a thermal test chip disclosed in an embodiment of the present application. The thermal test chip includes a first substrate 21, a second substrate 22, and a packaging layer 23. Among them, the packaging layer 23 can also be referred to as an underfill layer.

[0039] As Figure 2 and Figure 3 shown. Figure 3 FIG. is a schematic cross-sectional structure diagram of a first substrate disclosed in an embodiment of the present application. The first substrate 21 includes a first substrate 210, a heating layer 211, and a plurality of first solder balls 212 that are sequentially stacked on one side of the first substrate 210. Among them, the first substrate 210 can be a silicon substrate. The side of the heating layer 211 facing away from the first substrate 210 may further have a first barrier layer 213, and the first barrier layer 213 is used to protect the heating layer 211.

[0040] As Figure 4 shown. Figure 4 FIG. is a schematic plan view of a first substrate disclosed in an embodiment of the present application. The heating layer 211 includes a plurality of heating units 2110. The orthographic projection of each heating unit 2110 on the first substrate 210 overlaps with the orthographic projections of at least two first solder balls 212 on the first substrate 210, and each heating unit 2110 is electrically connected to at least two first solder balls 212 whose orthographic projections overlap with it. Among them, the orthographic projection of the first solder ball 212 is as Figure 4 shown by the dotted circles in. In addition, the first barrier layer 213 has a plurality of first openings, so that the plurality of first solder balls 212 are respectively electrically connected to the plurality of heating units 2110 through the plurality of first openings.

[0041] It should be noted that Figure 4 only takes 4×4 heating units 2110 as an example for illustration. However, the present application is not limited to this. The number and shape of the heating units 2110 can be set according to test requirements, but it is necessary to ensure that the overall size of all the heating units 2110 is the same as the size of the chip to be tested. Generally, the heating layer 211 includes n×n heating units 2110, where n≥2.

[0042] As Figure 2 and Figure 5 shown. Figure 5Schematic cross-sectional structure diagram of a second substrate disclosed in an embodiment of the present application. The second substrate 22 includes a second substrate 220 and a plurality of conductive connectors 221 penetrating the second substrate 220. The orthographic projection of each conductive connector 221 on the second substrate 220 overlaps with the orthographic projection of a first solder ball 212 on the second substrate 220, and each conductive connector 221 is electrically connected to the first solder ball 212 whose orthographic projection overlaps with it.

[0043] Among them, the conductive connector 221 and the first solder ball 212 are used to supply power to the heating unit 2110 to drive the heating unit 2110 to generate heat, so as to simulate the heat generation of the designed chip. In addition, the diameter of the first solder ball 212 is not less than 0.35 mm to ensure sufficient electrical connection between the heating unit 2110 and the conductive connector 221.

[0044] As Figure 2 shown, the encapsulation layer 23 is located between the first substrate 21 and the second substrate 22. The encapsulation layer 23 is used to fixedly connect the first side of the first substrate 210 and the second substrate 220, so that the second substrate 22 can stably supply power to the first substrate 21. And the encapsulation layer 23 at least wraps a plurality of first solder balls 212 located on the first side of the first substrate 210 to protect the plurality of first solder balls 212 and achieve insulation between the first solder balls 212.

[0045] Because the structure of this thermal test chip is relatively simple, the first substrate 21 and the second substrate 22 can be fabricated separately first, and then the first substrate 21 and the second substrate 22 are fixed by the encapsulation layer 23 to form a thermal test chip. By electrically connecting the first solder balls 212 electrically connected to the heating unit 2110 on the first substrate 21 and the conductive connectors 221 on the second substrate 22, a power supply path for driving the heating unit 2110 to generate heat is formed. Thus, it is not necessary to fabricate a heating layer, a redistribution layer, solder balls, etc. on the substrate in sequence, which can simplify the manufacturing process of the thermal test chip, shorten the manufacturing cycle of the thermal test chip, and improve the thermal test efficiency of the chip.

[0046] Moreover, when designing the second substrate 22, only the positions of the plurality of first solder balls 212 on the first substrate 21 need to be corresponded to design the positions of the plurality of conductive connectors 221 on the second substrate 22, and the design compatibility and reusability are relatively good.

[0047] In addition, by dividing the heating layer 211 into a plurality of heating units 2110, the heat generation of different chip regions can be simulated by different heating units 2110. Furthermore, according to the temperatures of different heating units 2110, the heat generation deviation between different chip regions can be analyzed to guide the optimization of chip design and risk identification.

[0048] In some embodiments of the present application, such as Figure 5As shown, the conductive connection member 221 at least includes a first conductive layer 2201 on one side of the second substrate 220, a second conductive layer 2202 on the opposite side of the second substrate 220, and a via 2203 penetrating the second substrate 220. The first conductive layer 2201 is electrically connected to the second conductive layer 2202 through the via 2203.

[0049] Among them, the first conductive layers 2201 of different conductive connection members 221 are disconnected, and the second conductive layers 2202 of different conductive connection members 221 are disconnected to avoid short - circuiting between different conductive connection members 221. Specifically, the first conductive layer 2201 can be electrically connected to the second conductive layer 2202 through the conductive layer at the inner wall of the via 2203.

[0050] It should be noted that, as Figure 2 shown, the central part of the via 2203 can also be filled with other materials to improve the hardness of the second substrate 22. The other material can be an insulating material, etc. It should also be noted that the second substrate 22 can be a printed circuit board, and the first conductive layer 2201 and the second conductive layer 2202 can be copper layers. Among them, the thickness of the copper layer needs to be greater than or equal to 0.5 oz.

[0051] In some embodiments of the present application, as Figure 5 shown, on the side of the first conductive layer 2201 facing away from the second substrate 220, there can also be a second barrier layer 222. The second barrier layer 222 is used to protect the first conductive layer 2201 and achieve insulation between adjacent first conductive layers 2201. And the second barrier layer 222 has a plurality of second openings. The plurality of second openings are used to respectively expose a plurality of conductive connection members 221, so that a plurality of first solder balls 212 are electrically connected to the plurality of conductive connection members 221 through the plurality of second openings.

[0052] On the side of the second conductive layer 2202 facing away from the second substrate 220, there can also be a third barrier layer 223. The third barrier layer 223 is used to protect the second conductive layer 2202 and achieve insulation between adjacent second conductive layers 2202. And the third barrier layer 223 has a plurality of third openings. The plurality of third openings are used to respectively expose a plurality of conductive connection members 221, so that a plurality of second solder balls 224 are electrically connected to the plurality of conductive connection members 221 through the plurality of third openings.

[0053] In some embodiments of the present application, as Figure 2 shown, the second substrate 22 further includes a plurality of second solder balls 224. The plurality of second solder balls 224 are located on the side of the second substrate 220 facing away from the first substrate 21, and the plurality of second solder balls 224 are electrically connected to the plurality of conductive connection members 221 respectively. The plurality of second solder balls 224 are used to realize the electrical connection between the thermal test chip and the printed circuit board.

[0054] Among them, the printed circuit board is used to supply power to the thermal test chip to drive the thermal test chip to perform thermal testing. Of course, the printed circuit board can also be used to receive temperature data output by the thermal test chip, etc. In addition, the diameter of the second solder ball 224 is not less than 0.35 mm to ensure sufficient electrical connection between the thermal test chip and the printed circuit board.

[0055] Of course, the present application is not limited to this. In some other embodiments, the second substrate 22 can also achieve its electrical connection with the printed circuit board through pads or leads, etc., which will not be elaborated here.

[0056] In some embodiments of the present application, such as Figure 4 shown, the heating unit 2110 includes a heating resistance wire 2110a, a first pad 2110b, and a second pad 2110c. The first pad 2110b and the second pad 2110c are respectively electrically connected to both ends of the heating resistance wire 2110a, and the first pad 2110b and the second pad 2110c are respectively electrically connected to different first solder balls 212. Among them, the heating resistance wire 2110a can be a metal wire, and the material of the metal wire includes but is not limited to copper, tungsten, constantan alloy, etc.

[0057] In some embodiments of the present application, such as Figure 4 shown, the heating resistance wire 2110a is bent and arranged in the length direction or width direction of the first substrate 210, so that sufficient heating resistance wires 2110a are distributed in each heating unit 2110, and the resistance value of the heating resistance wires 2110a in each heating unit 2110 meets the requirements.

[0058] In some embodiments of the present application, such as Figure 6 、 Figure 7 and Figure 8 shown, Figure 6 is a schematic structural diagram of a heating resistance wire with a smaller width disclosed in an embodiment of the present application, Figure 7 is a schematic structural diagram of a heating resistance wire with a larger width disclosed in an embodiment of the present application, Figure 8 is a schematic structural diagram of a heating resistance wire with a smaller length disclosed in an embodiment of the present application. The length and width of the heating resistance wire 2110a can be adjusted according to requirements, and the present application does not limit this, but it is necessary to ensure that the resistance values of the heating resistance wires 2110a of different heating units 2110 are the same.

[0059] In some embodiments of the present application, in order to ensure the normal operation of the heating resistance wire 2110a, it is necessary to ensure that the width of the heating resistance wire 2110a is greater than or equal to 100 μm, and / or the line spacing of the heating resistance wire 2110a is greater than or equal to 100 μm.

[0060] In some embodiments of the present application, such as Figure 9 andFigure 10 As shown Figure 9 FIG. is a schematic cross-sectional structure diagram of another thermal test chip disclosed in an embodiment of the present application Figure 10 FIG. is a schematic plan structure diagram of another first substrate disclosed in an embodiment of the present application. The first substrate 21 further includes a plurality of temperature measuring diodes 214. The plurality of temperature measuring diodes 214 are respectively arranged in a plurality of heating units 2110, and the temperature measuring diodes 214 are used to measure the temperature of the heating units 2110. Based on this, the temperature of each heating unit 2110 can be accurately obtained in real time, and then the heating analysis can be performed on the chip area corresponding to each heating unit 2110.

[0061] In some embodiments of the present application, as Figure 10 shown, the first substrate 21 further includes a third pad 215, a fourth pad 216, a fifth pad 217 and a sixth pad 218. Among them, the third pad 215 and the fourth pad 216 are respectively used for electrically connecting to the positive electrode and the negative electrode of the temperature measuring diode 214. The fifth pad 217 and the sixth pad 218 are electrically connected to the third pad 215 and the fourth pad 216 respectively. For example, the third pad 215 and the fifth pad 217 are electrically connected, and the fourth pad 216 and the sixth pad 218 are electrically connected. And, the fifth pad 217 and the sixth pad 218 are respectively electrically connected to different first solder balls 212, so as to output the temperature measurement result of the temperature measuring diode 214 through the first solder balls 212, the conductive connection member 221, the third pad 215, the fourth pad 216, the fifth pad 217 and the sixth pad 218.

[0062] In some embodiments of the present application, as Figure 10 shown, the temperature measuring diode 214 is arranged in the middle area of the heating unit 2110, and the heating resistance wire 2110a is arranged around the temperature measuring diode 214, so that the temperature measuring diode 214 can measure the temperature of the heating unit 2110 more accurately. Of course, the present application is not limited to this. In some other embodiments, the temperature measuring diode 214 can also be arranged in the edge area of the heating unit 2110, which will not be elaborated here.

[0063] The technical features of the above embodiments can be combined arbitrarily. For the sake of brief description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0064] The above embodiments merely represent several implementation manners of this specification. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the scope of the patented application. It should be noted that for those of ordinary skill in the art, without departing from the concept of this specification, several modifications and improvements can still be made, and these all fall within the protection scope of this specification. Therefore, the protection scope of the patent of this specification shall be subject to the appended claims.

Claims

1. A thermal test chip, characterized in that, include: A first substrate, the first substrate comprising a first substrate and a heating layer and a plurality of first solder balls sequentially stacked on a first side of the first substrate, the heating layer comprising a plurality of heating units, an orthographic projection of each of the heating units on the first substrate overlaps with an orthographic projection of at least two of the first solder balls on the first substrate, and each of the heating units is electrically connected to the at least two first solder balls overlapping with its orthographic projection; A second substrate, the second substrate comprising a second substrate and a plurality of conductive connecting members penetrating the second substrate; The orthographic projection of each of the conductive connecting members on the second substrate overlaps with the orthographic projection of one of the first solder balls on the second substrate, and each of the conductive connecting members is electrically connected to the first solder ball overlapping with its orthographic projection; the conductive connecting members and the first solder balls are used to supply power to the heating unit to drive the heating unit to generate heat; The encapsulation layer is located between the first substrate and the second substrate, and is used to fix the first side of the first substrate and the second substrate and at least wrap a plurality of first solder balls located on the first side of the first substrate.

2. The thermal test chip according to claim 1, characterized in that, The conductive connection member comprises at least a first conductive layer located on one side of the second substrate, a second conductive layer located on the other side of the second substrate, and a via hole penetrating the second substrate; the first conductive layer is electrically connected to the second conductive layer through the via hole.

3. The thermal test chip according to claim 1 or 2, characterized in that, The second substrate further includes a plurality of second solder balls; the plurality of second solder balls are located on a side of the second substrate facing away from the first substrate, and the plurality of second solder balls are electrically connected to the plurality of conductive connecting members respectively.

4. The thermal test chip according to claim 1, characterized in that The heating unit includes a heating resistor, a first solder pad and a second solder pad; the first solder pad and the second solder pad are electrically connected to two ends of the heating resistor, respectively, and the first solder pad and the second solder pad are electrically connected to different first solder balls, respectively.

5. The thermal test chip according to claim 4, characterized in that, The heating resistance wire is bent and arranged in the length direction or the width direction of the first substrate.

6. The thermal test chip according to claim 4 or 5, characterized in that, The width of the heating resistance wire is greater than or equal to 100 μm.

7. The thermal test chip according to claim 4 or 5, characterized in that, The line spacing of the heating resistance wire is greater than or equal to 100 μm.

8. The thermal test chip according to claim 4, characterized in that, The first substrate further includes a plurality of temperature measuring diodes; the plurality of temperature measuring diodes are respectively arranged in the plurality of heating units, and the temperature measuring diodes are used to test the temperature of the heating units.

9. The thermal test chip according to claim 8, characterized in that, The first substrate also includes a third solder pad, a fourth solder pad, a fifth solder pad and a sixth solder pad; the third solder pad and the fourth solder pad are electrically connected to the positive and negative poles of the temperature measuring diode, respectively; the fifth solder pad and the sixth solder pad are electrically connected to the third solder pad and the fourth solder pad, respectively, and the fifth solder pad and the sixth solder pad are electrically connected to different first solder balls, respectively.

10. The thermal test chip according to claim 8, wherein The temperature measuring diode is arranged in the middle area of ​​the heating unit, and the heating resistance wire is arranged around the temperature measuring diode.

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