Transistor packaging structure
By allowing the electrodes of the transistor to penetrate the epitaxial structure and substrate and connect them directly to the circuit board or through conductive devices, the problem of poor thermal efficiency of the existing transistor package structure is solved, and better heat dissipation and stability are achieved.
Patent Information
- Application Number
- CN202422169639.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-04
- Publication Date
- 2025-07-08
- Estimated Expiration
- 2034-09-04
AI Technical Summary
The existing transistor packaging structure has poor thermal efficiency, which affects the heat dissipation and stability of the transistor.
By allowing the first and second electrodes of the transistor to penetrate the epitaxial structure and the substrate, some electrodes are directly connected to the circuit board, and the other part is connected to the circuit board through the conductive device, which enhances heat dissipation using the conductive device as a thermal path.
Without increasing the packaging difficulty, the heat dissipation effect and stability of the transistor are improved.
Smart Images
Figure CN223079121U_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a transistor packaging structure. Background Art
[0002] A transistor is a switching device and is widely used in various electrical appliances.
[0003] Related technologies provide a transistor packaging structure, including: a circuit board, a transistor, and an electrical conducting device; the transistor includes a substrate, an epitaxial structure located on the substrate, a control electrode, a first electrode, and a second electrode connected to the epitaxial structure, the substrate is disposed on the circuit board, and the control electrode, the first electrode, and the second electrode are respectively connected to the circuit board through conducting wires.
[0004] However, although the packaging of the transistor in the above manner has a low packaging difficulty, the thermal efficiency is poor, which is not conducive to the heat dissipation of the transistor and the stability of the transistor. Summary of the Utility Model
[0005] Embodiments of the present disclosure provide a transistor packaging structure that improves heat dissipation with a relatively low packaging difficulty. The technical solution is as follows:
[0006] Embodiments of the present disclosure provide a transistor packaging structure, the transistor packaging structure including: a circuit board, a transistor, and an electrical conducting device; the transistor includes a substrate, an epitaxial structure, a control electrode, a first electrode, and a second electrode; the epitaxial structure and the control electrode are stacked on the substrate in sequence, one end of the first electrode and one end of the second electrode are electrically connected to the epitaxial structure, the other end of the first electrode and the other end of the second electrode penetrate through the epitaxial structure and the substrate; a part of the control electrode, the first electrode, and the second electrode is directly electrically connected to the circuit board, and another part of the control electrode, the first electrode, and the second electrode is electrically connected to the circuit board through the electrical conducting device.
[0007] Optionally, the control electrode is directly electrically connected to the circuit board, and the first electrode and the second electrode are electrically connected to the circuit board through the electrical conducting device.
[0008] Optionally, the electrical conducting device is a conducting wire.
[0009] Optionally, the first electrode and the second electrode are directly electrically connected to the circuit board, and the control electrode is electrically connected to the circuit board through the electrical conducting device.
[0010] Optionally, the electrical conducting device is a conductive clip.
[0011] Optionally, the control electrode is a gate, one of the first electrode and the second electrode is a source electrode, and the other of the first electrode and the second electrode is a drain electrode.
[0012] Optionally, the epitaxial structure is a GaN epitaxial structure.
[0013] Optionally, the GaN epitaxial structure includes a nucleation layer, a buffer layer, and a device layer, and the nucleation layer, the buffer layer, and the device layer are stacked on the surface of the substrate in sequence.
[0014] Optionally, the substrate is a sapphire substrate.
[0015] Optionally, the circuit board is a PCB circuit board.
[0016] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure are as follows:
[0017] In the embodiments of the present disclosure, the first electrode and the second electrode in the transistor penetrate through the epitaxial structure and the substrate, so that some of the control electrode, the first electrode, and the second electrode can be directly connected to the circuit board. Through this direct connection, the heat dissipation of the transistor can be enhanced. The other part of the control electrode, the first electrode, and the second electrode is electrically connected to the circuit board through a current conducting device. The current conducting device provides a good heat dissipation path as a heat conducting device, which is beneficial to the heat dissipation of the transistor and improves the stability of the device. On the other hand, the transistor packaging structure does not increase the packaging difficulty, and improves the heat dissipation under the condition of low packaging difficulty. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0019] Figure 1 is a schematic structural diagram of a transistor packaging structure provided by an embodiment of the present disclosure;
[0020] Figure 2 is a schematic structural diagram of another transistor packaging structure provided by an embodiment of the present disclosure;
[0021] Figure 3 is a schematic structural diagram of a transistor provided by an embodiment of the present disclosure;
[0022] Figure 4 is a flowchart of a manufacturing method of a transistor packaging structure provided by an embodiment of the present disclosure.
[0023] The reference numerals are as follows:
[0024] 100: Circuit board; 200: Transistor; 300: Conductive device;
[0025] 201 Substrate; 202: Epitaxial structure; 203: Control electrode; 204: First electrode; 205: Second electrode; 206: Insulating layer;
[0026] 221: Nucleation layer; 222: Buffer layer; 223: Device layer;
[0027] 2231: Channel layer; 2232: Barrier layer. Detailed implementation manners
[0028] To make the objectives, technical solutions, and advantages of the present disclosure clearer, the following will further describe the embodiments of the present disclosure in detail with reference to the accompanying drawings.
[0029] Figure 1 is a schematic structural diagram of a transistor packaging structure provided by an embodiment of the present disclosure. Figure 2 is a schematic structural diagram of another transistor packaging structure provided by an embodiment of the present disclosure. Refer to Figure 1 and Figure 2 , the transistor packaging structure includes: a circuit board 100, a transistor 200, and a conductive device 300.
[0030] Among them, the transistor 200 includes a substrate 201, an epitaxial structure 202, a control electrode 203, a first electrode 204, and a second electrode 205; the control electrode 203 and the epitaxial structure 202 are stacked on the substrate 201 in sequence, one end of the first electrode 204 and one end of the second electrode 205 are electrically connected to the epitaxial structure 202, and the other end of the first electrode 204 and the other end of the second electrode 205 penetrate through the epitaxial structure 202 and the substrate 201.
[0031] A part of the circuit board 100 among the control electrode 203, the first electrode 204, and the second electrode 205 is directly electrically connected, and another part among the control electrode 203, the first electrode 204, and the second electrode 205 is electrically connected to the circuit board 100 through the conductive device 300.
[0032] In the embodiment of the present disclosure, the first electrode and the second electrode in the transistor penetrate through the epitaxial structure and the substrate, so that some of the control electrode, the first electrode, and the second electrode can be directly connected to the circuit board. Through this direct connection, the heat dissipation of the transistor can be enhanced. Another part of the control electrode, the first electrode, and the second electrode is electrically connected to the circuit board through the conductive device. The conductive device provides a good heat dissipation path as a heat conduction device, which is beneficial to the heat dissipation of the transistor and improves the stability of the device. On the other hand, the transistor packaging structure does not increase the packaging difficulty and improves the heat dissipation under a lower packaging difficulty.
[0033] In an embodiment of the present disclosure, the epitaxial structure 202 is a GaN epitaxial structure.
[0034] Figure 3 It is a schematic structural diagram of a transistor provided by an embodiment of the present disclosure. Refer to Figure 3 , the epitaxial structure 202 may include a nucleation layer 221, a buffer layer 222, and a device layer 223 that are stacked in sequence. The nucleation layer 221, the buffer layer 222, and the device layer 223 are stacked on the surface of the substrate 201 in sequence.
[0035] In an embodiment of the present disclosure, the substrate 201 may be a sapphire substrate.
[0036] In an embodiment of the present disclosure, the nucleation layer 221 may be an AlN nucleation layer.
[0037] In an embodiment of the present disclosure, the buffer layer 222 may be an Al x Ga (1-x) N buffer layer, where x takes a value of 0 or the value range of x is 0.1 to 0.9.
[0038] In an embodiment of the present disclosure, the device layer 223 may include a channel layer 2231 and a barrier layer 2232.
[0039] In an embodiment of the present disclosure, the channel layer 2231 is a GaN channel layer, and the barrier layer 2232 is an AlGaN barrier layer.
[0040] As Figure 3 shown, through holes are formed in part of the substrate 201, the nucleation layer 221, the buffer layer 222, and the channel layer 2231, and the first electrode 204 and the second electrode 205 pass through the above through holes and are connected to the channel layer 2231.
[0041] Among them, the through hole penetrates at least half of the channel layer 2231 but does not completely penetrate the channel layer 2231. For example, it penetrates 4 / 5 of the channel layer.
[0042] As Figure 3 shown, an insulating layer 206 is disposed in the above through hole, and the insulating layer 206 may be any one of a silicon oxide layer, a silicon nitride layer, a gallium nitride layer, an aluminum nitride layer, etc.
[0043] Exemplarily, the insulating layer 206 is a silicon nitride layer.
[0044] Figure 3 The transistor shown is a depletion-mode gallium nitride-based transistor, and the transistor may also be an enhancement-mode gallium nitride-based transistor. In this case, the transistor further includes a P-type layer disposed between the control electrode and the device layer.
[0045] As Figure 1As shown, in a possible implementation, the control electrode 203 is directly electrically connected to the circuit board 100, and the first electrode 204 and the second electrode 205 are electrically connected to the circuit board 100 through a current conducting device 300.
[0046] In this implementation, the control electrode 203 is directly connected to the circuit board 100, enabling a large-area direct contact with the circuit board, which is beneficial to the heat dissipation of the transistor.
[0047] Among them, the current conducting device 300 is a conducting wire. In the case where the control electrode 203 achieves large-area contact heat dissipation, the first electrode 204 and the second electrode 205 only need to be connected by a wire to meet the heat dissipation requirements, and the implementation is simple.
[0048] Exemplarily, the conducting wire can be a copper wire, which has excellent electrical conductivity and chemical stability, good heat dissipation performance, and is easy to process and weld.
[0049] As Figure 2 shown, in another possible implementation, the first electrode 204 and the second electrode 205 are directly electrically connected to the circuit board 100, and the control electrode 203 is electrically connected to the circuit board 100 through the current conducting device 300.
[0050] In this implementation, the first electrode 204 and the second electrode 205 are both directly connected to the circuit board 100, enabling the two electrodes to directly contact the circuit board, which is beneficial to the heat dissipation of the transistor.
[0051] Among them, the current conducting device 300 is a conductive clip. In the case where the first electrode 204 and the second electrode 205 are in contact with the circuit board for heat dissipation, connecting the control electrode and the circuit board through the conductive clip can enhance the heat dissipation path of the transistor and increase the overall heat dissipation effect.
[0052] Exemplarily, the conductive clip can be a copper clip, which has excellent electrical conductivity and thermal conductivity, good heat conduction effect, and is beneficial to the heat dissipation of the epitaxial structure.
[0053] In the embodiments of the present disclosure, the circuit board 100 can be a Printed Circuit Board (PCB).
[0054] In the embodiments of the present disclosure, the control electrode 203 is a gate electrode, one of the first electrode 204 and the second electrode 205 is a source electrode, and the other of the first electrode 204 and the second electrode 205 is a drain electrode.
[0055] Next, taking the depletion-mode gallium nitride-based transistor as an example, an exemplary description will be given of the manufacturing method of the transistor packaging structure:
[0056] Figure 4It is a flowchart of a method for manufacturing a transistor packaging structure provided by an embodiment of the present disclosure. Refer to Figure 4 , the method steps include:
[0057] S11. Fabricate a nucleation layer on a substrate.
[0058] In the embodiment of the present disclosure, the substrate may be a sapphire substrate.
[0059] In the embodiment of the present disclosure, the nucleation layer may be an AlN nucleation layer.
[0060] In the embodiment of the present disclosure, the growth of the above semiconductor layer may be achieved by using a Veeco K465i or C4 or RB metal organic chemical vapor deposition (MOCVD) device or an AIXTRON metal organic chemical vapor deposition device. High-purity H2 (hydrogen) or high-purity N2 (nitrogen) or a mixed gas of high-purity H2 and high-purity N2 is used as the carrier gas, high-purity NH3 is used as the N source, trimethylgallium (TMGa) and triethylgallium (TEGa) are used as the gallium sources, trimethylindium (TMIn) is used as the indium source, silane (SiH4) is used as the N-type dopant, trimethylaluminum (TMAl) is used as the aluminum source, and cyclopentadienylmagnesium (CP2Mg) is used as the P-type dopant.
[0061] S12. Fabricate a buffer layer on the nucleation layer.
[0062] Among them, the buffer layer may be an Al x Ga (1-x) N buffer layer, where x takes a value of 0 or the value range of x is 0.1 to 0.9.
[0063] S13. Fabricate a device layer on the buffer layer.
[0064] In the embodiment of the present disclosure, the device layer may include a channel layer and a barrier layer.
[0065] In the embodiment of the present disclosure, the channel layer is a GaN channel layer, and the barrier layer is an AlGaN barrier layer.
[0066] In one example, step S13 may include:
[0067] The first step is to fabricate a channel layer on the buffer layer.
[0068] The second step is to fabricate a barrier layer on the channel layer.
[0069] S14. Fabricate an electrode structure, and the electrode structure includes a control electrode, a first electrode, and a second electrode.
[0070] In an embodiment of the present disclosure, the control electrode is the gate, one of the first electrode and the second electrode is the source, and the other of the first electrode and the second electrode is the drain.
[0071] In one example, step S14 may include:
[0072] First step, fabricate a control electrode on the device layer.
[0073] Second step, process the substrate, the nucleation layer and the buffer layer using a patterning technique to form a first through hole and a second through hole.
[0074] Wherein, the first through hole penetrates through the substrate, the nucleation layer and the buffer layer and communicates with the channel layer, and the second through hole penetrates through the substrate, the nucleation layer and the buffer layer and communicates with the channel layer.
[0075] Third step, form an insulating layer on the sidewall of the through hole.
[0076] Wherein, the insulating layer can be any one of a silicon oxide layer, a silicon nitride layer, a gallium nitride layer, an aluminum nitride layer, etc.
[0077] Exemplarily, the insulating layer is a silicon nitride layer.
[0078] Fourth step, fabricate the first electrode and the second electrode.
[0079] In an embodiment of the present disclosure, the first electrode is located in the first through hole, one end is connected to the channel layer, and the other end extends out of the substrate. The second electrode is located in the second through hole, one end is connected to the channel layer, and the other end extends out of the substrate.
[0080] S15. Package the transistor on a circuit board.
[0081] In one example, step S15 may include:
[0082] Directly electrically connect the control electrode of the transistor to the circuit board;
[0083] Use electrical conductive devices to connect the first electrode to the circuit board and the second electrode to the circuit board respectively.
[0084] In this example, the electrical conductive device is an electrical conductive wire. When the control electrode realizes large-area contact heat dissipation, the first electrode and the second electrode only need to be connected by a wire to meet the heat dissipation requirement, and the implementation is simple.
[0085] Exemplarily, the electrical conductive wire can be a copper wire. The copper wire has excellent electrical conductivity and chemical stability, good heat dissipation performance, and is easy to process and weld.
[0086] In another example, step S15 may include:
[0087] Directly electrically connect the first electrode and the second electrode of the transistor to the circuit board;
[0088] A conductive device is used to connect the control electrode to the circuit board.
[0089] In this example, the conductive device is a conductive clip. When the first electrode and the second electrode are in contact with the circuit board for heat dissipation, connecting the control electrode and the circuit board through the conductive clip can enhance the heat dissipation path of the transistor and increase the overall heat dissipation effect.
[0090] Exemplarily, the conductive clip can be a copper clip. The copper clip has excellent electrical conductivity and thermal conductivity, and has a good heat dissipation effect, which is beneficial to the heat dissipation of the epitaxial structure.
[0091] The above are only optional embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present disclosure shall be included within the protection scope of the present disclosure.
Claims
1. A transistor packaging structure, characterized in that, The transistor packaging structure includes: a circuit board (100), a transistor (200), and an electrical conductor device (300); The transistor (200) includes a substrate (201), an epitaxial structure (202), a control electrode (203), a first electrode (204), and a second electrode (205); the epitaxial structure (202) and the control electrode (203) are sequentially stacked on the substrate (201), one end of the first electrode (204) and one end of the second electrode (205) are electrically connected to the epitaxial structure (202), and the other end of the first electrode (204) and the other end of the second electrode (205) penetrate through the epitaxial structure (202) and the substrate (201); A part of the control electrode (203), the first electrode (204), and the second electrode (205) is directly electrically connected to the circuit board (100), and another part of the control electrode (203), the first electrode (204), and the second electrode (205) is electrically connected to the circuit board (100) through the electrical conductor device (300).
2. The transistor package structure according to claim 1, wherein, The control electrode (203) is directly electrically connected to the circuit board (100), and the first electrode (204) and the second electrode (205) are electrically connected to the circuit board (100) through the electrical conductor device (300).
3. The transistor package structure according to claim 2, wherein, The electrical conductor device (300) is a conducting wire.
4. The transistor package structure according to claim 1, wherein The first electrode (204) and the second electrode (205) are directly electrically connected to the circuit board (100), and the control electrode (203) is electrically connected to the circuit board (100) through the electrical conductor device (300).
5. The transistor package structure according to claim 4, wherein, The electrical conductor device (300) is a conductive clip.
6. The transistor packaging structure according to any one of claims 1 to 5, characterized in that, The control electrode (203) is a gate electrode, one of the first electrode (204) and the second electrode (205) is a source electrode, and the other of the first electrode (204) and the second electrode (205) is a drain electrode.
7. The transistor package structure according to any one of claims 1 to 5, characterized in that, The epitaxial structure (202) is a GaN epitaxial structure.
8. The transistor packaging structure according to claim 7, wherein, The GaN epitaxial structure (202) includes a nucleation layer, a buffer layer, and a device layer, and the nucleation layer, the buffer layer, and the device layer are sequentially stacked on the surface of the substrate (201).
9. The transistor package structure according to any one of claims 1 to 5, characterized in that, The substrate (201) is a sapphire substrate.
10. The transistor package structure according to any one of claims 1 to 5, characterized in that, The circuit board (100) is a PCB circuit board.