Internet of Things terminal circuit board based on RISC-V architecture

Abstract

The utility model provides an internet of things terminal circuit board based on RISC-V. The internet of things terminal circuit board comprises a substrate, the substrate is provided with a main control module, a 4G network communication module, a 485 communication interface module and a CAN communication interface module, the main control module comprises a main control chip and other components, the main control chip adopts a CH32V208 chip, and the CAN communication interface module is connected with the 4G network communication module. The CH32V208 chip is a wireless microcontroller CH32V208RBT6 designed based on 32-bit RISC-V, the main control chip is connected with a 4G network through the 4G network communication module, the main control chip is connected with an RS485 bus through the 485 communication interface module, and the main control chip is connected with a CAN bus through the CAN communication interface module; compared with the prior art, the utility model has the following beneficial effects: a plurality of serial ports are externally expanded on the basis of a relatively lightweight RISC-V architecture, that is, the utility model is provided with a plurality of communication interfaces such as USART, RS485, CAN and the like, supports a plurality of communication protocols and rates, and is convenient for efficient communication with different devices.

Description

Technical Field

[0001] The utility model relates to the technical field of Internet of Things terminal circuit boards, in particular to an Internet of Things terminal circuit board based on the RISC-V architecture. Background Art

[0002] The Internet of Things refers to the use of various information sensors, radio frequency identification technologies, global positioning systems, infrared sensors, laser scanners and other devices and technologies to collect in real time any objects or processes that need to be monitored, connected and interacted with, collect various required information such as their sound, light, heat, electricity, mechanics, chemistry, biology, location, etc., and through various possible network accesses, realize the ubiquitous connection of things to things and things to people, and realize the intelligent perception, identification and management of items and processes.

[0003] The RISC-V architecture processor has emerged in recent years and has become a research hotspot in academia and industry. In the design of hardware architecture, the verification process often takes years as a cycle, which is obviously too long for iterative improvement and feedback loops. For researchers, it is extremely crucial to be able to evaluate and iterate quickly as early as possible. The RISC-V architecture significantly shortens this cycle through a Chisel-based design method, making the iteration and verification of hardware design extremely rapid; when the hardware performance can be evaluated more quickly, researchers can optimize it faster, thus approaching the constantly changing performance boundary earlier. Compared with architectures such as ARM, the design of the RISC-V architecture is extremely simple, and its performance loss is less than 1%, fully demonstrating its high efficiency and competitiveness; although the processors developed based on RISC-V have lower performance than the high-performance processors of mobile phones and PCs, their microcontrollers applied to sensing devices have a low coupling degree with the ecological environment, a more streamlined instruction set, lower power consumption, and can better meet various heterogeneous and customized application scenarios in the Internet of Things; given the great potential and broad prospects shown by the RISC-V processor, but the development of the RISC-V processor is still in its infancy, and there are still many imperfections in its peripheral support, which cannot meet the diverse communication needs of communication between things and between people and things in the Internet of Things. Summary of the Utility Model

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present utility model is to provide an Internet of Things terminal circuit board based on the RISC-V architecture, which is used to solve the problem that there are still many imperfections in the peripheral support of the RISC-V processor in the prior art and cannot meet the diverse communication needs of communication between things and between people and things in the Internet of Things.

[0005] To achieve the above-mentioned purpose and other related purposes, the present utility model provides the following technical solutions:

[0006] An Internet of Things terminal circuit board based on the RISC-V architecture, including a substrate, on which a main control module, a 4G network communication module, a 485 communication interface module, and a CAN communication interface module are provided. The main control module is respectively connected to the 4G network communication module, the 485 communication interface module, and the CAN communication interface module. Among them, the main control module includes a main control chip and other components. The main control chip uses a CH32V208 chip, and the CH32V208 chip is a wireless microcontroller CH32V208RBT6 designed based on 32-bit RISC-V. The main control chip is connected to the 4G network through the 4G network communication module, the main control chip is connected to the RS485 bus through the 485 communication interface module, and the main control chip is connected to the CAN bus through the CAN communication interface module.

[0007] In an embodiment of the present invention, the 4G network communication module includes a 4G communication chip and other components. The 4G communication chip uses a WH-GM800TF-8-N41 chip, and four of the control terminals of the 4G communication chip are all connected to the main control module.

[0008] In an embodiment of the present invention, the 485 communication interface module includes a first 485 communication chip, a second 485 communication chip, and other components. The first 485 communication chip uses a PI131U31 chip, and the second 485 communication chip uses an SP3485 chip. Two of the control terminals of the first 485 communication chip are all connected to the main control module, and two of the control terminals of the first 485 communication chip are all connected to the second 485 communication chip.

[0009] In an embodiment of the present invention, the CAN communication interface module includes a first CAN communication chip, a second CAN communication chip, and other components. The first CAN communication chip uses a PI121M31 chip, and the second CAN communication chip uses a TJA1050 chip. Two of the control terminals of the first CAN communication chip are all connected to the main control module, and two of the control terminals of the first CAN communication chip are all connected to the second CAN communication chip.

[0010] In an embodiment of the present invention, the CAN communication interface module includes a first CAN communication chip, a second CAN communication chip, and other components. The first CAN communication chip uses a PI121M31 chip, and the second CAN communication chip uses a TJA1050 chip. Two of the control terminals of the first CAN communication chip are all connected to the main control module, and two of the control terminals of the first CAN communication chip are all connected to the second CAN communication chip.

[0011] In an embodiment of the present utility model, a power supply module for supplying power to each module is further provided on the substrate. The power supply module includes a first power conversion chip, a second power conversion chip and other components. The first power conversion chip uses a TPS54561 chip, and the second power conversion chip uses an XC6210B332MR chip.

[0012] As described above, a circuit board of an Internet of Things terminal based on the RISC-V architecture of the present utility model has the following beneficial effects: The present utility model is designed based on the RISC-V architecture. The open-source characteristic of the RISC-V processor enables designers to freely design the processor and software according to the needs of specific applications without being restricted by proprietary architectures and licensing fees, facilitating the breakthrough of chip blockades. Therefore, the present utility model externally expands multiple serial ports based on the relatively lightweight RISC-V architecture, that is, the present utility model has multiple communication interfaces such as USART, RS485, and CAN, supports multiple communication protocols and rates, and is convenient for efficient communication with different devices. The industrial data collected by the peripherals is interacted and aggregated through the expanded communication devices, which is applicable to information sharing, analysis and diagnosis in the industrial Internet of Things scenario and facilitates timely response. Description of the Drawings

[0013] Figure 1 It shows the overall structural block diagram of the circuit board of the Internet of Things terminal based on the RISC-V architecture disclosed in the embodiment of the present utility model;

[0014] Figure 2 It shows the overall structural block diagram of the circuit board of the Internet of Things terminal based on the RISC-V architecture disclosed in the embodiment of the present utility model, including various chip models;

[0015] Figure 3 It shows the circuit schematic diagram of the main control module in the circuit board of the Internet of Things terminal based on the RISC-V architecture disclosed in the embodiment of the present utility model;

[0016] Figure 4 It shows the circuit schematic diagram of the 4G network communication module in the circuit board of the Internet of Things terminal based on the RISC-V architecture disclosed in the embodiment of the present utility model;

[0017] Figure 5 It shows the circuit schematic diagram of the 485 communication interface module in the circuit board of the Internet of Things terminal based on the RISC-V architecture disclosed in the embodiment of the present utility model;

[0018] Figure 6 It shows the circuit schematic diagram of the CAN communication interface module in the circuit board of the Internet of Things terminal based on the RISC-V architecture disclosed in the embodiment of the present utility model;

[0019] Figure 7 It shows the circuit schematic diagram of the power supply module in the Internet of Things terminal circuit board based on the RISC-V architecture disclosed in the embodiments of the present invention. Specific implementation manners

[0020] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0021] Please refer to Figure 1 , the present invention provides an Internet of Things terminal circuit board based on the RISC-V architecture, including a substrate, on which a main control module, a 4G network communication module, a 485 communication interface module, a CAN communication interface module, and a power supply module are provided.

[0022] Please refer to Figure 3 , the main control module includes a main control chip and other components. In this embodiment, the main control chip used is the CH32V208 chip. The CH32V208 chip is a wireless microcontroller CH32V208RBT6 designed based on 32-bit RISC-V. Hereinafter, the main control chip U1 is selected as an example for illustration;

[0023] The main control chip U1 is integrated with a Bluetooth communication module and an Ethernet interface module, and the sixteenth pin, seventeenth pin, fifty-eighth pin, and fifty-ninth pin of the main control chip U1 are four of its control terminals. The sixteenth pin, seventeenth pin, fifty-eighth pin, and fifty-ninth pin of the main control chip U1 are all connected to the 4G network communication module. The twenty-ninth pin and thirtieth pin of the main control chip U1 are two of its control terminals. The twenty-ninth pin and thirtieth pin of the main control chip U1 are all connected to the 485 communication interface module. The forty-fourth pin and forty-fifth pin of the main control chip U1 are two of its control terminals. The forty-fourth pin and forty-fifth pin of the main control chip U1 are all connected to the CAN communication interface module;

[0024] Among them, the main control chip U1 in this embodiment adopts Qinheng's CH32V208 chip. The CH32V208 chip is an industrial-grade general-purpose microcontroller based on the 32-bit RISC-V design of Qingke. The whole series of products adds hardware stack area, fast interrupt entry and other designs, which greatly improves the interrupt response speed compared with the standard; the CH32V208 chip is equipped with a V4C core, which not only increases the memory protection function, but also reduces the hardware division cycle, and supports 144MHz main frequency zero wait operation in product functions. This series of products integrates 2Mbps low-power Bluetooth BLE communication module, 10M Ethernet MAC+PHY module, USB2.0 full-speed device + host / device interface, CAN controller, etc.; on the circuit board, the VCC_3V3 power supply is generated by the switching power supply, that is, the power module, to power the CH32V208 processor;

[0025] There is also a first crystal oscillator Y1 which is a 32.768k clock source, serving as an external low-frequency oscillator (LSE) for the processor; the second crystal oscillator Y2 is a 32MHz clock source generated by an X3225 passive crystal oscillator, serving as an external high-frequency oscillator (HSE) for the processor; the button SW1 is connected to the eighth pin (nRST) of the main control chip U1, and is a reset button; the button SW2 is connected to the sixtieth pin (BOOT0) of the main control chip U1, and is a start control button; the first connector J3 is connected to the forty-second pin (DBG_TX) and the forty-third pin (DBG_RX) of the main control chip U1.

[0026] See also Figure 4 , the 4G network communication module includes a 4G communication chip. In this embodiment, the 4G communication chip is a WH-GM800TF-8-N41 chip. The 4G communication chip includes a first 4G communication sub-chip and a second 4G communication sub-chip. The first 4G communication sub-chip U10A and the second 4G communication sub-chip U10B are selected as examples for explanation;

[0027] The seventeenth pin and the eighteenth pin of the first 4G communication sub-chip U10A are two control terminals, and the seventeenth pin and the eighteenth pin of the first 4G communication sub-chip U10A are both connected to the main control module, and the fifty-ninth pin and the sixtieth pin of the second 4G communication sub-chip U10B are two control terminals, and the fifty-ninth pin and the sixtieth pin of the second 4G communication sub-chip U10B are both connected to the main control module;

[0028] Among them, the 4G communication chip in this embodiment uses the WH-GM800TF-8-N41 chip, which is connected to the RISCV processor, that is, the main control chip U1, through the USB interface and the UART interface. The forty-second and forty-third pins (VBAT) of the first 4G communication sub-chip U10A are connected to VCC_3V8 to provide power for the 4G network communication module. The seventh pin (PWR_ON) of the first 4G communication sub-chip U10A is used to control the power-on of the 4G network communication module. The USB interface provided by the 4G network communication module is a standard USB2.0 interface, and this USB interface and the driver can map a virtual serial port on the PC. The serial port of the 4G network communication module is in the 1.8V power supply domain, and the maximum input limit voltage of the 1.8V voltage IO port cannot exceed 1.8V. The USIM pin of the 4G network communication module is connected to the SIM card holder, and the module provides a SIM card interface that complies with the ISO 7816-3 standard and can automatically identify 3.0V and 1.8V SIM cards. Also in this embodiment, after the 4G network communication module is started, the RISCV processor, that is, the main control chip U1, interacts with the 4G communication module through AT commands for SOCKET connection and data sending and receiving functions.

[0029] Please refer to Figure 5 , the 485 communication interface module includes a first 485 communication chip, a second 485 communication chip and other components. In this embodiment, the first 485 communication chip uses the PI131U31 chip, and the second 485 communication chip uses the SP3485 chip. Here, the first 485 communication chip U4 and the second 485 communication chip U5 are selected as examples for explanation;

[0030] The fourth and fifth pins of the first 485 communication chip U4 are two of its control terminals. Both the fourth and fifth pins of the first 485 communication chip U4 are connected to the main control module. The twelfth and thirteenth pins of the first 485 communication chip U4 are two of its control terminals. Both the twelfth and thirteenth pins of the first 485 communication chip U4 are connected to the second 485 communication chip U5. Among them, in this embodiment, the 485 transceiver module uses a PI131U31 chip and an SP3485 chip. The PI131U31 chip is an enhanced ESD dual-channel digital isolator. The first pin (VDD1) of the PI131U31 chip is connected to VCC_3V3. The SP3485 chip is a +3.3V low-power half-duplex transceiver that conforms to the RS-485 and RS-422 serial protocols. The eighth pin (VCC) of the SP3485 chip is connected to V50_ISO, and V50_ISO is provided by B0505S-1WR2. The B0505S-1WR2 chip is a DC-DC isolated power module that realizes 5V to 5V conversion. Also, the differential signals of the sixth pin (A) and the seventh pin (B) of the SP3485 chip are connected to 485CH1_A and 485CH1_B of the external interface.

[0031] Please refer to Figure 6 , the CAN communication interface module includes a first CAN communication chip, a second CAN communication chip, and other components. In this embodiment, the first CAN communication chip uses a PI121M31 chip, and the second CAN communication chip uses a TJA1050 chip. Here, the first CAN communication chip U6 and the second CAN communication chip U7 are selected as examples for illustration;

[0032] The second and third pins of the first CAN communication chip U6 are two of its control terminals. Both the second and third pins of the first CAN communication chip U6 are connected to the main control module. The sixth and seventh pins of the first CAN communication chip U6 are two of its control terminals. Both the sixth and seventh pins of the first CAN communication chip U6 are connected to the second CAN communication chip U7. Among them, in this embodiment, the CAN transceiver module uses PI121M31 chip and TJA1050 chip, and is connected to the CAN controller ports (CAN_TX and CAN_RX) integrated in the CH32V208RBT6 chip, which is the main control chip U1, and then connects to the CAN bus. The first pin (VDD1) and the eighth pin (VDD2) of the PI121M31 chip are the power supply voltage inputs on both sides of the isolator respectively. The second pin (VIA) and the sixth pin (VIB) of the PI121M31 chip are the logic inputs A and B respectively. The seventh pin (VOA) and the third pin (VOB) of the PI121M31 chip are the logic outputs A and B respectively. The fourth pin (GND1) and the fifth pin (GND2) of the PI121M31 chip are the ground wires on both sides of the isolator respectively. The first pin (TXD) of the TJA1050 chip represents the transmit data pin of the CAN bus. The fourth pin (RXD) of the TJA1050 chip represents the receive data pin of the CAN bus. The fifth pin (VREF) of the TJA1050 chip is the reference voltage pin for CAN bus level shift. The seventh pin (CANH) and the sixth pin (CANL) of the TJA1050 chip are the high-level and low-level signal lines of the CAN bus respectively. Also, the TJA1050 chip is used to send and receive data on the CAN bus, while the PI121M31 chip is used to isolate the transmit and receive paths of the TJA1050 to protect the microcontroller or other CAN bus nodes from potential electrical interference or faults.

[0033] Please refer to Figure 7 , the power supply module includes a first power conversion chip, a second power conversion chip and other components. In this embodiment, the first power conversion chip uses TPS54561 chip, and the second power conversion chip uses XC6210B332MR chip. Here, the first power conversion chip U11 and the second power conversion chip U13 are selected as examples for illustration. Among them, the power supply module in this embodiment includes a 9 - 36V input to 5V output module (TPS54561 chip), a 5V to 3V3 module (XC6210B332MR chip) and a second connector J1. Figure 7The second pin (VIN) of the TPS54561 chip is supplied with a 12V power supply externally connected by the second connector J1. It is output through the ninth pin (SW) and the sixth pin (FB) of the TPS54561 chip, converted via the inductor L2, resistors R47 and R50, and the filtering function is achieved by capacitors C44 and C45 to ensure normal power signal ripple. Finally, VCC_5V0 is output to the first pin (VIN) of the XC6210B332MR chip. VCC_5V0 is provided by the TPS54561 chip, and the filtering is achieved by capacitors C50 and C51. A 3.3V voltage is output through the fifth pin (VOUT) of the XC6210B332MR chip. Finally, VCC_3V3 is input to the corresponding pins of the CH32V208RBT6 chip, which is the main control chip U1.

[0034] Specifically, the present utility model takes the wireless microcontroller CH32V208RBT6 based on 32-bit RISC-V design as the core, and arranges a Bluetooth communication module, a 4G network communication module, an Ethernet interface module, a 485 communication interface module, a CAN communication interface module, etc. to achieve diversified data communication methods; the core part is the CH32V208RBT6 microcontroller, which is responsible for the logic control and data processing of the entire circuit board. The microcontroller is connected to the CAN bus through the PI121M31 and TJA1050 transceivers; connected to the RS485 bus through the PI131U31 and SP3485 signal processing chips; the CH32V208RBT6 chip integrates a Bluetooth BLE communication module, a 10M Ethernet module, and is connected to the 4G network through the WH-GM800TF-8-N41 chip; in terms of power supply, the XC6210B332MR chip and the TPS54561 chip are adopted to provide 3.3V and 5V power supplies to ensure the stability and reliability of the power supply. For details, please refer to Figure 2 。

[0035] In summary, the present utility model is designed based on the RISC-V architecture. The open-source characteristic of the RISC-V processor enables designers to freely design the processor and software according to the requirements of specific applications, without being restricted by proprietary architectures and licensing fees, facilitating the breakthrough of chip blockade. Therefore, the present utility model extends multiple serial ports externally based on the relatively lightweight RISC-V architecture, that is, the present utility model has multiple communication interfaces such as USART, RS485, and CAN, supports multiple communication protocols and rates, and is convenient for efficient communication with different devices. The industrial data collected by the peripherals is interacted and aggregated through the extended communication devices, which is applicable to information sharing, analysis, and diagnosis in the industrial Internet of Things scenario and facilitates timely response. In addition, the processor designed with the RISC-V architecture is simple in design and has a streamlined instruction set, which gives them an advantage in power consumption control. In the Internet of Things, devices usually need to run for a long time with low power consumption to achieve long-term autonomous operation.

[0036] The above embodiments are only illustrative of the principles and effects of the present utility model and are not intended to limit the present utility model. All equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present utility model should still be covered by the claims of the present utility model.

Claims

1. An Internet of Things terminal circuit board based on the RISC-V architecture, comprising a substrate, characterized in that: A main control module, a 4G network communication module, a 485 communication interface module, and a CAN communication interface module are provided on the substrate. The main control module is respectively connected to the 4G network communication module, the 485 communication interface module, and the CAN communication interface module. Among them, the main control module includes a main control chip and other components. The main control chip uses a CH32V208 chip, and the CH32V208 chip is a wireless microcontroller CH32V208RBT6 based on 32-bit RISC-V. The main control chip is connected to the 4G network through the 4G network communication module, the main control chip is connected to the RS485 bus through the 485 communication interface module, and the main control chip is connected to the CAN bus through the CAN communication interface module.

2. The Internet of Things terminal circuit board based on the RISC-V architecture according to claim 1, wherein: A Bluetooth communication module and an Ethernet interface module are integrated on the main control chip. Four of the control terminals of the main control chip are connected to the 4G network communication module, two of the control terminals of the main control chip are connected to the 485 communication interface module, and two of the control terminals of the main control chip are connected to the CAN communication interface module.

3. The Internet of Things terminal circuit board based on the RISC-V architecture according to claim 1, characterized in that: The 4G network communication module includes a 4G communication chip and other components. The 4G communication chip uses a WH-GM800TF-8-N41 chip, and four of the control terminals of the 4G communication chip are connected to the main control module.

4. The Internet of Things terminal circuit board based on the RISC-V architecture according to claim 1, characterized in that: The 485 communication interface module includes a first 485 communication chip, a second 485 communication chip, and other components. The first 485 communication chip uses a PI131U31 chip, and the second 485 communication chip uses an SP3485 chip. Two of the control terminals of the first 485 communication chip are connected to the main control module, and two of the control terminals of the first 485 communication chip are connected to the second 485 communication chip.

5. The Internet of Things terminal circuit board based on the RISC-V architecture according to claim 1, wherein: The CAN communication interface module includes a first CAN communication chip, a second CAN communication chip, and other components. The first CAN communication chip uses a PI121M31 chip, and the second CAN communication chip uses a TJA1050 chip. Two of the control terminals of the first CAN communication chip are connected to the main control module, and two of the control terminals of the first CAN communication chip are connected to the second CAN communication chip.

6. The Internet of Things terminal circuit board based on the RISC-V architecture according to claim 1, wherein: A power supply module for supplying power to each module is also provided on the substrate. The power supply module includes a first power conversion chip, a second power conversion chip, and other components. The first power conversion chip uses a TPS54561 chip, and the second power conversion chip uses an XC6210B332MR chip.

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