Silicon carbide VDMOS resistant to drain voltage impact
By adopting the trench gate structure, protective layer and masking layer design in SiC VDMOS, the damage caused by drain voltage shock is solved, and the device performance with low on-resistance and high switching speed is achieved.
Patent Information
- Application Number
- CN202421839614.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-31
- Publication Date
- 2025-07-08
- Estimated Expiration
- 2034-07-31
AI Technical Summary
Silicon carbide VDMOS devices are susceptible to irrecoverable damage caused by drain voltage impact, and it is urgent to improve the voltage impact resistance of drain source and drain gate to improve device reliability and switching speed.
A trench gate structure is adopted to build a protective layer and a masking layer. The conductive layer with high doping concentration is combined with the drift layer to form an electric field buffer and capacitance shield, reduce the gate leakage capacitance and increase the switching speed.
It improves the device's drain voltage impact resistance, reduces the on-resistance and gate leakage capacitance, and enhances the device's switching speed and reliability.
Smart Images
Figure CN223080381U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a silicon carbide VDMOS resistant to drain voltage impact. Background Art
[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices and has wide applications in fields such as electric vehicles, aerospace, and power conversion. With the development of the structure and manufacturing process of silicon carbide VDMOS, the on-resistance of the device is reduced and the reliability is improved. For trench-gate devices, they are prone to occasional voltage impacts on the drain and are likely to cause irreversible damage. Therefore, it is urgent to improve the voltage impact resistance of the drain-source and drain-gate to effectively improve the reliability of the device. Content of the Utility Model
[0003] The technical problem to be solved by the utility model is to provide a silicon carbide VDMOS resistant to drain voltage impact, which can improve the drain voltage impact resistance of the device while increasing the switching speed.
[0004] The utility model is realized as follows: A silicon carbide VDMOS resistant to drain voltage impact, comprising:
[0005] A silicon carbide substrate;
[0006] A drift layer, the lower side of the drift layer is connected to the upper side of the silicon carbide substrate; a conductive layer is provided in the drift layer, a groove is provided in the drift layer, and a masking layer is provided at the bottom of the groove; a protective layer is provided on the drift layer;
[0007] A well region, the lower side of the well region is respectively connected to the drift layer and the protective layer;
[0008] A P-type source region, the lower side of the P-type source region is connected to the well region;
[0009] An N-type source region, the lower side of the N-type source region is connected to the well region, and the outer side of the N-type source region is connected to the inner side of the P-type source region;
[0010] A gate dielectric layer, the lower part of the gate dielectric layer is provided in the groove, and the lower side of the gate dielectric layer is connected to the masking layer; the outer side of the gate dielectric layer is respectively connected to the inner side of the well region and the inner side of the N-type source region; a trench is provided in the gate dielectric layer;
[0011] A gate metal layer, the gate metal layer is provided in the trench;
[0012] A source metal layer, the source metal layer is respectively connected to the P-type source region and the N-type source region;
[0013] And a drain metal layer, the drain metal layer is connected to the lower side of the silicon carbide substrate.
[0014] The advantages of the present utility model are as follows:
[0015] First, the present utility model adopts a trench gate structure, and the device has the characteristic of low on-resistance.
[0016] Second, the present utility model constructs a protective layer under the well region. When a large voltage impact occurs at the drain, the electric field is quickly buffered in the P-type protective layer, without affecting the source region and well region structures of the device, and improving the voltage impact of the drain on the source of the device.
[0017] Third, a masking layer and a conductive layer are constructed directly under the gate metal layer of the present utility model. The masking layer has a high doping concentration, and the conductive layer is N-type highly doped. When the electric field diffuses in the N-type region, the diffusion speed slows down due to the high doping concentration in this region, comprehensively realizing the diffusion speed of the electric field under the gate and improving the ability of the gate to withstand the drain voltage impact.
[0018] Fourth, there is a drift layer between the conductive layer and the masking layer of the present utility model, which is to prevent the conductive layer from weakening the electric field buffering of the masking layer at the gate insulating medium.
[0019] Fifth, the conductive layer of the present utility model realizes the shielding of the gate-drain capacitance of the device, effectively reducing the gate-drain capacitance of the device and improving the switching speed of the device.
[0020] Sixth, the conductive layer of the present utility model drains the electrons from the N-type source region to the middle region, reducing the total on-resistance of the device. Description of the Drawings
[0021] The following further describes the present utility model with reference to the drawings in conjunction with embodiments.
[0022] Figure 1 It is the schematic diagram of a silicon carbide VDMOS resistant to drain voltage impact of the present utility model.
[0023] Figure 2 It is the flowchart of the manufacturing method of a silicon carbide VDMOS resistant to drain voltage impact of the present utility model.
[0024] Figure 3 It is the process cross-section of a silicon carbide VDMOS resistant to drain voltage impact of the present utility model Figure 1 .
[0025] Figure 4 It is the process cross-section of a silicon carbide VDMOS resistant to drain voltage impact of the present utility model Figure 2 .
[0026] Figure 5 It is the process cross-section of a silicon carbide VDMOS resistant to drain voltage impact of the present utility model Figure 3 .
[0027] Figure 6 Process cross-section of a silicon carbide VDMOS resistant to drain voltage shock according to the present utility model Figure 4 。
[0028] Figure 7 Process cross-section of a silicon carbide VDMOS resistant to drain voltage shock according to the present utility model Figure 5 。
[0029] Figure 8 Process cross-section of a silicon carbide VDMOS resistant to drain voltage shock according to the present utility model Figure 6 。
[0030] Figure 9 Process cross-section of a silicon carbide VDMOS resistant to drain voltage shock according to the present utility model Figure 7 。
[0031] Figure 10 Process cross-section of a silicon carbide VDMOS resistant to drain voltage shock according to the present utility model Figure 8 。
[0032] Figure 11 Process cross-section of a silicon carbide VDMOS resistant to drain voltage shock according to the present utility model Figure 9 。
[0033] Figure 10 Process cross-section of a silicon carbide VDMOS resistant to drain voltage shock according to the present utility model Figure 10 。
[0034] Figure 13 Process cross-section of a silicon carbide VDMOS resistant to drain voltage shock according to the present utility model Figure 10 One.
[0035] Figure 14 Process cross-section of a silicon carbide VDMOS resistant to drain voltage shock according to the present utility model Figure 10 One. Detailed implementation manners
[0036] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.
[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used in the description of the present application in this specification are only for the purpose of describing specific embodiments and are not intended to limit the present application.
[0038] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "in contact with", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or parts, these elements, components, regions, layers, doping types, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or part from another element, component, region, layer, doping type, or part. Thus, without departing from the teachings of the present utility model, the first element, component, region, layer, doping type, or part discussed below may be denoted as the second element, component, region, layer, or part.
[0039] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientation depicted in the figures, spatial relationship terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "below" other elements or features will be oriented "on" the other elements or features. Thus, the exemplary terms "under" and "below" may include both an upper and a lower orientation. Additionally, the device may also assume other orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.
[0040] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / have" etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.
[0041] As Figure 1 shown, an embodiment of the present application provides a silicon carbide VDMOS resistant to drain voltage shock, comprising:
[0042] a silicon carbide substrate 1;
[0043] Drift layer 2, the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1; a conductive layer 21 is provided in the drift layer 2, a groove 22 is provided in the drift layer 2, and a masking layer 23 is provided at the bottom of the groove 22; a protective layer 24 is provided on the drift layer 2; the conductive layer 21 is located directly below the groove 22;
[0044] Well region 3, the lower side of the well region 3 is respectively connected to the drift layer 2 and the protective layer 24;
[0045] P-type source region 4, the lower side of the P-type source region 4 is connected to the well region 3;
[0046] N-type source region 5, the lower side of the N-type source region 5 is connected to the well region 3, and the outer side of the N-type source region 5 is connected to the inner side of the P-type source region 4;
[0047] Gate dielectric layer 6, the lower part of the gate dielectric layer 6 is provided in the groove 22, and the lower side of the gate dielectric layer 6 is connected to the masking layer 23; the outer side of the gate dielectric layer 6 is respectively connected to the inner side of the well region 3 and the inner side of the N-type source region 5; a trench 61 is provided in the gate dielectric layer 6;
[0048] Gate metal layer 7, the gate metal layer 7 is provided in the trench 61;
[0049] Source metal layer 8, the source metal layer 8 is respectively connected to the P-type source region 4 and the N-type source region 5;
[0050] And a drain metal layer 9, the drain metal layer 9 is connected to the lower side of the silicon carbide substrate 2;
[0051] The silicon carbide substrate 1, the drift layer 2 and the conductive layer 21 are all N-type; the protective layer 24, the masking layer 23 and the well region 3 are all P-type.
[0052] As Figures 2 to 14 shown, the manufacturing method of the above-mentioned silicon carbide VDMOS includes the following steps:
[0053] Step 1, deposit metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 9; epitaxially grow on the upper side of the silicon carbide substrate 1 to form a drift layer 2;
[0054] Step 2, form a barrier layer 10 on the drift layer 2, etch the barrier layer 10 to form a through hole, and perform ion implantation on the drift layer 2 to form a conductive layer 21;
[0055] Step 3, remove the barrier layer 10, reform the barrier layer 10, etch the barrier layer 10 to form a through hole, and perform ion implantation on the drift layer 2 to form a protective layer 24;
[0056] Step 4: Remove the blocking layer 10, reform the blocking layer 10, etch the blocking layer 10 to form a through hole, perform ion implantation on the drift layer 2 to form a masking layer 23;
[0057] Step 5: Remove the blocking layer 10, perform ion implantation on the drift layer 2 to form a well region 3;
[0058] Step 6: Form a blocking layer 10 on the drift layer 2, etch the blocking layer 10 to form a through hole, perform ion implantation on the well region 3 to form an N-type source region 5;
[0059] Step 7: Remove the blocking layer 10, reform the blocking layer 10, etch the blocking layer 10 to form a through hole, perform ion implantation on the well region 3 to form a P-type source region 4;
[0060] Step 8: Remove the blocking layer 10, reform the blocking layer 10, etch the blocking layer 10 to form a through hole, etch the drift layer 2 to the upper side surfaces of the N-type source region 5 and the P-type source region 4, deposit metal to form a source electrode metal layer 8;
[0061] Step 9: Remove the blocking layer 10, reform the blocking layer 10, etch the blocking layer 10 to form a through hole, and etch the drift layer 2 and the well region 3 to the upper side surface of the masking layer 23, oxidize to form a gate dielectric layer 6, and a groove 61 is provided in the gate dielectric layer 6;
[0062] Step 10: Remove the blocking layer 10, reform the blocking layer 10, etch the blocking layer 10 to form a through hole, deposit metal to form a gate electrode metal layer 7.
[0063] In this embodiment, preferably, the doping concentration of the silicon carbide substrate 1 is 2e18 cm -3 , the doping concentration of the drift layer 2 is 6e16 cm -3 , the doping concentration of the conductive layer 21 is 5e17 cm -3 , the doping concentration of the protective layer 24 is 8e17 cm -3 , the doping concentration of the masking layer 23 is 2e18 cm -3 , the doping concentration of the well region 3 is 5e17 cm -3 , the doping concentration of the N-type source region 5 is 2e18 cm -3 , the doping concentration of the P-type source region 4 is 1e19 cm -3; The doping concentration of the silicon carbide substrate 1 is to ensure a low-resistance ohmic contact with the drain metal layer 9 and reduce the overall on-resistance of the device; the doping concentration of the drift layer 2 is a trade-off between the reverse breakdown voltage and on-resistance of the device; the doping concentration of the conductive layer 21 is to divert the current from the N-type source region 5 to directly below the gate metal layer 7 of the device, avoiding overheating caused by excessive electric field density due to current concentration; the protective layer 24 is to reduce the impact of the drain voltage of the device on the source; the masking layer 23 is to suppress the electric field concentration at the gate corner of the device and the impact of the drain voltage on the gate of the device; the doping concentrations of the N-type source region 5 and the P-type source region 4 are to form an ohmic contact with the source metal layer 8 and reduce the contact resistance.
[0064] In this embodiment, preferably, the thickness of the silicon carbide substrate 1 of the device is 1 μm, the thickness of the drift layer 2 is 15 - 25 μm, which can be adjusted within the above range according to different requirements for the breakdown voltage characteristics of the device. The thickness of the conductive layer 21 is 300 nm. The conductive layer 21 can effectively shield the capacitive effect of the gate on the drain, reduce the gate-drain charge of the device, and improve the switching speed of the device; the distance from the upper side of the conductive layer 21 to the lower side of the masking layer 23 is 200 nm; this is to achieve the current diversion function of the conductive layer while avoiding the conductive layer weakening the electric field buffering of the P-type masking layer 23 at the gate dielectric layer 6. The thickness of the P-type masking layer 23 is 100 nm, and the thickness of the protective layer 24 is 300 nm. When a large voltage impact occurs at the drain of the device, the electric field is quickly buffered in the protective layer 24, without affecting the source region and well region structures of the device, improving the voltage impact on the source of the drain of the device. The thickness of the well region 3 is 100 nm. The combination of the doping concentration and thickness of the well region 3 can reduce the gate charge of the device, reduce the drive loss of the device, improve the switching speed of the device, reduce the resistance from the P-type source region 4 to the well region 3, and reduce the on-loss of the body diode. The design is completed from the perspective of reducing the on-loss of the body diode. The thicknesses of the N-type source region and the P-type source region are 300 nm, the thickness of the gate dielectric layer is 20 - 30 nm, and the thickness of the source metal layer 8 is 300 nm.
[0065] Although the specific implementation manners of the present invention have been described above, those skilled in the art should understand that the specific embodiments we described are illustrative rather than used to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should all be covered by the scope protected by the claims of the present invention.
Claims
1. A silicon carbide VDMOS resistant to drain voltage shock, characterized in that: Including: A silicon carbide substrate; A drift layer, the lower side surface of which is connected to the upper side surface of the silicon carbide substrate; A conductive layer is provided in the drift layer, a groove is provided in the drift layer, and a masking layer is provided at the bottom of the groove; a protective layer is provided on the drift layer; A well region, the lower side surface of which is respectively connected to the drift layer and the protective layer; A P-type source region, the lower side surface of which is connected to the well region; An N-type source region, the lower side surface of which is connected to the well region, and the outer side surface of the N-type source region is connected to the inner side surface of the P-type source region; A gate dielectric layer, the lower part of which is provided in the groove, and the lower side surface of the gate dielectric layer is connected to the masking layer; the outer side surface of the gate dielectric layer is respectively connected to the inner side surface of the well region and the inner side of the N-type source region; a trench is provided in the gate dielectric layer; A gate metal layer, which is provided in the trench; A source metal layer, which is respectively connected to the P-type source region and the N-type source region; And a drain metal layer, which is connected to the lower side surface of the silicon carbide substrate.
2. The silicon carbide VDMOS resistant to drain voltage impact according to claim 1, wherein: The conductive layer is located directly below the groove.
3. The silicon carbide VDMOS resistant to drain voltage shock according to claim 1, wherein: The silicon carbide substrate, the drift layer and the conductive layer are all N-type; the protective layer, the masking layer and the well region are all P-type.
4. The silicon carbide VDMOS resistant to drain voltage shock according to claim 1, wherein: The distance from the upper side surface of the conductive layer to the lower side surface of the masking layer is 200 nm; the thickness of the masking layer is 100 nm; the thickness of the protective layer is 330 nm.
5. A silicon carbide VDMOS resistant to drain voltage shock according to claim 1, characterized in that: The thickness of the conductive layer is 300 nm.