Planar gate silicon carbide VDMOS capable of reducing gate-drain capacitance

Abstract

The utility model provides a planar gate silicon carbide VDMOS capable of reducing gate-drain capacitance. The planar gate silicon carbide VDMOS is characterized in that the lower side surface of a first drift layer is connected to the upper side surface of a silicon carbide substrate; the lower side surface of the low-resistance channel region is connected to the upper side surface of the first drift layer; the lower side surface of the second drift layer is connected to the low-resistance channel region; the lower side surface of the P-type well region is connected to the lower side surface of the first drift layer; an N-type source region is arranged in the P-type well region; the inner side surface of the P-type well region is connected to the outer side surface of the low-resistance channel region and the outer side surface of the second drift layer; the lower side surface of the N-type body region is connected to the upper side surface of the first drift layer; the inner side surface of the N-type body region is connected to the outer side surface of the P-type well region; the lower side surface of the gate dielectric layer is respectively connected with the second drift layer and the P-type well region; the source metal layer is respectively connected with the N-type body region, the P-type well region and the N-type source region; the gate metal layer is connected to the gate dielectric layer; the drain metal layer is connected to the lower side surface of the silicon carbide substrate; the gate capacitance of the device is reduced, the switching speed of the device is improved, and the reverse recovery loss of the device is reduced.

Description

Technical Field

[0001] The utility model relates to a planar-gate silicon carbide VDMOS with reduced gate-drain capacitance. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices and has wide applications in fields such as electric vehicles, aerospace, and power conversion. High efficiency, small volume, and high power density are the most concerned features in applications with limited volume and weight, such as electric vehicles and aerospace. Therefore, reducing the gate charge of the device, reducing the reverse recovery time of the device, and increasing the switching speed of the device are the eternal demands for power devices in these applications. Content of the Utility Model

[0003] The technical problem to be solved by the utility model is to provide a planar-gate silicon carbide VDMOS with reduced gate-drain capacitance, which reduces the gate capacitance of the device, increases the switching speed of the device, and reduces the reverse recovery loss of the device. It is a better choice for power switches applied under conditions of limited volume and weight.

[0004] The utility model is implemented as follows: A planar-gate silicon carbide VDMOS with reduced gate-drain capacitance, comprising:

[0005] A silicon carbide substrate,

[0006] A first drift layer, the lower side of the first drift layer is connected to the upper side of the silicon carbide substrate;

[0007] A low-resistance channel region, the lower side of the low-resistance channel region is connected to the upper side of the first drift layer;

[0008] A second drift layer, the lower side of the second drift layer is connected to the low-resistance channel region;

[0009] A P-type well region, the lower side of the P-type well region is connected to the lower side of the first drift layer; an N-type source region is provided in the P-type well region, and the inner side of the P-type well region is connected to the outer side of the low-resistance channel region and the outer side of the second drift layer;

[0010] An N-type body region, the lower side of the N-type body region is connected to the upper side of the first drift layer, and the inner side of the N-type body region is connected to the outer side of the P-type well region;

[0011] A gate dielectric layer, the lower side of the gate dielectric layer is respectively connected to the second drift layer and the P-type well region;

[0012] A source metal layer, the source metal layer is respectively connected to the N-type body region, the P-type well region, and the N-type source region;

[0013] A gate metal layer, the gate metal layer is connected to the gate dielectric layer;

[0014] And a drain metal layer connected to the lower side of the silicon carbide substrate.

[0015] The advantages of the present utility model are as follows:

[0016] 1. The present utility model adopts a planar gate device structure and has the characteristics of a highly reliable gate.

[0017] 2. The present utility model constructs a low-resistance channel region under the planar gate of the device. This low-resistance channel region can reduce the resistance of the JFET region directly under the gate insulating dielectric of the device, thereby reducing the on-resistance of the device. And by constructing a low-resistance region directly under the gate, it shields the gate-drain capacitance of the device caused by the positive gate voltage, reduces the gate charge of the device, and improves the switching speed of the device.

[0018] 3. The present utility model constructs N-type body regions on both sides of the P-type well region of the device. The doping concentration of this N-type body region is higher than that of the N-type drift layer, and a Schottky diode with a low conduction voltage drop between the source metal and the N-type body region can be constructed, reducing the conduction voltage drop and reverse recovery time of the device, reducing the freewheeling loss of the body diode of the device, and improving the switching speed of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present utility model will be further described below with reference to the drawings in conjunction with embodiments.

[0020] Figure 1 It is a schematic diagram of a planar gate silicon carbide VDMOS for reducing gate-drain capacitance according to the present utility model.

[0021] Figure 2 It is a flowchart of a preparation method of a planar gate silicon carbide VDMOS for reducing gate-drain capacitance according to the present utility model.

[0022] Figure 3 It is a process cross-section of a planar gate silicon carbide VDMOS for reducing gate-drain capacitance according to the present utility model Figure 1 .

[0023] Figure 4 It is a process cross-section of a planar gate silicon carbide VDMOS for reducing gate-drain capacitance according to the present utility model Figure 2 .

[0024] Figure 5 It is a process cross-section of a planar gate silicon carbide VDMOS for reducing gate-drain capacitance according to the present utility model Figure 3 .

[0025] Figure 6 It is a process cross-section of a planar gate silicon carbide VDMOS for reducing gate-drain capacitance according to the present utility model Figure 4 .

[0026] Figure 7Process cross-section of a planar-gate silicon carbide VDMOS with reduced gate-drain capacitance according to the present utility model Figure 5 。

[0027] Figure 8 Process cross-section of a planar-gate silicon carbide VDMOS with reduced gate-drain capacitance according to the present utility model Figure 6 。

[0028] Figure 9 Process cross-section of a planar-gate silicon carbide VDMOS with reduced gate-drain capacitance according to the present utility model Figure 7 。

[0029] Figure 10 Process cross-section of a planar-gate silicon carbide VDMOS with reduced gate-drain capacitance according to the present utility model Figure 8 。 Detailed implementation manner

[0030] To facilitate understanding of this application, the following will provide a more comprehensive description of this application with reference to relevant attached drawings. Embodiments of this application are shown in the attached drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of this application more thorough and comprehensive.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used in the description of this application in this specification are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0032] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "in contact with", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or parts, these elements, components, regions, layers, doping types, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or part from another element, component, region, layer, doping type, or part. Therefore, without departing from the teachings of the present utility model, the first element, component, region, layer, doping type, or part discussed below may be referred to as the second element, component, region, layer, or part.

[0033] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. can be used herein to describe the relationship of one element or feature described in the figure with other elements or features. It should be understood that, in addition to the orientations described in the figure, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the drawing is flipped, an element or feature described as "under other elements" or "beneath it" or "under it" will be oriented "above" other elements or features. Thus, the exemplary terms "under" and "beneath" can include both upper and lower orientations. In addition, the device may also include additional orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are accordingly interpreted.

[0034] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that terms such as "comprising" or "having" etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0035] As Figure 1 shown, an embodiment of the present application provides a planar-gate silicon carbide VDMOS for reducing gate-drain capacitance, comprising:

[0036] A silicon carbide substrate 101,

[0037] A first drift layer 102, the lower side of the first drift layer 102 being connected to the upper side of the silicon carbide substrate 101;

[0038] A low-resistance channel region 103, the lower side of the low-resistance channel region 103 being connected to the upper side of the first drift layer 102;

[0039] A second drift layer 104, the lower side of the second drift layer 104 being connected to the low-resistance channel region 103;

[0040] A P-type well region 105, the lower side of the P-type well region 105 being connected to the lower side of the first drift layer 102; an N-type source region 1051 is provided in the P-type well region 105, and the inner side of the P-type well region 105 is connected to the outer side of the low-resistance channel region 103 and the outer side of the second drift layer 104;

[0041] The N-type body region 106, the lower side surface of the N-type body region 106 is connected to the upper side surface of the first drift layer 102, and the inner side surface of the N-type body region 106 is connected to the outer side surface of the P-type well region 105;

[0042] The gate dielectric layer 107, the lower side surface of the gate dielectric layer 107 is respectively connected to the second drift layer 104 and the P-type well region 105;

[0043] The source metal layer 108, the source metal layer 108 is respectively connected to the N-type body region 106, the P-type well region 105 and the N-type source region 1051;

[0044] The gate metal layer 109, the gate metal layer 109 is connected to the gate dielectric layer 107;

[0045] And, the drain metal layer 110, the drain metal layer 110 is connected to the lower side surface of the silicon carbide substrate 101.

[0046] As Figures 2 to 10 shown, the manufacturing method of the above-mentioned silicon carbide VDMOS includes the following steps:

[0047] Step 1, deposit metal on the lower side surface of the silicon carbide substrate 101 to form the drain metal layer 110; epitaxially grow on the upper side surface of the silicon carbide substrate 101 to form the drift region 111;

[0048] Step 2, form the barrier layer 112 on the drift region 111, etch the barrier layer 112 to form a through hole, perform ion implantation on the drift region 111 to form the N-type body region 106, and the ion implantation energy is 10 - 200 kev;

[0049] Step 3, remove the original barrier layer 112, reform the barrier layer 112, etch the barrier layer 112 to form a through hole, perform ion implantation on the drift region 111 to form the P-type well region 105, and the ion implantation energy is 10 - 200 kev;

[0050] Step 4, remove the original barrier layer 112, reform the barrier layer 112, etch the barrier layer 112 to form a through hole, perform ion implantation on the drift region 111 to form the low-resistance channel region 103, the first drift layer 102 and the second drift layer 104, and the ion implantation energy is 100 - 200 kev;

[0051] Step 5, remove the original barrier layer 112, reform the barrier layer 112, etch the barrier layer 112 to form a through hole, perform ion implantation on the P-type well region 105 to form the N-type source region 1051, and the ion implantation energy is 10 - 100 kev;

[0052] Step 6, remove the original barrier layer 112, reform the barrier layer 112, etch the barrier layer 112 to form a through hole, and deposit to form the gate dielectric layer 107;

[0053] Step 7: Remove the original barrier layer 112, reform the barrier layer 112, etch the barrier layer 112 to form a through hole, deposit metal, and form the gate metal layer 109;

[0054] Step 8: Remove the original barrier layer 112, reform the barrier layer 112, etch the barrier layer 112 to form a through hole, deposit metal, and form the source metal layer 108.

[0055] The doping concentration of the N-type body region 106 is higher than that of the first drift layer 102 and the P-type well region 105; the silicon carbide substrate 101 is N-type with a doping concentration of 2e18 cm -3 ; both the first drift layer 102 and the second drift layer 104 are N-type with doping concentrations of 5e16 cm -3 ; the low-resistance channel region 103 is N-type with a doping concentration of 8e17 cm -3 ; the doping concentration of the P-type well region 105 is 1e17 cm -3 , the doping concentration of the N-type body region 106 is 2e17 cm -3 , the doping concentration of the N-type source region 1051 is 2e18 cm -3 ; the gate dielectric layer 107 is silicon dioxide; the gate metal layer 109, the source metal layer 108, and the drain metal layer 110 are all Al. The thickness of the silicon carbide substrate 101 of the device is 1 μm; the thickness of the drift layer 102 is 10 - 20 μm; the thickness of the N-type low-resistance channel region 103 is 300 nm, the thickness from the bottom of the P-type well region 105 to the bottom of the N-type source region 1051 is 300 nm, the thickness from the bottom of the P-type well region 105 to the bottom of the source metal layer 108 is 600 nm, the bottom of the P-type well region 105 is flush with the bottom of the N-type low-resistance channel region 103, the thickness of the P-type well region 105 is 600 nm, the thickness of the N-type source region 1051 is 300 nm, the thickness of the source metal layer 108 is 300 nm, the thickness of the insulating dielectric layer 107 is 20 nm, the thickness of the gate metal layer 109 is 280 nm, the breakdown voltage of the device is 800 - 1200 V, the width L1 of the N-type body region 106 is 50 nm, and the distance L2 from the edge of the P-type well region away from the gate to the edge of the N-type source region away from the gate is ≥500 nm;

[0056] The concentration of the N-type silicon carbide substrate 101 is for forming a low-resistance ohmic contact with the drain metal layer 110, reducing the on-resistance of the device. Its thickness is designed to ensure support under the design conditions of the device epitaxial thickness (N-type first drift layer 102), improving the process stability. The thickness and doping concentration of the N-type first drift layer 102 are a compromise between on-resistance and breakdown voltage. The design of the N-type body region 106 is to reduce the on-voltage drop of the device body diode and reduce the reverse recovery time of the device. The N-type low-resistance channel region 103 is to reduce the on-resistance of the device and reduce the gate-drain capacitance of the device. Its concentration, thickness, and positional relationship are to increase the N-type doping concentration in the JFET region without affecting the gate control ability of the device, reducing the on-resistance of the JFET region of the device. At the same time, a low-resistance region between the gate and the drain is constructed through the low-resistance N-type low-resistance channel region, reducing the gate-drain capacitance of the device;

[0057] The design of the width of the N-type body region 106 of the device is to complete the pn structure formation from the P-type well region 105 to the N-type body region 106 when a positive voltage is applied to the drain when the device is turned off, avoiding the diffusion of the electric field from the N-type body region 106 to the source during reverse breakdown voltage. When the gate of the device is not turned on and a positive voltage is applied to the source, a Schottky diode is formed between the source and the N-type body region 106. Since the Schottky diode has no hole conduction, its reverse recovery speed is fast and the loss is low, which can improve the switching speed of the device.

[0058] Although the specific embodiments of the present invention have been described above, those skilled in the art of this technology should understand that the specific embodiments we described are illustrative rather than used to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered by the scope protected by the claims of the present invention.

Claims

1. A planar-gate silicon carbide VDMOS for reducing gate-drain capacitance, characterized in that: Comprising: A silicon carbide substrate, A first drift layer, the lower side surface of the first drift layer being connected to the upper side surface of the silicon carbide substrate; A low-resistance channel region, the lower side surface of the low-resistance channel region being connected to the upper side surface of the first drift layer; A second drift layer, the lower side surface of the second drift layer being connected to the low-resistance channel region; A P-type well region, the lower side surface of the P-type well region being connected to the lower side surface of the first drift layer; an N-type source region is provided in the P-type well region, and the inner side surface of the P-type well region is connected to the outer side surface of the low-resistance channel region and the outer side surface of the second drift layer; An N-type body region, the lower side surface of the N-type body region being connected to the upper side surface of the first drift layer, and the inner side surface of the N-type body region being connected to the outer side surface of the P-type well region; A gate dielectric layer, the lower side surface of the gate dielectric layer being respectively connected to the second drift layer and the P-type well region; A source metal layer, the source metal layer being respectively connected to the N-type body region, the P-type well region, and the N-type source region; A gate metal layer, the gate metal layer being connected to the gate dielectric layer; And a drain metal layer, the drain metal layer being connected to the lower side surface of the silicon carbide substrate.

2. The planar-gate silicon carbide VDMOS for reducing gate-drain capacitance according to claim 1, wherein: The thickness of the N-type body region is equal to the thickness of the P-type well region.

3. The planar-gate silicon carbide VDMOS for reducing gate-drain capacitance according to claim 1, wherein: The width of the N-type body region is 50 nm.

4. The planar-gate silicon carbide VDMOS for reducing gate-drain capacitance according to claim 1, wherein: The thickness of the N-type low-resistance channel region is 300 nm; the thickness of the second drift layer is 300 nm.

5. The planar-gate silicon carbide VDMOS for reducing gate-drain capacitance according to claim 1, wherein: The doping concentration of the N-type body region is higher than the doping concentration of the first drift layer and the doping concentration of the P-type well region.

Images