Novel silicon carbide VDMOS transistor structure

Abstract

The utility model relates to the technical field of MOS (Metal Oxide Semiconductor), and discloses a novel silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) transistor structure, which comprises a novel silicon carbide VDMOS transistor structure consisting of a plurality of VDMOS cells, and is characterized in that each VDMOS cell comprises a drain electrode, a metal source electrode, a grid electrode and a semiconductor epitaxial layer; the semiconductor epitaxial layer comprises a sinking layer, a diffusion layer, a P well layer and an N well layer; wherein a drift layer is formed between the substrate layer and the diffusion layer through ion implantation, and the drift layer comprises a lightly doped drift layer I, a lightly doped drift layer II and a heavily doped drift layer; the P well layer comprises a heavily doped P well layer I, a lightly doped P well layer I and a heavily doped P well layer II; the N-well layer comprises a heavily doped N-well layer 1, a lightly doped N-well layer 1 and a lightly doped N-well layer 2. According to the utility model, the multi-level drift layer is formed between the substrate layer and the diffusion layer through ion implantation, the drift layer does not influence the attraction of a grid electric field to drain charges, and the probability that the drain charges directly break down the oxide layer is also reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of MOS semiconductors, and more specifically to a novel silicon carbide VDMOS transistor structure. Background Art

[0002] A VDMOS (Vertical Double-diffused MOS) device is a vertical double-diffused MOS (Metal Oxide Semiconductor) device, usually referring to a VDMOSFET (Vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor). This device is well-known for its structural characteristics and is mainly used in power electronics applications. VDMOS devices have the advantages of low on-resistance, high breakdown voltage, high-speed switching, etc., and are suitable for occasions requiring high-performance power switches, such as power management, electric vehicle control, frequency converters, etc.

[0003] A prior patent discloses a metal gate and field plate structure of a radio frequency VDMOS transistor and its manufacturing method (publication number CN107068567A). By using wet etching, a trapezoidal oxide layer is formed at the middle position on the surface of the silicon substrate epitaxial layer; then, conventional processes are used on both sides of the trapezoidal oxide layer to form conventional doped regions such as channels, source and drain; next, a gate oxide layer is grown on the surface of the epitaxial layer and covered with a metal layer, and wet etching is used to remove the metal layer on the side of the trapezoidal oxide layer; finally, dry etching is used to form the metal gate and field plate structure. In the technology disclosed in this patent, after a gate voltage is applied to the gate, there is a probability that due to the sudden application of the gate electric field, the charge at the drain will break down the oxide layer under the action of the electric field. And there is a lateral radiation in the gate electric field, which causes the gate electric field to also interfere with the P-well layer or N-well layer, and further makes a parasitic capacitance formed in the epitaxial layer part of this MOS semiconductor. Summary of the Invention

[0004] The main technical problem to be solved by the utility model is to provide a novel silicon carbide VDMOS transistor structure, which solves the problems in the above background art.

[0005] To solve the above technical problem, according to one aspect of the utility model, more specifically, a novel silicon carbide VDMOS transistor structure includes a novel silicon carbide VDMOS transistor structure composed of a plurality of VDMOS cells. The VDMOS cell includes a drain, a metal source, a gate, and a semiconductor epitaxial layer;

[0006] The semiconductor epitaxial layer includes a deposition layer, a diffusion layer, a P-well layer, and an N-well layer;

[0007] Among them, a drift layer is formed by ion implantation between the substrate layer and the diffusion layer, and the drift layer includes a lightly doped drift layer 1, a lightly doped drift layer 2, and a heavily doped drift layer;

[0008] The P-well layer includes a heavily doped P-well layer 1, a lightly doped P-well layer 1, and a heavily doped P-well layer 2;

[0009] The N-well layer includes a heavily doped N-well layer 1, a lightly doped N-well layer 1, and a lightly doped N-well layer 2;

[0010] When the gate is connected to the gate voltage, the internal charges in the lightly doped P-well layer 1 gather towards the gate to form a charge channel, and the diffusion layer and the N-well layer are connected through the charge channel.

[0011] Furthermore, an oxide layer is deposited between the surface of the gate, the metal source, and the semiconductor epitaxial layer.

[0012] Furthermore, when a voltage is applied to the gate, a depletion layer of the JFET region is formed inside the diffusion layer, and the depletion layer is located between two heavily doped P-well layers 2.

[0013] Furthermore, the heavily doped P-well layer 1 and the heavily doped P-well layer 2 between adjacent VDMOS cells are in ohmic contact with each other.

[0014] Furthermore, a lightly doped and heavily doped P-well layer 2 is formed by low-concentration ion implantation at the intersection of the lightly doped P-well layer 1 and the heavily doped P-well layer 2.

[0015] Furthermore, the heavily doped N-well layer 1, the lightly doped N-well layer 1, and the lightly doped N-well layer 2 adopt a lateral array design, and the cross-sectional profiles of the heavily doped N-well layer 1, the lightly doped N-well layer 1, and the lightly doped N-well layer 2 are the same in size and shape.

[0016] Furthermore, the heavily doped N-well layer 1, the lightly doped N-well layer 1, and the lightly doped N-well layer 2 in the N-well layer are all in ohmic contact with the metal source.

[0017] Furthermore, the lightly doped drift layer 1, the lightly doped drift layer 2, and the heavily doped drift layer are arranged from high to low in sequence, and the cross-sectional heights of the lightly doped drift layer 1, the lightly doped drift layer 2, and the heavily doped drift layer are the same.

[0018] Furthermore, the substrate layer, the heavily doped N-well layer 1, and the heavily doped drift layer are doped with high-concentration phosphorus ions;

[0019] The lightly doped drift layer 2, the lightly doped drift layer 1, the lightly doped N-well layer 2, the diffusion layer, and the lightly doped N-well layer 1 are doped with low-concentration phosphorus ions.

[0020] Further, the lightly and heavily doped P-well layer two and the heavily doped P-well layer two are doped with a high concentration of boron ions.

[0021] The beneficial effects of a novel silicon carbide VDMOS transistor structure of the present utility model are as follows:

[0022] 1. In the present utility model, a multi-level drift layer is formed by ion implantation between the substrate layer and the diffusion layer. The drift layer neither affects the attraction of the gate electric field to the drain charge, nor reduces the probability of the direct breakdown of the drain charge through the oxide layer.

[0023] 2. By dividing the N-well layer into a three-equal-part hierarchical design, the present utility model can effectively reduce the excessive lateral intervention of the gate electric field on the charges inside the N-well layer, thereby affecting adjacent VDMOS cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The present utility model will be further described in detail below with reference to the drawings and specific implementation methods.

[0025] Figure 1 is a schematic diagram of a novel silicon carbide VDMOS transistor structure;

[0026] Figure 2 is Figure 1 a partial enlarged detail schematic diagram;

[0027] Figure 3 is a schematic diagram of a dual-cell juxtaposed structure of the present utility model.

[0028] In the figure: 1. Drain; 2. Substrate layer; 3. Metal source; 4. Oxide layer; 5. Gate; 6. Heavily doped N-well layer one; 7. Lightly doped N-well layer one; 8. Lightly doped N-well layer two; 9. Heavily doped P-well layer one; 10. Lightly doped P-well layer one; 11. Lightly and heavily doped P-well layer two; 12. Heavily doped P-well layer two; 13. Diffusion layer; 14. Lightly doped drift layer one; 15. Lightly doped drift layer two; 16. Heavily doped drift layer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0029] The present utility model will be described in detail below with reference to the drawings and embodiments. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0030] As Figures 1-3 shown, according to one aspect of the present utility model, a novel silicon carbide VDMOS transistor structure is provided, including a novel silicon carbide VDMOS transistor structure composed of a plurality of VDMOS cells. The VDMOS cell includes a drain 1, a metal source 3, a gate 5, and a semiconductor epitaxial layer. The semiconductor epitaxial layer includes a substrate layer 2, a diffusion layer 13, a P-well layer, and an N-well layer (as Figure 1As shown, when the gate 5 is connected to the gate voltage, a charge channel will be formed inside the P-well layer. This charge channel can connect the diffusion layer 13 and the N-well layer, so that the drain 1 and the metal source 3 are electrically connected.

[0031] Among them, a drift layer is formed by ion implantation between the substrate layer 2 and the diffusion layer 13. The drift layer includes a lightly doped drift layer 14, a lightly doped drift layer 15, and a heavily doped drift layer 16 (as Figure 2 shown). A multi-level drift layer is formed by ion implantation between the substrate layer 2 and the diffusion layer 13. The drift layer not only does not affect the attraction of the gate electric field to the overflow charge of the drain 1, but also reduces the probability of the direct breakdown of the oxide layer 4 by the charge of the drain 1.

[0032] In this embodiment, the P-well layer includes a heavily doped P-well layer 9, a lightly doped P-well layer 10, and a heavily doped P-well layer 12. Among them, this part of the body region is doped with boron element, and the doping concentration of each body region is:

[0033] The doping concentration of the lightly and heavily doped P-well layer 11 is 4 - 7×10 16 mol / cm 3 .

[0034] The doping concentration of the heavily doped P-well layer 12 is 7 - 8×10 18 mol / cm 3 .

[0035] In this embodiment, the N-well layer includes a heavily doped N-well layer 6, a lightly doped N-well layer 7, and a lightly doped N-well layer 8. Among them, this part of the body region is doped with phosphorus element, and the doping and ion implantation concentration of each body region is:

[0036] The doping concentration of the substrate layer 2 and the heavily doped N-well layer 6 is 5 - 8×10 18 mol / cm 3 .

[0037] The doping concentration of the heavily doped drift layer 16 is 1 - 3.2×10 18 mol / cm 3 .

[0038] The doping concentration of the lightly doped drift layer 15 is 7 - 9.4×10 16 mol / cm 3 .

[0039] The doping concentration of the lightly doped drift layer 14 and the lightly doped N-well layer 8 is 1 - 2.7×10 16 mol / cm 3 .

[0040] The doping concentration of the diffusion layer 13 and the lightly doped N-well layer 7 is 4 - 5.4×1016 mol / cm 3 。

[0041] In this embodiment, when the gate 5 is connected to the gate voltage, the charges inside the lightly doped P-well layer 10 gather towards the gate 5 to form a charge channel, and the diffusion layer 13 and the N-well layer are connected through the charge channel. When the gate voltage is positive, the gate electric field will attract the movement of negative charges, concentrating in the region near the semiconductor surface of the oxide layer 4. This region forms a negatively charged channel, and because the number of electrons increases, an N-type channel is formed.

[0042] An oxide layer 4 is deposited between the surface of the gate 5, the metal source electrode 3, and the semiconductor epitaxial layer. When a voltage is applied to the gate 5, a depletion layer in the JFET region will be formed inside the diffusion layer 13, and the depletion layer is located between two heavily doped P-well layers 12. The characteristics of the depletion layer in the JFET region depend on the action of the gate electric field, and the conductivity of the JFET region can be adjusted by controlling the gate voltage.

[0043] In this embodiment, the heavily doped P-well layer 9 and the heavily doped P-well layer 12 between adjacent VDMOS cells are in ohmic contact with each other, and a lightly doped P-well layer 10 and a heavily doped P-well layer 12 are cross-sectionally intersected to form a lightly and heavily doped P-well layer 11 by low-concentration ion implantation (as Figure 3 shown). The lightly and heavily doped P-well layer 11 can suppress the charge mobility between the lightly doped P-well layer 10 and the heavily doped P-well layer 12. This ensures that when the P-well layer is intervened by the gate electric field, the stock of parasitic charges in the P-well layer is reduced.

[0044] In this embodiment, the heavily doped N-well layer 6, the lightly doped N-well layer 7, and the lightly doped N-well layer 8 are designed in a horizontal array, and the cross-sectional profiles of the heavily doped N-well layer 6, the lightly doped N-well layer 7, and the lightly doped N-well layer 8 are the same in size and shape. The heavily doped N-well layer 6, the lightly doped N-well layer 7, and the lightly doped N-well layer 8 in the N-well layer are all in ohmic contact with the metal source electrode 3 (as Figure 1 shown). The N-well layer is divided into a three-equal-part hierarchical design, which can effectively reduce the excessive lateral intervention effect of the gate electric field on the charges inside the N-well layer.

[0045] In this embodiment, the lightly doped drift layer 14, the lightly doped drift layer 15, and the heavily doped drift layer 16 are arranged in order from high to low, and the cross-sectional heights of the lightly doped drift layer 14, the lightly doped drift layer 15, and the heavily doped drift layer 16 are the same. This design can reduce the amount of instantaneous charges that appear on the shortest route between the gate and the source electrode, improving the breakdown voltage performance of this semiconductor.

[0046] Certainly, the above description is not a limitation of the present utility model, nor is the present utility model limited to the above examples. Changes, modifications, additions or substitutions made by those of ordinary skill in the art within the scope of the essence of the present utility model also fall within the protection scope of the present utility model.

Claims

1. A novel silicon carbide VDMOS transistor structure, characterized in that, A novel silicon carbide VDMOS transistor structure composed of multiple VDMOS cells, where each VDMOS cell includes a drain (1), a metal source (3), a gate (5), and a semiconductor epitaxial layer; The semiconductor epitaxial layer includes a substrate layer (2), a diffusion layer (13), a P-well layer, and an N-well layer; Among them, a drift layer is formed by ion implantation between the substrate layer (2) and the diffusion layer (13), and the drift layer includes a lightly doped drift layer one (14), a lightly doped drift layer two (15), and a heavily doped drift layer (16); The P-well layer includes a heavily doped P-well layer one (9), a lightly doped P-well layer one (10), and a heavily doped P-well layer two (12); The N-well layer includes a heavily doped N-well layer one (6), a lightly doped N-well layer one (7), and a lightly doped N-well layer two (8); When the gate (5) is in a state of accessing the gate voltage, charges inside the lightly doped P-well layer one (10) gather towards the gate (5) to form a charge channel, and the diffusion layer (13) and the N-well layer are connected through the charge channel.

2. The novel silicon carbide VDMOS transistor structure according to claim 1, wherein: An oxide layer (4) is deposited between the surface of the gate (5), the metal source (3), and the semiconductor epitaxial layer.

3. The novel silicon carbide VDMOS transistor structure according to claim 1, wherein: When a voltage is applied to the gate (5), a depletion layer of the JFET region is formed inside the diffusion layer (13), and the depletion layer is located between two heavily doped P-well layers two (12).

4. The novel silicon carbide VDMOS transistor structure according to claim 1, characterized in that: The heavily doped P-well layer one (9) and the heavily doped P-well layer two (12) between adjacent VDMOS cells are in ohmic contact with each other.

5. The novel silicon carbide VDMOS transistor structure according to claim 1, characterized in that: A lightly and heavily doped P-well layer two (11) is formed by low-concentration ion implantation at the intersection of the lightly doped P-well layer one (10) and the heavily doped P-well layer two (12).

6. The novel silicon carbide VDMOS transistor structure according to claim 1, characterized in that: The heavily doped N-well layer one (6), the lightly doped N-well layer one (7), and the lightly doped N-well layer two (8) adopt a lateral array design, and the cross-sectional profiles of the heavily doped N-well layer one (6), the lightly doped N-well layer one (7), and the lightly doped N-well layer two (8) are of the same size and shape.

7. The novel silicon carbide VDMOS transistor structure according to claim 6, characterized in that: The heavily doped N-well layer one (6), the lightly doped N-well layer one (7), and the lightly doped N-well layer two (8) in the N-well layer are all in ohmic contact with the metal source (3).

8. The novel silicon carbide VDMOS transistor structure according to claim 1, characterized in that: The lightly doped drift layer one (14), the lightly doped drift layer two (15), and the heavily doped drift layer (16) are arranged from high to low in sequence, and the cross-sectional heights of the lightly doped drift layer one (14), the lightly doped drift layer two (15), and the heavily doped drift layer (16) are the same.

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