Low-on-resistance trench gate silicon carbide VDMOS

Abstract

The utility model provides a low-on-resistance trench gate silicon carbide VDMOS. The low-on-resistance trench gate silicon carbide VDMOS is characterized in that the lower side surface of a drift layer is connected to the upper side surface of a silicon carbide substrate; a second P-type well region, a groove and a shielding layer are arranged in the drift layer, and a second N-type source region is arranged in the second P-type well region; the lower side surface of the first P-type well region is connected to the drift layer, the second P-type well region and the second N-type source region; the lower side surface of the first N-type source region is connected to the upper side surface of the first P-type well region; the lower portion of the gate dielectric layer is arranged in the groove, the outer side wall of the gate dielectric layer is connected with the first N-type source region, the first P-type well region and the drift layer, and a groove is formed in the gate dielectric layer; the source metal layer is respectively connected with the first N-type source region, the first P-type well region, the drift layer, the second P-type well region and the second N-type source region; the gate metal layer is arranged in the groove; and the drain metal layer is connected to the lower side surface of the silicon carbide substrate to construct a second N-type source region and a second P-type well region for providing a large number of electrons in the drift layer and reducing the on-resistance of the device.

Description

Technical Field

[0001] The utility model relates to a trench-gate silicon carbide VDMOS with low on-resistance. Background Art

[0002] Silicon carbide MOSFET is a typical representative of silicon carbide power devices and has wide applications in fields such as electric vehicles, aerospace, and power conversion. The device has achieved good characteristics within 1200V and has completed the replacement of silicon MOSFET and IGBT within 1200V. With the improvement of the device's breakdown voltage and the reduction of on-resistance, achieving high reliability and low on-resistance under high breakdown voltage conditions has become a new requirement for the development of device technology; there is an urgent need to provide a silicon carbide power device with low on-resistance. Summary of the Utility Model

[0003] The technical problem to be solved by the utility model is to provide a trench-gate silicon carbide VDMOS with low on-resistance, which constructs a second P-type well region and a second N-type source region on the basis of ensuring the breakdown voltage of the device and the low on-resistance of the trench gate, and further reduces the on-resistance of the device.

[0004] The utility model is implemented as follows: A trench-gate silicon carbide VDMOS with low on-resistance, comprising:

[0005] A silicon carbide substrate,

[0006] A drift layer, the lower side surface of the drift layer is connected to the upper side surface of the silicon carbide substrate; a second P-type well region is provided in the drift layer, a second N-type source region is provided in the second P-type well region, a groove is provided on the drift layer, and a shielding layer is provided in the drift layer, and the shielding layer is located at the bottom of the groove;

[0007] A first P-type well region, the lower side surface of the first P-type well region is connected to the drift layer, the second P-type well region, and the second N-type source region;

[0008] A first N-type source region, the lower side surface of the first N-type source region is connected to the upper side surface of the first P-type well region;

[0009] A gate dielectric layer, the lower part of the gate dielectric layer is provided in the groove, the outer side walls of the gate dielectric layer are respectively connected to the first N-type source region, the first P-type well region, and the drift layer, and a trench is provided in the gate dielectric layer;

[0010] A source metal layer, the source metal layer is respectively connected to the first N-type source region, the first P-type well region, the drift layer, the second P-type well region, and the second N-type source region;

[0011] A gate metal layer, the gate metal layer is provided in the trench;

[0012] And a drain metal layer connected to the lower side of the silicon carbide substrate.

[0013] The advantages of the present utility model are as follows:

[0014] 1. On the basis of the trench-gate VDMOS device structure, a second N-type source region and a second P-type well region structure are constructed to provide a large number of electrons in the drift region, thereby reducing the on-resistance of the device;

[0015] 2. A direct contact between the source metal layer and the N-type drift layer is constructed on the left and right sides of the device, thereby forming a Schottky contact and constructing a parasitic Schottky diode, which can reduce the body diode voltage drop of the device and improve the reverse recovery speed of the device;

[0016] 3. The gate metal layer of the device is 170 nm deeper than the first P-type well region, thereby realizing the gate control of the second P-type well region and the second N-type source region structure;

[0017] 4. A P-type shielding layer is constructed at the bottom of the gate dielectric layer of the device, which can effectively suppress the gate reliability problem caused by electric field concentration at the gate corner while shielding the gate-drain capacitance and improving the switching speed of the device. Description of the Drawings

[0018] The present utility model will be further described below with reference to the drawings in conjunction with embodiments.

[0019] Figure 1 It is a schematic diagram of a low-on-resistance trench-gate silicon carbide VDMOS of the present utility model.

[0020] Figure 2 It is a flowchart of a preparation method of a low-on-resistance trench-gate silicon carbide VDMOS of the present utility model.

[0021] Figure 3 It is a process cross-section of a low-on-resistance trench-gate silicon carbide VDMOS of the present utility model Figure 1 。

[0022] Figure 4 It is a process cross-section of a low-on-resistance trench-gate silicon carbide VDMOS of the present utility model Figure 2 。

[0023] Figure 5 It is a process cross-section of a low-on-resistance trench-gate silicon carbide VDMOS of the present utility model Figure 3 。

[0024] Figure 6 It is a process cross-section of a low-on-resistance trench-gate silicon carbide VDMOS of the present utility model Figure 4 。

[0025] Figure 7Process cross-section of a low on-resistance trench-gate silicon carbide VDMOS of the present utility model Figure 5 。

[0026] Figure 8 Process cross-section of a low on-resistance trench-gate silicon carbide VDMOS of the present utility model Figure 6 。

[0027] Figure 9 Process cross-section of a low on-resistance trench-gate silicon carbide VDMOS of the present utility model Figure 7 。

[0028] Figure 10 Process cross-section of a low on-resistance trench-gate silicon carbide VDMOS of the present utility model Figure 8 。

[0029] Figure 11 Process cross-section of a low on-resistance trench-gate silicon carbide VDMOS of the present utility model Figure 9 。

[0030] Figure 12 Process cross-section of a low on-resistance trench-gate silicon carbide VDMOS of the present utility model Figure 10 。

[0031] Figure 13 Process cross-section of a low on-resistance trench-gate silicon carbide VDMOS of the present utility model Figure 10 One.

[0032] Figure 14 Process cross-section of a low on-resistance trench-gate silicon carbide VDMOS of the present utility model Figure 10 Two.

[0033] Figure 15 Process cross-section of a low on-resistance trench-gate silicon carbide VDMOS of the present utility model Figure 10 Three. Detailed implementation manners

[0034] To facilitate the understanding of this application, the following will describe this application more comprehensively with reference to the relevant drawings. Embodiments of this application are given in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of this application more thorough and comprehensive.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0036] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "in contact with", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as the second element, component, region, layer, or portion.

[0037] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientation depicted in the figures, spatial relationship terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. Additionally, the device may also include other orientations (such as rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0038] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprise / include" or "have" etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0039] As Figure 1 shown, an embodiment of the present application provides a low on-resistance trench-gate silicon carbide VDMOS, including:

[0040] a silicon carbide substrate 1,

[0041] A drift layer 2, the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1; a second P-type well region 21 is provided in the drift layer 2, a second N-type source region 211 is provided in the second P-type well region 21, a groove 22 is provided on the drift layer 2, a shielding layer 23 is provided in the drift layer 2, and the shielding layer 23 is located at the bottom of the groove 22;

[0042] A first P-type well region 3, the lower side of the first P-type well region 3 is connected to the drift layer 2, the second P-type well region 21 and the second N-type source region 211;

[0043] A first N-type source region 4, the lower side of the first N-type source region 4 is connected to the upper side of the first P-type well region 3;

[0044] A gate dielectric layer 5, the lower part of the gate dielectric layer 5 is provided in the groove 22, the outer sidewalls of the gate dielectric layer 5 are respectively connected to the first N-type source region 4, the first P-type well region 3 and the drift layer 2, and a trench 51 is provided in the gate dielectric layer 5;

[0045] A source metal layer 6, the source metal layer 6 is respectively connected to the first N-type source region 4, the first P-type well region 3, the drift layer 2, the second P-type well region 21 and the second N-type source region 211;

[0046] A gate metal layer 7, the gate metal layer 7 is provided in the trench 51;

[0047] And a drain metal layer 8, the drain metal layer 8 is connected to the lower side of the silicon carbide substrate 2.

[0048] As Figures 2 to 15 shown, the preparation method of the above-mentioned silicon carbide VDMOS includes the following steps:

[0049] Step 1, deposit metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 8; epitaxially grow on the upper side of the silicon carbide substrate 1 to form a drift layer 2;

[0050] Step 2, form a barrier layer a on the upper part of the drift layer 2, etch the barrier layer a to form a through hole, perform ion implantation on the drift layer 2, and form a shielding layer 23 in the drift layer 2, and the ion implantation energy is 370 - 440 kev, 1100 nm - 1300 nm;

[0051] Step 3, remove the barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, perform ion implantation on the drift layer 2, and form a second P-type well region 21 in the drift layer 2, and the ion implantation energy is 300 - 400 kev;

[0052] Step 4: Remove the blocking layer a, reform the blocking layer a, etch the blocking layer a to form a through hole, perform ion implantation on the drift layer 2 to form a second N-type source region 211 in the second P-type well region 21, and the ion implantation energy is 300 - 370 kev;

[0053] Step 5: Remove the blocking layer a, reform the blocking layer a, etch the blocking layer a to form a through hole, perform ion implantation on the drift layer 2 to form a first P-type well region 3 in the drift layer 2, and the ion implantation energy is 200 - 300 kev;

[0054] Step 6: Remove the blocking layer a, reform the blocking layer a, etch the blocking layer a to form a through hole, perform ion implantation on the drift layer 2 to form a first N-type source region 4 in the drift layer 2, and the ion implantation energy is 100 - 200 kev;

[0055] Step 7: Remove the blocking layer a, reform the blocking layer a, etch the blocking layer a to form a through hole, then etch the drift layer 2 and the first P-type well region 3 until the upper side of the shielding layer 23 to form a groove 22, perform dry oxidation on the groove 22 to form a gate dielectric layer 5, and the gate dielectric layer 5 is provided with a groove 51;

[0056] Step 8: Remove the blocking layer a, reform the blocking layer a, etch the blocking layer a to form a through hole, deposit metal to form a gate metal layer 7;

[0057] Step 9: Remove the blocking layer a, reform the blocking layer a, etch the blocking layer a to form a through hole, etch the drift layer 2 to an etching depth of 900 nm, deposit metal to form a first source metal region 61;

[0058] Step 10: Remove the blocking layer a, reform the blocking layer a, etch the blocking layer a to form a through hole, etch the drift layer 2 to an etching depth of 300 nm, deposit metal to form a second source metal region 62, the source metal layer 6 includes the first source metal region 61 and the second source metal region 62, remove the blocking layer a, and complete the preparation.

[0059] The depth of the groove 22 is 200 nm; the distance L1 from the inner sidewall of the second N-type source region 211 to the inner sidewall of the second P-type well region 21 is 10 nm; the distance L2 from the outer sidewall of the second N-type source region 211 to the outer sidewall of the second P-type well region 21 is 60 nm.

[0060] The silicon carbide substrate 1 and the drift layer 2 are both N-type, and the shielding layer 23 is P-type; the doping concentration of the silicon carbide substrate 1 is 5e18 cm -3 , the doping concentration of the drift layer 2 is 2e17 cm -3 , the doping concentration of the shielding layer 23 is 1e18 cm -3, the doping concentration of the second P-type well region 21 is 5e17 cm -3 , the doping concentration of the second N-type source region 211 is 8e18 cm -3 , the doping concentration of the first P-type well region 21 is 5e17 cm -3 , the doping concentration of the first N-type source region 211 is 8e18 cm -3 , the gate metal layer 7 is an alloy of Ni and Al with a ratio of 2:8; the source metal layer 6 is an alloy of Ni and Al with a ratio of 2:8.

[0061] The thickness of the N-type silicon carbide substrate 1 of the device is 1 μm, the thickness of the N-type drift layer 2 is 20 - 30 μm, the thickness of the P-type shield gate 23 is 200 nm, the thickness of the second P-type well region 21 is 300 nm, the thickness of the second N-type source region 211 is 200 nm, the distance L1 between the most distal end on the side of the second P-type well region 21 close to the gate and the most distal end on the side of the second N-type source region 211 close to the gate is 10 nm, the other side L2 is 60 nm, the bottom thickness of the gate dielectric layer 5 is 30 nm, the sidewall thickness is 20 nm, the thickness of the first P-type well region 3 is 300 nm, the thickness of the first N-type source region 4 is 300 nm, the thickness from the top of the source metal layer 6 to the top of the N-type drift layer 2 and the second P-type well region 21 and the second N-type source region 211 is 900 nm, the thickness from the top of the source metal layer 6 to the top of the first N-type source region 4 is 300 nm, the thickness of the gate metal layer 7 is 1100 nm, and the breakdown voltage of the device is 1200 - 3000 V;

[0062] The concentration of the N-type silicon carbide substrate 1 is for forming a low-resistance ohmic contact with the drain metal layer 8 to reduce the on-resistance of the device, and its thickness is for ensuring support during device epitaxy and improving process stability. The thickness and doping concentration of the P-type shield layer 23 are a compromise based on achieving the gate protection ability. The best effect is that the lower the doping concentration, the better, and the thinner the thickness, the better, because to achieve the protection ability, these two relationships affect each other and are compromised. The thickness and doping ability of the second P-type well region 21 are related to the depth of the gate metal layer 7 to improve the control ability of the gate over the second P-type well region 21 and the second N-type source region 211. The lateral width relationship between the second P-type well region 21 and the second N-type source region 211 is that under this structural condition, the control ability of the gate over the second P-type well region 21 and the second N-type source region 211 is weak, and the thin second P-type well region 211 close to the gate side can improve the gate control ability. The doping concentration and thickness design of the first P-type well region 3 are for ensuring the gate control ability of the device over the first P-type well region 3. The doping concentration of the N-type drift layer 2 is a compromise considering the breakdown voltage and on-resistance of the device. The first N-type source region 4 is for achieving an ohmic contact with the source metal layer 6. Under the control of the gate metal layer 7, the second P-type well region 21 and the second N-type source region 211 can provide a large number of electrons inside the drift layer when the device is conducting, thereby reducing the on-resistance of the device.

[0063] The device constructs a direct contact between the source metal layer 6 and the N-type drift layer 2, thereby forming a Schottky contact, constructing a parasitic Schottky diode, which can reduce the body diode voltage drop of the device and improve the reverse recovery speed of the device.

[0064] Although the specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments we described are illustrative rather than used to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered by the scope protected by the claims of the present invention.

Claims

1. A low on-resistance trench-gate silicon carbide VDMOS, characterized in that, Comprising: A silicon carbide substrate, A drift layer, the lower side surface of which is connected to the upper side surface of the silicon carbide substrate; A second P-type well region is provided in the drift layer, a second N-type source region is provided in the second P-type well region, a groove is provided on the drift layer, and a shielding layer is provided in the drift layer, and the shielding layer is located at the bottom of the groove; A first P-type well region, the lower side surface of which is connected to the drift layer, the second P-type well region, and the second N-type source region; A first N-type source region, the lower side surface of which is connected to the upper side surface of the first P-type well region; A gate dielectric layer, the lower part of which is provided in the groove, the outer side walls of the gate dielectric layer are respectively connected to the first N-type source region, the first P-type well region, and the drift layer, and a trench is provided in the gate dielectric layer; A source metal layer, which is respectively connected to the first N-type source region, the first P-type well region, the drift layer, the second P-type well region, and the second N-type source region; A gate metal layer, which is provided in the trench; And a drain metal layer, which is connected to the lower side surface of the silicon carbide substrate.

2. The low on-resistance trench-gate silicon carbide VDMOS according to claim 1, characterized in that The bottom thickness of the gate dielectric layer is 30 nm, and the side wall thickness is 20 nm.

3. A low on-resistance trench-gate silicon carbide VDMOS according to claim 1, characterized in that, The depth of the groove is 200 nm.

4. A low on-resistance trench-gate silicon carbide VDMOS as claimed in claim 1, wherein, The thickness of the shielding layer is 200 nm.

5. A low on-resistance trench-gate silicon carbide VDMOS as claimed in claim 1, wherein The distance from the inner side wall of the second N-type source region to the inner side wall of the second P-type well region is 10 nm; the distance from the outer side wall of the second N-type source region to the outer side wall of the second P-type well region is 60 nm.

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