Planar gate silicon carbide VDMOS capable of improving short circuit reliability
By designing a two-layer gate dielectric structure and an N-type low-resistance region in silicon carbide VDMOS, combined with nickel-tungsten alloy metal, the device damage caused by heat concentration during short circuit is solved, and the thermal conductivity and device reliability of the insulating medium are improved.
Patent Information
- Application Number
- CN202422198983.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-06
- Publication Date
- 2025-07-08
- Estimated Expiration
- 2034-09-06
AI Technical Summary
When the silicon carbide VDMOS is short-circuited, the device is damaged due to heat concentration, and the prior art is difficult to effectively improve its thermal reliability and thermal conduction ability of the insulating medium.
A two-layer gate dielectric structure was designed, in which the first gate dielectric layer is silicon dioxide and the second gate dielectric layer is diamond. Combined with the N-type low-resistance region and the N-type current-sharing region, a nickel-tungsten alloy is used as the metal layer to construct an N-type drift layer to uniformly distribute heat.
It improves the thermal conduction ability and thermal reliability of the insulating medium of the device, avoids heat concentration, enhances the metal reliability of the device, protects the gate structure, and improves the device reliability during short circuits.
Smart Images
Figure CN223080391U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a planar-gate silicon carbide VDMOS for improving short-circuit reliability. Background Art
[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices and has wide applications in fields such as electric vehicles, aerospace, and power conversion. For silicon carbide power VDMOS, the performance requirements for the device vary in different fields, but generally, the overall requirements include lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage shock reliability, short-circuit reliability, etc.), and lower body diode conduction loss.
[0003] In applications such as motor control systems or load switches, when the motor or load is short-circuited, it will cause the VDMOS to be directly connected to the bus voltage. Since the VDMOS is in the on state at this time, an instantaneous short-circuit current of hundreds of amperes will be generated, resulting in a very large internal transient temperature rise and damaging the device. Summary of the Utility Model
[0004] The technical problem to be solved by the utility model is to provide a planar-gate silicon carbide VDMOS for improving short-circuit reliability, which effectively improves the heat conduction ability and thermal reliability of the insulating medium.
[0005] The utility model is realized as follows: A planar-gate silicon carbide VDMOS for improving short-circuit reliability, comprising:
[0006] A silicon carbide substrate,
[0007] A drift layer, the lower side of the drift layer is connected to the upper side of the silicon carbide substrate;
[0008] A current-sharing layer, the lower side of the current-sharing layer is connected to the upper side of the drift layer; a groove is provided in the current-sharing layer;
[0009] A low-resistance region, the low-resistance region is provided in the groove, and the lower sides of the current-sharing layer are all connected to the current-sharing layer;
[0010] A P-type well region, the P-type well region is provided in the groove, the outer side of the P-type well region is connected to the current-sharing layer, the inner side of the P-type well region is connected to the outer side of the low-resistance region, and the lower side of the P-type well region is connected to the current-sharing layer; an N-type source region and a P-type source region are provided in the P-type well region, and the N-type source region is connected to the P-type source region;
[0011] A first gate dielectric layer, the lower side of the first gate dielectric layer is respectively connected to the N-type source region, the P-type well region, and the low-resistance region;
[0012] A second gate dielectric layer, the second gate dielectric layer is connected to the first gate dielectric layer;
[0013] A source metal layer, which is respectively connected to the current-sharing layer, the P-type well region, the N-type source region, and the P-type source region;
[0014] A gate metal layer, which is connected to the second gate dielectric layer;
[0015] And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.
[0016] The advantages of the present utility model are as follows:
[0017] First, the present utility model designs the gate insulating dielectric for the problem of gate structure degradation during short circuit. The gate dielectric is designed as two layers. The first gate dielectric layer is traditional silicon dioxide to ensure good contact with the silicon carbide interface and reduce the interface state density. The second gate dielectric layer is diamond, which can effectively improve the thermal conductivity and thermal reliability of the insulating dielectric;
[0018] Second, the present utility model constructs an N-type low-resistance region in the JFET region, which can effectively reduce the on-resistance of the JFET region, avoid heat concentration in the JFEF region during short circuit, and distribute it in the N-type drift layer with a larger resistance, avoiding heat concentration and effectively protecting the gate structure and suppressing heat concentration;
[0019] Third, since heat accumulates in a very short time during device short circuit, the source metal aluminum of traditional devices is prone to melting and flowing towards the gate structure, affecting the reliability of the device. The present utility model uses nickel-tungsten alloy to effectively improve the metal reliability of the device;
[0020] Fourth, in order to avoid heat concentration in the JFET and its lower region during device short circuit, an N-type current-sharing region is constructed to evenly distribute the current from the JFET region to the inside of the device, move the heat concentration region to the N-type drift region near the drain region, and improve the reliability of the device. Description of the Drawings
[0021] The following further describes the present utility model with reference to the accompanying drawings in conjunction with embodiments.
[0022] Figure 1 It is a schematic diagram of a planar-gate silicon carbide VDMOS for improving short-circuit reliability of the present utility model.
[0023] Figure 2 It is a process cross-section of a planar-gate silicon carbide VDMOS for improving short-circuit reliability of the present utility model Figure 1 .
[0024] Figure 3 It is a process cross-section of a planar-gate silicon carbide VDMOS for improving short-circuit reliability of the present utility model Figure 2 .
[0025] Figure 4 Process cross - section of a planar - gate silicon carbide VDMOS for improving short - circuit reliability of the present utility model Figure 3 。
[0026] Figure 5 Process cross - section of a planar - gate silicon carbide VDMOS for improving short - circuit reliability of the present utility model Figure 4 。
[0027] Figure 6 Process cross - section of a planar - gate silicon carbide VDMOS for improving short - circuit reliability of the present utility model Figure 5 。
[0028] Figure 7 Process cross - section of a planar - gate silicon carbide VDMOS for improving short - circuit reliability of the present utility model Figure 6 。
[0029] Figure 8 Process cross - section of a planar - gate silicon carbide VDMOS for improving short - circuit reliability of the present utility model Figure 7 。
[0030] Figure 9 Process cross - section of a planar - gate silicon carbide VDMOS for improving short - circuit reliability of the present utility model Figure 8 。
[0031] Figure 10 Process cross - section of a planar - gate silicon carbide VDMOS for improving short - circuit reliability of the present utility model Figure 9 。
[0032] Figure 11 Process cross - section of a planar - gate silicon carbide VDMOS for improving short - circuit reliability of the present utility model Figure 10 。 Detailed implementation manners
[0033] To facilitate the understanding of this application, the following will provide a more comprehensive description of this application with reference to the relevant drawings. Embodiments of this application are given in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of this application more thorough and comprehensive.
[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0035] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "in contact with", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present utility model, the first element, component, region, layer, doping type, or portion discussed below may be denoted as the second element, component, region, layer, or portion.
[0036] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that in addition to the orientation depicted in the figures, spatial relationship terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "below" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. Additionally, the device may also have other orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.
[0037] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprise / include" or "have", etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.
[0038] As Figure 1 shown, an embodiment of the present application provides a planar-gate silicon carbide VDMOS for improving short-circuit reliability, including:
[0039] a silicon carbide substrate 101,
[0040] The drift layer 102, the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101;
[0041] The current sharing layer 103, the lower side of the current sharing layer 103 is connected to the upper side of the drift layer 102; a groove (not shown in the figure) is provided in the current sharing layer 103;
[0042] The low resistance region 104 is provided in the groove, and the lower side of the current sharing layer 104 is connected to the current sharing layer 103;
[0043] The P-type well region 105 is provided in the groove, the outer side of the P-type well region 105 is connected to the current sharing layer 103, the inner side of the P-type well region 105 is connected to the outer side of the low resistance region 104, and the lower side of the P-type well region 105 is connected to the current sharing layer 103; an N-type source region 1051 and a P-type source region 1052 are provided in the P-type well region 105, and the N-type source region 1051 is connected to the P-type source region 1052;
[0044] The first gate dielectric layer 106, the lower side of the first gate dielectric layer 106 is respectively connected to the N-type source region 1051, the P-type well region 105, and the low resistance region 104;
[0045] The second gate dielectric layer 107 is connected to the first gate dielectric layer 106;
[0046] The source metal layer 108 is respectively connected to the current sharing layer 103, the P-type well region 105, the N-type source region 1051, and the P-type source region 1052;
[0047] The gate metal layer 109 is connected to the second gate dielectric layer 107;
[0048] And, the drain metal layer 110 is connected to the lower side of the silicon carbide substrate 101.
[0049] As Figures 1 to 11 shown, the preparation method of the above planar gate silicon carbide VDMOS includes the following steps:
[0050] Step 1, deposit metal on the lower side of the silicon carbide substrate 101 to form the drain metal 110; epitaxially grow on the upper side of the silicon carbide substrate 101 to form the drift layer 102;
[0051] Step 2, form the current sharing layer 103 by ion implantation into the drift layer 102, and the ion implantation energy is 10 - 300 kev;
[0052] Step 3: Form a blocking layer a on the drift layer 102, etch the blocking layer a to form a through hole, perform ion implantation on the current-sharing layer 103 to form a P-type well region 105, and the ion implantation energy is 10 - 200 kev;
[0053] Step 4: Remove the original blocking layer a, reform the blocking layer a, etch the blocking layer a to form a through hole, perform ion implantation on the current-sharing layer 103 to form a low-resistance region 104, and the ion implantation energy is 10 - 200 kev;
[0054] Step 5: Remove the original blocking layer a, reform the blocking layer a, etch the blocking layer a to form a through hole, perform ion implantation on the P-type well region 105 to form an N-type source region 1051, and the ion implantation energy is 10 - 100 kev;
[0055] Step 6: Remove the original blocking layer a, reform the blocking layer a, etch the blocking layer a to form a through hole, perform ion implantation on the P-type well region 105 to form a P-type source region 1052, and the ion implantation energy is 10 - 100 kev;
[0056] Step 7: Remove the original blocking layer a, reform the blocking layer a, etch the blocking layer a to form a through hole, and deposit to form a first gate dielectric layer 106;
[0057] Step 8: Deposit to form a second gate dielectric layer 107, and the deposition materials of the first gate dielectric layer 106 and the second gate dielectric layer 107 are different;
[0058] Step 9: Remove the original blocking layer a, reform the blocking layer a, etch the blocking layer a to form a through hole, deposit metal to form a gate metal layer 109;
[0059] Step 10: Remove the original blocking layer a, reform the blocking layer a, etch the blocking layer a to form a through hole, deposit metal to form a source metal layer 108, and remove the blocking layer a to complete the preparation.
[0060] In this embodiment, preferably, the first gate dielectric layer 106 is silicon dioxide, and the second gate dielectric layer 107 is diamond.
[0061] In this embodiment, preferably, the doping concentration of the low-resistance region 104 is greater than that of the current-sharing layer 103.
[0062] In this embodiment, preferably, the thickness of the first gate dielectric layer 106 is less than that of the second gate dielectric layer 107.
[0063] In this embodiment, preferably, the thickness of the P-type well region 105 is twice that of the N-type source region 1051.
[0064] In this embodiment, preferably, the thickness of the current-sharing layer 103 is three times that of the N-type source region 1051.
[0065] In this embodiment, preferably, the thickness of the low-resistance region 104 is equal to the thickness of the P-well region 105.
[0066] In another embodiment, the silicon carbide substrate 101 is N-type with a doping concentration of 2e18 cm -3 ; the drift layer 102 is N-type with a doping concentration of 1e16 cm -3 ; the current-sharing layer 103 is N-type with a doping concentration of 1e17 cm -3 ; the doping concentration of the P-well region 105 is 5e17 cm -3 ; the low-resistance region 104 is N-type with a doping concentration of 1e18 cm -3 , the material of the first gate dielectric layer 106 is silicon dioxide, the material of the second gate dielectric layer 107 is diamond, the doping concentration of the N-type source region 1051 is 2e18 cm -3 , the doping concentration of the P-type source region 1052 is 1e19 cm -3 ;
[0067] The concentration of the N-type silicon carbide substrate 101 is to ensure a low-resistance ohmic contact with the drain metal layer 110 and reduce the overall on-resistance of the device; the doping concentration of the N-type drift layer 102 is a trade-off between the reverse breakdown voltage and the on-resistance of the device, and the doping concentration of the N-type current-sharing layer 103 is to reduce the on-resistance of the device while forming a Schottky metal rather than an ohmic contact with the source metal layer 108; the N-type low-resistance region 104 is to reduce the resistance of the JFET region of the device and avoid the heat generation in this region from affecting the reliability of the device gate structure, and the doping concentrations of the N-type source region 1051 and the P-type source region 1052 are to form an ohmic contact with the source metal and reduce the contact resistance.
[0068] The thickness of the N-type silicon carbide substrate 101 of the device is 1 μm, the thickness of the N-type drift layer 102 is 15 - 25 μm, which is adjusted within the above range according to different requirements for the breakdown voltage characteristics of the device. The thickness of the N-type current-sharing layer 103 below the P-well region 105 is 300 nm, the thickness of the N-type current-sharing layer 103 from the contact region with the source metal layer 108 to the upper side of the drift layer 102 is 900 nm, and the width of the contact surface of the N-type current-sharing layer 103 with the source metal layer 108 is 200 nm - 300 nm, which can be designed separately according to the freewheeling ability of the body diode. The N-type current-sharing layer 103 can effectively shield the capacitance effect of the gate on the drain, reduce the gate-drain charge of the device, and improve the switching speed of the device. The thickness of the P-well region 105 is 600 nm, the thickness of the first gate dielectric layer 106 is 20 nm, the thickness of the second gate dielectric layer 107 is 30 nm, the thickness of the P-type source region 1052 is 300 nm, and the thickness of the N-type source region 1051 is 300 nm;
[0069] The present utility model designs the gate insulating dielectric for the problem of gate structure degradation existing during short circuit. The gate dielectric is designed into two layers, namely a first gate dielectric layer 106 and a second gate dielectric layer 107. The first gate dielectric layer 106 is silicon dioxide to ensure good contact with the silicon carbide interface, reduce the interface state density, and improve the consistency of the device threshold voltage and switching characteristics. The second gate dielectric layer 107 is diamond, which can effectively improve the heat conduction ability and thermal reliability of the insulating dielectric;
[0070] Since heat accumulates within a very short time when the device is short-circuited, the source metal aluminum of traditional devices is prone to heat melting and flowing towards the gate structure, affecting the reliability of the device. The present utility model uses nickel-tungsten alloy for both the source metal layer, drain metal layer, and gate metal layer, effectively improving the metal reliability of the device.
[0071] Although the specific embodiments of the present utility model have been described above, those skilled in the art should understand that the specific embodiments we described are illustrative rather than used to limit the scope of the present utility model. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present utility model should all be covered by the scope protected by the claims of the present utility model.
Claims
1. A planar-gate silicon carbide VDMOS for improving short-circuit reliability, characterized in that: Comprising: A silicon carbide substrate, A drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate; A current sharing layer, the lower side of which is connected to the upper side of the drift layer; grooves are provided in the current sharing layer; A low-resistance region, which is provided in the groove, and the lower sides of the current sharing layer are all connected to the current sharing layer; A P-type well region, which is provided in the groove, the outer side of the P-type well region is connected to the current sharing layer, the inner side of the P-type well region is connected to the outer side of the low-resistance region, and the lower side of the P-type well region is connected to the current sharing layer; an N-type source region and a P-type source region are provided in the P-type well region, and the N-type source region is connected to the P-type source region; A first gate dielectric layer, the lower side of which is respectively connected to the N-type source region, the P-type well region, and the low-resistance region; A second gate dielectric layer, which is connected to the first gate dielectric layer; A source metal layer, which is respectively connected to the current sharing layer, the P-type well region, the N-type source region, and the P-type source region; A gate metal layer, which is connected to the second gate dielectric layer; And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.
2. The planar-gate silicon carbide VDMOS for improving short-circuit reliability according to claim 1, wherein: The thickness of the first gate dielectric layer is less than the thickness of the second gate dielectric layer.
3. A planar-gate silicon carbide VDMOS for improving short-circuit reliability as claimed in claim 1, wherein: The thickness of the P-type well region is twice the thickness of the N-type source region.
4. The planar-gate silicon carbide VDMOS for improving short-circuit reliability according to claim 1, wherein: The thickness of the current sharing layer is three times the thickness of the N-type source region.
5. The planar-gate silicon carbide VDMOS for improving short-circuit reliability according to claim 1, wherein: The thickness of the low-resistance region is equal to the thickness of the P-type well region.