Zener diode with groove structure

Abstract

The utility model relates to the technical field of semiconductor power devices, in particular to a voltage stabilizing diode with a groove structure. Comprising a first conductive type negative electrode region, a first conductive type epitaxial layer and a second conductive type positive electrode region, and further comprises a groove which is formed in the first conductive type epitaxial layer and extends into the first conductive type epitaxial layer from the top of the first conductive type epitaxial layer; the passivation layer is located above the first conductive type epitaxial layer, the second conductive type anode region and the groove; the TEOS layer is filled in the trench and above the passivation layer; the contact hole penetrates through the TEOS layer and the passivation layer and extends to the second conductive type anode region; the metal layer is evaporated and deposited in the contact hole and extends to the upper part of the TEOS layer; the silicon nitride layer is located above the TEOS layer and wraps the edge of the metal layer; and the bonding region is positioned on the metal layer. The trench structure is added to effectively replace a subsurface breakdown structure, so that the withstand voltage reliability of the device is improved, and the dynamic resistance is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor power devices, in particular to a zener diode with a trench structure. Background Art

[0002] At present, the device structure of zener diodes is mainly a planar structure. For an ordinary planar-structured zener diode, the PN junction depth is relatively shallow, the junction edge is curved and the diffusion concentration has a large discreteness, resulting in a relatively strong electric field at the PN junction edge, poor stability of the breakdown characteristics, a small safe operating area of the device, and the device is easily damaged. In addition, there are some defects at the silicon dioxide-silicon interface on the semiconductor surface, leading to the emergence of surface energy levels. For example, a large number of surface states and interface states are formed due to surface damage and periodic interruption of the silicon dioxide-silicon interface, fixed charges caused by oxygen vacancies during the thermal oxidation process, and mobile charges caused by sodium ion contamination, etc. The PN junctions fabricated by ordinary planar processes are generally surface breakdowns, thus being greatly affected by the surface state, with a relatively large reverse leakage current, so the voltage discreteness is large during breakdown. At the same time, it also brings an increase in the dynamic resistance characteristics, thus affecting the voltage regulation effect. Summary of the Utility Model

[0003] Aiming at the defects of the prior art, the utility model provides a zener diode with a trench structure, which reduces the dynamic resistance of the device and improves the stability of the breakdown characteristics of the device.

[0004] To solve the above technical problems, the technical solution adopted by the utility model is: a zener diode with a trench structure, which includes a first-conductivity-type negative electrode region, a first-conductivity-type epitaxial layer located above the first-conductivity-type negative electrode region, and a second-conductivity-type anode region located above the first-conductivity-type epitaxial layer. It also includes a trench, which is opened on the first-conductivity-type epitaxial layer and extends from the top of the first-conductivity-type epitaxial layer to the inside of the first-conductivity-type epitaxial layer; a passivation layer, which is located above the first-conductivity-type epitaxial layer, the second-conductivity-type anode region and the trench; a TEOS layer, which is filled in the trench and above the passivation layer; a contact hole, which penetrates through the TEOS layer and the passivation layer and extends to the second-conductivity-type anode region; a metal layer, which is evaporated and deposited in the contact hole, the bottom of the metal layer extends above the second-conductivity-type anode region, and the top of the metal layer is located above the TEOS layer; silicon nitride

[0005] Further, a second-conductivity-type impurity is implanted at the central position above the first-conductivity-type epitaxial layer to form the second-conductivity-type anode region, and the trench surrounds the outside of the second-conductivity-type anode region.

[0006] Further, the contact hole is located at the center of the TEOS layer and the passivation layer, and the metal layer is located at the center of the silicon nitride layer.

[0007] Furthermore, the trench is formed by etching on the second-conductivity-type epitaxial layer, and the depth of the trench is 5 - 15 μm.

[0008] Furthermore, the passivation layer is formed by deposition, and the thickness is 100 - 200 nm.

[0009] Furthermore, the TEOS layer is a silicon dioxide layer prepared from tetraethyl orthosilicate and is formed by deposition, with a thickness of 700 - 900 nm.

[0010] Furthermore, the silicon nitride layer is formed by deposition, and the thickness is 200 - 600 nm.

[0011] Advantages of the present utility model: The present utility model provides a zener diode with a trench structure. When the device operates in reverse, by adding the trench structure, the curvature of the electric field at the edge of the PN junction can be reduced, and the edge electric field strength can be decreased, thereby increasing the breakdown voltage.

[0012] By adding the trench structure, breakdown can occur inside, thereby improving the reliability of the device.

[0013] By adding the trench structure, the potential curvature becomes smaller, so the breakdown curve is steeper, the dynamic resistance is reduced, and the performance of the zener diode is improved.

[0014] In summary, the present utility model adds a trench structure to the traditional planar zener diode device structure, which can effectively replace the subsurface breakdown structure. At the same time, the breakdown voltage reliability of the device is improved, and the dynamic resistance is effectively reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic structural diagram of the present utility model;

[0016] Figure 2 is a schematic diagram of a silicon dioxide mask synthesized by hydrogen and oxygen;

[0017] Figure 3 is a schematic diagram of the second-conductivity-type anode ion implantation;

[0018] Figure 4 is a schematic diagram of the second-conductivity-type impurity high-temperature drive-in;

[0019] Figure 5 is a schematic diagram of the trench etching;

[0020] Figure 6 is a schematic diagram of the photoresist mask stripping and the silicon dioxide mask stripping;

[0021] Figure 7 is a schematic diagram of the formation of the sacrificial oxide layer;

[0022] Figure 8Schematic diagram for removing sacrificial oxide layer;

[0023] Figure 9 Schematic diagram for depositing passivation layer;

[0024] Figure 10 Schematic diagram for depositing TEOS layer;

[0025] Figure 11 Schematic diagram for etching contact holes;

[0026] Figure 12 Schematic diagram for depositing metal layer;

[0027] Figure 13 Schematic diagram for etching metal layer;

[0028] Figure 14 Schematic diagram for depositing silicon nitride layer;

[0029] Figure 15 Schematic diagram for etching silicon nitride layer;

[0030] In the figure: 1. N-type negative region of the first conductivity type, 2. N-type epitaxial layer of the first conductivity type, 3. P-type anode region of the second conductivity type, 4. Trench, 5. Passivation layer, 6. TEOS layer, 7. Contact hole, 8. Metal layer, 9. Silicon nitride layer, 10. Bonding region, 11. Silicon dioxide mask, 12. Photoresist mask, 13. Sacrificial oxide layer. Detailed implementation mode

[0031] The present utility model will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0032] Embodiment 1

[0033] This embodiment discloses a voltage stabilizing diode with a trench structure, as Figure 1 shown, which includes an N-type negative region 1 of the first conductivity type, an N-type epitaxial layer 2 of the first conductivity type located above the N-type negative region 1 of the first conductivity type, and a P-type anode region 3 of the second conductivity type located above the N-type epitaxial layer 2 of the first conductivity type. It also includes a trench 4 opened on the N-type epitaxial layer 2 of the first conductivity type and extending from the top of the N-type epitaxial layer 2 of the first conductivity type to the inside along the N-type epitaxial layer 2 of the first conductivity type; a passivation layer 5 located above the N-type epitaxial layer 2 of the first conductivity type, the P-type anode region 3 of the second conductivity type, and the trench 4; a TEOS layer 6 which is silicon dioxide prepared by tetraethyl orthosilicate and filled in the trench 4 and above the passivation layer 5; a contact hole 7 penetrating through the TEOS layer 6 and the passivation layer 5 and extending to the P-type anode region 3 of the second conductivity type; a metal layer 8 deposited by evaporation in the contact hole 7, the bottom of the metal layer 8 extending above the P-type anode region 3 of the second conductivity type, and the top of the metal layer 8 located above the TEOS layer 6; a silicon nitride layer 9 located above the TEOS layer 6 and covering the edge of the metal layer 8; and a bonding region 10 located above the metal layer 8.

[0034] In this embodiment, a second-conductivity-type anode region 3 is formed by implanting second-conductivity-type impurities at the central position above the first-conductivity-type epitaxial layer 2, and the trench 4 surrounds the outside of the second-conductivity-type anode region 3. The contact hole 7 is located at the center of the TEOS layer 6 and the passivation layer 5, and the metal layer 8 is located at the center of the silicon nitride layer 9.

[0035] The processing technology of the zener diode described in this embodiment is as follows:

[0036] (1) Hydroxyl synthesis of silicon dioxide mask 11. As Figure 2 shown, hydroxyl synthesis of silicon dioxide mask 11 is carried out above the first-conductivity-type epitaxial layer 2, with a thickness of 300 - 1000 nm. The main process steps include: ① The diffusion furnace is heated to a predetermined temperature; ② The silicon wafer is placed into the diffusion furnace; ③ The diffusion furnace is heated to 900 - 1100 °C; ④ The diffusion furnace is kept at a constant temperature for 20 - 80 min.

[0037] (2) Second-conductivity-type anode ion implantation. As Figure 3 shown, second-conductivity-type impurities are implanted into the central part of the top of the first-conductivity-type epitaxial layer 2 to form the second-conductivity-type anode region 3. The implantation dose is 1×10 15 -1×10 16 / cm 2 , and the implantation energy is 40 - 100 keV.

[0038] (3) Drive-in. As Figure 4 shown, the second-conductivity-type impurities are driven in at a high temperature. The drive-in temperature is 1000 - 1150 °C, and the drive-in time is 3 - 15 h.

[0039] (4) Trench 4 etching. As Figure 5 shown, the trench 4 is formed by dry etching of silicon, and the depth of the trench 4 is 5 - 15 μm. The process steps include: ① Photoresist is deposited, pre-baked, exposed, developed, and hardened to cover a blocking layer on the surface of the silicon wafer; ② Isotropic etching of silicon dioxide is carried out; ③ Isotropic deposition is carried out to cover a blocking layer on the etched silicon surface, sidewalls, and the surface of the photoresist layer; ④ Anisotropic etching is carried out to remove the blocking layer covering the etched surface to expose the etched surface; ⑤ Isotropic etching of silicon is carried out; ⑥ Steps ③, ④, and ⑤ are repeated until the predetermined etching depth is reached.

[0040] (5) Stripping of the photoresist mask 12 and the silicon dioxide mask 11: The photoresist mask 12 is removed until clean using a negative photoresist stripping solution, and the silicon dioxide mask 11 is removed until clean using an etching solution. As Figure 6 shown.

[0041] (6) Sacrificial oxidation. As Figure 7As shown, a sacrificial oxide layer 13 of hydrogen-oxygen synthesis has a thickness of 40 - 60 nm. The process steps include: ① Heating the oxidation furnace to 900 - 1000 °C; ② Holding the temperature for 5 - 15 min.

[0042] (7)Removal of the sacrificial oxide layer 13: Use a 6:1 ammonium fluoride etching solution to remove the silicon dioxide masking layer until clean, as Figure 8 shown.

[0043] (8)Deposition of the passivation layer 5, as Figure 9 shown, deposit a silicon dioxide passivation layer 5 of hydrogen-oxygen synthesis above the first-conductivity-type epitaxial layer 2, the trench 4, and the second-conductivity-type anode region 3, with a thickness of 100 - 200 nm. The process steps include: ① Heating the diffusion furnace to 900 - 1000 °C; ② Holding the temperature for 15 - 50 min.

[0044] (9)Deposition of the TEOS layer 6, as Figure 10 shown, use the LPCVD method to deposit a layer of silicon dioxide above the passivation layer 5 to form the TEOS layer, with a thickness of 700 - 900 nm. The process steps include: ① Heating the diffusion furnace to 600 - 700 °C; ② Holding the temperature for 90 - 110 min.

[0045] (10)Etching of the contact hole 7: As Figure 11 shown, etch the TEOS layer 6 to be clean at the middle position between the TEOS layer 6 and the passivation layer 5, and etch the passivation layer 5 to be clean.

[0046] (11)Deposition of the metal layer 8, as Figure 12 shown, deposit a layer of metal layer 8 above the TEOS layer 6, with a thickness of 0.5 - 2 μm.

[0047] (12)Etching of the metal layer 8, as Figure 13 shown, use a ferric nitrate solution, a mixed solution of deionized water and hydrofluoric acid, and a nitric acid solution to wet-etch silver metal, nickel metal, and titanium metal, and remove the metal layer 8 at the edge part, only retaining the part located in the center.

[0048] (13)Deposition of the silicon nitride layer 9, as Figure 14 shown, deposit a layer of silicon nitride layer 9 above the metal layer 8, with a thickness of 200 - 600 nm.

[0049] (14)Etching of the silicon nitride layer 9, as Figure 15 shown, remove the silicon nitride layer 9 located above the metal layer 8 by etching, only retaining the part located above the TEOS layer 6, and the retained silicon nitride layer 9 covers the edge of the metal layer 8.

[0050] Although the embodiments of the present utility model have been disclosed as above, it is not limited to the applications listed in the specification and embodiments. It can be fully applied to various fields suitable for the present utility model. For those familiar with the field, additional modifications can be easily made. Therefore, without departing from the general concept defined by the claims and the equivalent scope, the present utility model is not limited to the specific details and the illustrated examples here.

Claims

1. A zener diode with a trench structure, comprising a first-conductivity-type cathode region, a first-conductivity-type epitaxial layer located above the first-conductivity-type cathode region, and a second-conductivity-type anode region located above the first-conductivity-type epitaxial layer, characterized in that: It further includes a groove, which is formed on the epitaxial layer of the first conductivity type and extends from the top of the epitaxial layer of the first conductivity type to the inside of the epitaxial layer of the first conductivity type; A passivation layer, which is located above the epitaxial layer of the first conductivity type, the anode region of the second conductivity type and the groove; A TEOS layer, which is filled in the groove and above the passivation layer; A contact hole, which penetrates through the TEOS layer and the passivation layer and extends to the anode region of the second conductivity type; A metal layer, which is evaporated and deposited in the contact hole, the bottom of the metal layer extends above the anode region of the second conductivity type, and the top of the metal layer is located above the TEOS layer; A silicon nitride layer, which is located above the TEOS layer and covers the edge of the metal layer; A bonding region, which is located above the metal layer.

2. The zener diode with a groove structure according to claim 1, characterized in that: The anode region of the second conductivity type is formed by implanting impurities of the second conductivity type at the central position above the epitaxial layer of the first conductivity type, and the groove surrounds the outside of the anode region of the second conductivity type.

3. The voltage stabilizing diode with a groove structure according to claim 1, wherein: The contact hole is located at the center of the TEOS layer and the passivation layer, and the metal layer is located at the center of the silicon nitride layer.

4. The voltage stabilizing diode with a groove structure according to claim 1, characterized in that: The groove is formed by etching on the epitaxial layer of the second conductivity type, and the depth of the groove is 5 - 15 μm.

5. The voltage stabilizing diode with a groove structure according to claim 1, characterized in that: The passivation layer is formed by deposition, and the thickness is 100 - 200 nm.

6. The zener diode with a groove structure according to claim 1, characterized in that: The TEOS layer is a silicon dioxide layer prepared by using tetraethyl orthosilicate, and is formed by deposition, and the thickness is 700 - 900 nm.

7. The voltage stabilizing diode with a groove structure according to claim 1, characterized in that: The silicon nitride layer is formed by deposition, and the thickness is 200 - 600 nm.

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