Flip LED chip

Abstract

The utility model discloses a flip LED chip, and aims to improve the voltage overload resistance of the LED chip, optimize the current distribution, enhance the light output performance, and improve the structural stability and durability. By designing the conductive through holes made of the DBR or SiO2 material around the N-GaN through hole and optimizing the layout and the diameter of the through holes, the risk of current concentration is remarkably reduced, so that the damage caused by EOS is reduced. In addition, the combination of the metal reflecting layer and the non-metal reflecting layer and the transparent conducting layer are adopted, so that efficient light reflection and excellent electrical performance are realized. The application of the metal protective layer further enhances the environmental stability and durability of the chip. The utility model is suitable for various high-performance illumination and display applications, and can provide excellent photoelectric performance and long-term reliability.

Description

Technical Field

[0001] The utility model relates to the technical field of light-emitting diode (LED) chips, and particularly relates to a flip-chip LED chip. Background Art

[0002] LED technology has become a revolutionary advancement in the lighting industry due to its outstanding energy-saving performance, environmental-friendly characteristics, high safety standards, long-term durability, and low energy consumption advantages. These unique features not only reduce energy consumption but also significantly alleviate the environmental burden, providing a safer and more sustainable lighting solution. The application scope of LEDs is extremely wide, from simple indicator lights to complex displays, from household and commercial decorative lighting to high-efficiency backlights and daily lighting needs, LED technology can provide efficient and reliable solutions. Its diverse application scenarios and superior performance make LEDs one of the first choices for modern lighting technology.

[0003] Electrical overstress (EOS) is a phenomenon caused by current or voltage exceeding the tolerance limit of electronic devices, which is particularly critical in the LED field. When an LED is subjected to current or voltage beyond its design standard, it may lead to a reduction in its performance or even irreversible damage. The consequences of an EOS event may be immediate, such as bond wire breakage, breakdown of semiconductor chips or Zener diodes, or component burnout; or they may be delayed, such as damage signs gradually appearing within a period of time after the EOS event occurs. Such damage may result in the early failure of LED devices, affecting their performance and lifespan.

[0004] The causes of EOS are diverse, including but not limited to the instability of power output, electrical noises such as overvoltage and overcurrent, and current surges generated during hot plugging. These situations may all lead to EOS failures and cause damage to LED devices. To minimize the occurrence of such events, it is crucial to take appropriate preventive measures. This includes ensuring power stability, using appropriate overvoltage protection devices, and cautious operation to avoid hot plugging. These measures together ensure the stable operation of LED devices and extend their service life. By understanding the causes and consequences of EOS, we can more effectively take measures to protect LED devices, ensuring that while providing efficient and environmentally friendly lighting solutions, they also have a longer service life cycle and higher reliability.

[0005] In current TV backlight technology, chips with a silver mirror flip-chip structure are becoming increasingly popular due to their excellent reflection efficiency and brightness performance. This technology further improves the reflectivity by adding a distributed Bragg reflector (DBR) or a silicon dioxide (SiO2) layer under the chip's reflective layer, thereby achieving higher brightness. DBR is a multi-layer thin film structure that enhances the reflection of light by alternately stacking materials with different refractive indices. As an efficient reflection-enhancing layer, the SiO2 layer can also effectively improve the light reflectivity. Both methods aim to enhance the brightness performance of the final product.

[0006] To ensure uniform current distribution throughout the chip, designers typically use a method of densely opening holes at equal intervals, as Figure 1 shown. This design aims to promote uniform current transfer, thereby ensuring the uniform brightness and long-term stability of the LED. However, this design sometimes causes current concentration near the N-GaN vias, that is, the current prefers to flow through the paths of these vias rather than being uniformly distributed throughout the chip. This current concentration phenomenon can lead to a higher current density in local areas, thereby increasing the risk of EOS failure. EOS failure may cause a decline in LED performance or even early failure because excessive current density may cause local heating, material degradation, or even damage. Summary of the Invention

[0007] To solve the above problems, the present utility model proposes a flip-chip LED chip with improved voltage overload resistance.

[0008] The technical solution adopted by the present utility model is as follows:

[0009] A flip-chip LED chip, comprising:

[0010] A patterned sapphire substrate;

[0011] An epitaxial layer located on the substrate, the epitaxial layer comprising N-type gallium nitride (N-GaN), a quantum well structure, and P-type gallium nitride (P-GaN);

[0012] A group of N-GaN layer vias formed in the epitaxial layer, prepared by high-precision lithography and etching techniques;

[0013] A transparent conductive layer covering the epitaxial layer, forming an ohmic contact with P-GaN;

[0014] A non-metal reflective layer located above the transparent conductive layer, which contains a plurality of hollow vias. The hollow vias are arranged in a uniform and equidistant manner in the area close to the N-GaN vias, and their diameter is 1.2 to 2.5 times larger than the vias in other areas;

[0015] A metal conductive reflective layer, covering the non-metal reflective layer and the hollow through-hole, and achieving electrical connection with P-GaN through the transparent conductive layer.

[0016] A metal protective layer, covering the top surface and side walls of the metal conductive reflective layer;

[0017] The first non-metal passivation layer, covering the metal protective layer;

[0018] The first electrode, penetrating the first non-metal passivation layer to connect with N-GaN;

[0019] The second non-metal passivation layer, covering the first electrode and the first non-metal passivation layer;

[0020] The second electrode, penetrating the second non-metal passivation layer to connect to the first electrode and P-GaN.

[0021] Wherein the material of the transparent conductive layer is indium tin oxide (ITO) or zinc oxide (ZnO), and its thickness is set between 5 nanometers and 200 nanometers.

[0022] The distance between the edge of the hollow through-hole and the edge of the N-GaN through-hole is between 5μm and 50μm.

[0023] Wherein the non-metal reflective layer is selected from SiO2, MgF2, MgO, Al2O3, HfO2, BaF2 or AlF3, and the film thickness is 50nm to 5000nm; or the DBR reflective stack technology is adopted, wherein the stack is an alternating high and low reflectivity film layer, the number of film layers is greater than or equal to 3 layers, the manufacturing temperature is 100°C to 300°C, and the film layer thickness is 100nm to 6000nm.

[0024] Wherein the metal conductive reflective layer uses silver (Ag) as the material, and the thickness is 80 - 300nm.

[0025] Preferably, a metal adhesion layer not exceeding 10 nanometers is added under the metal conductive reflective layer, and the selected material is chromium (Cr), titanium (Ti) or nickel (Ni).

[0026] The material of the metal protective layer is selected from aluminum (Al), titanium (Ti), nickel (Ni), platinum (Pt), gold (Au), chromium (Cr) or titanium tungsten (TiW), and the total thickness range is 50 nanometers to 5000 microns.

[0027] The non-metal reflective layer adopts a low reflectivity thin film or the DBR reflective stack technology.

[0028] The material of the metal protective layer is selected from aluminum (Al), titanium (Ti), nickel (Ni), platinum (Pt), gold (Au), chromium (Cr), or titanium tungsten alloy (TiW), and the total thickness is between 50 nanometers and 5000 micrometers.

[0029] The first and second non-metallic passivation layers respectively use SiO2, Si3N4, or the alternating growth of the two as the insulating passivation layer; or a DBR stack is selected, with the number of film layers ≥ 3, the production temperature is 100 - 300 °C, and the film layer thickness is 100 nm - 6000 nm.

[0030] The technological progress and beneficial effects achieved by the above technical solutions mainly include:

[0031] 1. Improve the anti-EOS ability: By optimizing the layout and size of the DBR or SiO2 conductive vias around the N-GaN vias, the current is effectively dispersed, reducing the current concentration near the vias, thereby significantly reducing the damage risk caused by EOS. This improvement enables the LED chip to better withstand EOS generation situations such as unstable power output, overvoltage, overcurrent, and noise, enhancing the reliability and lifespan of the product.

[0032] 2. Optimize the current distribution: By setting larger-diameter conductive vias around the N-GaN vias, the current distribution in the chip is further optimized. This design helps to even out the current, avoiding local overheating or stress concentration, thereby improving the overall performance and durability of the LED chip.

[0033] 3. Enhance the reflection efficiency and light output performance: The design of introducing a metal conductive reflection layer (such as using Ag material) and a non-metallic reflection layer in the LED chip, through fine structural layout and material selection, not only enhances the light reflection efficiency but also improves the overall light output performance. In particular, using materials such as DBR or SiO2 to optimize the design of the conductive vias and reflection layer helps to enhance the brightness and efficiency of the light source.

[0034] 4. Improve the structural stability and durability: By adding a metal adhesion layer (such as Cr, Ti, Ni, etc.) under the metal conductive reflection layer, not only the adhesion between the reflection layer and the underlying structure is enhanced, but also additional protection is provided, reducing the negative impact of environmental factors (such as humidity, oxidation) on the performance of the LED chip. At the same time, through fine control of the design of the non-metallic passivation layer and the metal protective layer, the overall stability and durability of the LED chip are further improved. Description of the Drawings

[0035] Figure 1 is a top view of a flip-chip LED chip with a conventional design.

[0036] Figure 2It is a top view of the N-GaN vias (12 pieces) designed in the present utility model.

[0037] Figure 3 It is a top view of the P vias designed in the present utility model.

[0038] Figure 4 It is Figure 3 a detailed view of the P vias in

[0039] Figure 5 It is a cross-sectional structure diagram of the flip-chip LED chip designed in the present utility model. Specific embodiments

[0040] The following provides the preferred embodiments of the present utility model in conjunction with the attached drawings to elaborate in detail on the technical solutions of the present utility model.

[0041] Embodiment:

[0042] As Figure 2-5 shown, the method for fabricating the flip-chip LED chip of the present utility model includes the following steps:

[0043] 1. Epitaxial layer construction: An epitaxial layer including N-type gallium nitride (N-GaN) 200, quantum well structure 300, and P-type gallium nitride (P-GaN) 400 is formed on the patterned sapphire substrate 100.

[0044] 2. MESA etching process: The N-type region is precisely exposed using MESA etching technology.

[0045] 3. Preparation of N-GaN vias: Corresponding patterns are made through photolithography, and then etched using ICP (inductively coupled plasma etching) from P-GaN to N-GaN, with a depth between 0.8 - 1.5 um. N electrode vias 201 are fabricated in the N-type gallium nitride (N-GaN) layer. These vias will serve as channels for injecting metal or other conductive materials later to achieve effective electrical connection with N-GaN.

[0046] 4. Fabrication of isolation region (ISO): The isolation region is created in the patterned sapphire substrate through etching technology, focusing on the middle part of the etching cut-off track to achieve electrical isolation.

[0047] 5. Fabrication of transparent conductive layer 500: It can form an ohmic contact with P-GaN using a planar, patterned mesh, or island layout. The transparent conductive layer is selected from ITO or ZnO, with a thickness between 5 nanometers and 200 nanometers.

[0048] 6. Fabrication of the non-metallic reflective layer 600: The non-metallic reflective layer can be made of a low-reflectivity thin film or a DBR reflective stack technology. The low-reflectivity thin film can be selected from SiO2, MgF2, MgO, Al2O3, HfO2, BaF2, or AlF3, with a film thickness of 50 nm - 5000 nm; DBR reflective stack: The stack is composed of alternating high- and low-reflectivity film layers, with the number of film layers ≥ 3, a fabrication temperature of 100 - 300 °C, and a film layer thickness of 100 nm - 6000 nm. The non-metallic reflective layer is selected to be patterned in a mesh or island distribution, such as Figure 3 shown in the figure. A hollow through-hole is fabricated in the non-metallic reflective layer. The following are the key steps of the present utility model: Adjust the through-holes 501 close to the N-GaN through-hole 201 to be arranged in a uniform and equal-spacing manner, ensuring that the distance (D1) between the edge of the through-hole 501 and the edge of the N-GaN through-hole 201 is between 5 and 50 microns. At the same time, the diameter Φ1 of the through-hole 501 should be 1.2 to 2.5 times the diameter Φ2 of the small hole 502; the small holes 502 are arranged in a mesh pattern with a spacing (D2) of 5 to 50 microns.

[0049] 7. Fabrication of the metal conductive reflective layer 700: Apply Ag as a reflective and conductive layer above the P-GaN, and the thickness of the silver reflective layer needs to exceed 80 nanometers. The metal conductive reflective layer is connected to the transparent conductive layer through the hollow holes of the non-metallic reflective layer to achieve electrical connection with the P-GaN. A metal adhesion layer (such as Cr, Ti, Ni) with a thickness of no more than 10 nanometers can be added under the Ag layer, and metals such as Ni, TiW, Ti, Pt, etc. are used to protect the Ag reflective layer.

[0050] 8. Fabrication of the metal protection layer 800: Expand 1 to 20 microns outward along the contour of the metal conductive reflective layer to cover the top surface and side walls of the metal conductive reflective layer. The laminated material is selected from Al, Ti, Ni, Pt, Au, Cr, or TiW, with a total thickness between 50 nanometers and 5000 microns.

[0051] 9. Fabrication of the first non-metallic passivation layer 900: Use SiO2, Si3N4, or their alternating growth as an insulating passivation layer. The growth temperature of the passivation layer is 150 to 300 °C, and the thickness is between 200 and 2000 nanometers. Or select a DBR stack, with the number of film layers ≥ 3, a fabrication temperature of 100 - 300 °C, and a film layer thickness of 100 nm - 6000 nm, which can achieve insulation and reflection functions. Fabricate N-GaN connection holes on the first non-metallic passivation layer, and fabricate connection holes in the area covered by the metal protection layer above the P-GaN.

[0052] 10. Fabrication of the first electrode 1000: The first electrode is connected to N-GaN through the N-GaN connection hole 901 prepared on the first non-metallic passivation layer, and the connection hole 902 fabricated in the area covered by the metal protection layer above P-GaN is exposed as the P-region electrode through-hole of the first electrode; The electrode includes an adhesion layer and a structural layer. The materials of the adhesion layer include Cr, Ni, or Ti, etc., and the structural layer is selected from Al, Ti, Pt, Ni, or Au, with a total thickness ranging from 50 nanometers to 5000 micrometers.

[0053] 11. Fabrication of the second non-metallic passivation layer 1100: The fabrication method is the same as that of the first metal passivation layer. Connection holes are fabricated above the P-region and N-region of the first electrode through a patterning process to expose the underlying first electrode and its P-region electrode through-hole.

[0054] 12. Fabrication of the second metal electrode 1200: The second metal electrode is connected to the first electrode and its P-region respectively through the connection holes prepared in the previous step. The second electrode consists of three layers: an adhesion layer, a structural layer, and a eutectic layer. The adhesion layer is made of Cr, Ni, or Ti, with a thickness ranging from 0.5 to 100 nanometers, aiming to enhance the adhesion between the electrode and the substrate. The structural layer is made of Al, Ti, Pt, Ni, or Au, with a thickness between 1000 and 5000 nanometers, responsible for the main conductive function of the electrode. The eutectic layer is selected from Au, Sn, or AuSn alloy, with a thickness between 1 and 100 micrometers, used to achieve efficient welding and electrical connection between the electrodes.

[0055] In this embodiment, the flip-chip LED chip exhibits excellent anti-voltage shock ability and uniform current distribution through an optimized structural design, significantly reducing the damage risk caused by current concentration. The chip utilizes a carefully designed reflective layer and through-hole structure, not only improving the light output efficiency but also achieving efficient light extraction, ensuring high reliability and excellent brightness performance. This preparation technology of the flip-chip LED chip, combined with the effective application of the metal reflective layer and protection layer, further optimizes its optical performance and environmental stability, making it an ideal choice in the field of high-performance lighting and display technologies.

Claims

1. A flip-chip LED chip, characterized in that: Comprising: A patterned sapphire substrate (100); An epitaxial layer located on the substrate, the epitaxial layer comprising N-type gallium nitride (200), a quantum well structure (300), and P-type gallium nitride (400); A group of N-GaN layer vias (201) formed in the epitaxial layer; A transparent conductive layer (500) covering the epitaxial layer and forming an ohmic contact with P-GaN; A non-metallic reflective layer (600) located above the transparent conductive layer, which contains a plurality of hollow vias (501), the hollow vias are arranged at uniform equal intervals in the area close to the N-GaN layer vias, and their diameter is 1.2 times to 2.5 times larger than that of the small holes (502); A metal conductive reflective layer (700) covering the non-metallic reflective layer (600) and the hollow vias (501), and realizing electrical connection with P-GaN through the transparent conductive layer; A metal protective layer (800) covering the top surface and side walls of the metal conductive reflective layer (700); A first non-metallic passivation layer (900) covering the metal protective layer (800); A first electrode (1000) penetrating the first non-metallic passivation layer (900) and connecting to N-type gallium nitride (200); A second non-metallic passivation layer (1100) covering the first electrode (1000) and the first non-metallic passivation layer (900); A second electrode (1200) penetrating the second non-metallic passivation layer (1100) and connecting to the first electrode (1000) and P-type gallium nitride (400).

2. The flip-chip LED chip according to claim 1, wherein Wherein the material of the transparent conductive layer is indium tin oxide or zinc oxide, and its thickness is set between 5 nanometers and 200 nanometers.

3. The flip-chip LED chip according to claim 1, wherein, The distance between the edge of the hollow via and the edge of the N-GaN via is between 5 μm and 50 μm.

4. The flip-chip LED chip according to claim 1, wherein Wherein the material selected for the non-metallic reflective layer is SiO2, MgF2, MgO, Al2O3, HfO2, BaF2 or AlF3, and the film thickness is 50 nm to 5000 nm; or the DBR reflective stack technology is adopted, wherein the stack is an alternating high and low reflectivity film layer, the number of film layers is greater than or equal to 3 layers, the production temperature is 100°C to 300°C, and the film layer thickness is 100 nm to 6000 nm.

5. The flip-chip LED chip according to claim 1, characterized in that, Wherein the metal conductive reflective layer uses silver as the material and the thickness is 80 - 300 nm.

6. The flip-chip LED chip according to claim 5, wherein, A metal adhesion layer not exceeding 10 nanometers is added under the metal conductive reflective layer, and the selected materials are chromium, titanium or nickel.

7. The flip-chip LED chip according to claim 1, characterized in that, Wherein the material of the metal protective layer is selected from aluminum, titanium, nickel, platinum, gold, chromium or titanium tungsten alloy, and the total thickness range is 50 nanometers to 5000 microns.

8. The flip-chip LED chip according to claim 1, wherein, Wherein the non-metallic reflective layer adopts a low-reflectivity thin film or the DBR reflective stack technology.

9. The flip-chip LED chip according to claim 1, wherein, Wherein the material of the metal protective layer is aluminum, titanium, nickel, platinum, gold, chromium or titanium tungsten alloy, and the total thickness is between 50 nanometers and 5000 microns.

10. The flip-chip LED chip according to claim 1, wherein, Wherein, the first and second non-metallic passivation layers respectively use SiO2, Si3N4 or the alternate growth of both as the insulating passivation layer; or a DBR stack is selected, the number of film layers ≥ 3 layers, the manufacturing temperature is 100 - 300 °C, and the film layer thickness is 100 nm - 6000 nm.

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