Module communication circuit on Internet of Things equipment
By using inductors and capacitors to replace electrolytic capacitors in IoT devices and using TVS tubes for electrostatic protection, the problems of high cost, large volume and short life of electrolytic capacitors are solved, and cost reduction, volume reduction and reliability improvement are achieved.
Patent Information
- Application Number
- CN202422079717.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-27
- Publication Date
- 2025-07-11
- Estimated Expiration
- 2034-08-27
AI Technical Summary
The electrolytic capacitors used in existing IoT devices are costly, large in size and short in life, which affect the reliability and space utilization of the equipment.
The combination of inductor and capacitor is used to replace the electrolytic capacitor, and TVS tubes are used for electrostatic protection and surge energy absorption, reducing costs, reducing volume and improving reliability.
It achieves cost reduction, volume reduction and reliability improvement, avoids aging and corrosion problems of electrolytic capacitors, and meets the power and power supply stability requirements of the equipment.
Smart Images
Figure CN223093796U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of Internet of Things device circuits, in particular to a module communication circuit on an Internet of Things device. Background Art
[0002] It is known that the Internet of Things is another revolutionary development in the information industry following computers, the Internet, and mobile communications. The Internet of Things has been officially listed as one of the strategically emerging industries that the country focuses on developing. The Internet of Things industry has the characteristics of a long industrial chain and involves multiple industrial clusters, and its application scope almost covers all walks of life. The Internet of Things refers to a huge network formed by combining various information sensing devices to collect any required information of objects or processes that need to be monitored, connected, and interacted in real time with the Internet, aiming to achieve the connection of things to things, things to people, and all items to the network, facilitating identification, management, and control. As Figure 1 shown, in the existing circuit, the C3 capacitor uses an electrolytic capacitor (aluminum electrolytic capacitor) to achieve the function of storage and filtering, which will cause the following defects: First, for the increasingly fierce competition in the current electronic circuit industry, the cost of using an electrolytic capacitor (aluminum electrolytic capacitor) is relatively high and cannot meet modern requirements; Second, due to the higher integration of current electronic circuits, the electrolytic capacitor (aluminum electrolytic capacitor) needs to use a liquid electrolyte, which will result in a relatively large overall volume and is very unsuitable for electronic devices with limited space in terms of space and reliability requirements; Third, the service life of the electrolytic capacitor (aluminum electrolytic capacitor) is limited and relatively short. After a long storage time, the aging and corrosion of the electrolyte may cause the capacitor to fail, seriously affecting the normal use of electronic devices. It is necessary to make improvements in response to the above phenomena. Summary of the Utility Model
[0003] (1) Technical problems to be solved
[0004] In view of the deficiencies in the prior art, the utility model provides a module communication circuit on an Internet of Things device, which reduces costs while maintaining the required power requirements and relatively stable power supply ripple, and both space and reliability can meet the requirements, and the service life will also be greatly improved.
[0005] (2) Technical solutions to be adopted
[0006] In order to achieve the above object, the technical solutions adopted by the utility model are as follows:
[0007] A module communication circuit on an Internet of Things device, including a DC-DC chip U1. The DC-DC chip U1 is connected to an output voltage terminal and an input voltage terminal. Between the DC-DC chip U1 and the output voltage terminal, a first capacitor C1 and an inductor L1 are sequentially arranged. Between the inductor L1 and the output voltage terminal, a first resistor R1 and a second capacitor C2 are sequentially connected. A fifth capacitor C5 is connected in parallel between the inductor L1 and the output voltage terminal. The fifth capacitor C5 is electrically connected to a sixth capacitor C6, and the sixth capacitor C6 is used for the ground terminal. It is characterized in that: the BST pin of the DC-DC chip U1 is sequentially connected to the first capacitor C1. A third capacitor C3 is connected in parallel between the inductor L1 and the output voltage terminal. The third capacitor C3 is connected to a fourth capacitor C4, and the fourth capacitor C4 is connected to the fifth capacitor C5. The ground pin of the DC-DC chip U1 is connected to the ground terminal. The FB pin of the DC-DC chip U1 is respectively connected to the first resistor R1 and the second capacitor C2. Both the first resistor R1 and the second capacitor C2 are connected to a second resistor R2, and the second resistor R2 is connected to the ground terminal. The SW pin of the DC-DC chip U1 is connected to the inductor L1. The VIN pin and the EN pin of the DC-DC chip U1 are both connected to the input voltage terminal.
[0008] Preferably, a seventh capacitor C7 is connected in parallel between the VIN pin of the DC-DC chip U1 and the input voltage terminal. The seventh capacitor C7 is electrically connected to an eighth capacitor C8, and the eighth capacitor C8 is electrically connected to a diode D1. The diode D1 is used for the ground terminal. The EN pin of the DC-DC chip U1 is electrically connected to the seventh capacitor C7.
[0009] Preferably, both the seventh capacitor C7 and the eighth capacitor C8 adopt the capacitor surface mount package 0805, and the capacitance values of both the seventh capacitor C7 and the eighth capacitor C8 are 22 uF.
[0010] Preferably, both the third capacitor C3 and the fourth capacitor C4 connected thereto adopt the capacitor surface mount package 0805.
[0011] Preferably, the capacitance values of both the third capacitor C3 and the fourth capacitor C4 connected thereto are 22 uF.
[0012] Preferably, both the fifth capacitor C5 and the sixth capacitor C6 adopt the capacitor surface mount package 0603. The capacitance value of the fifth capacitor C5 is 0.1 uF, and the capacitance value of the sixth capacitor C6 is 10 pF.
[0013] Preferably, the inductor L1 adopts the model WPN4020H100MT, and the inductance is 4.7 uH.
[0014] Preferably, the first capacitor C1 is in the 0603 chip capacitor package, and the capacitance is 0.1 uF.
[0015] Preferably, the second capacitor C2 is in the 0603 chip capacitor package, and the capacitance is 33 pF.
[0016] Preferably, the specification of the first resistor R1 is 0603 / 100K±1%, and the second resistor R2 is in the 0603 / 27K±1% package.
[0017] (III) Technical effects to be achieved
[0018] Compared with the prior art, the beneficial effects of the present utility model are as follows:
[0019] First, a third capacitor C3 is connected in parallel between the inductor L1 and the output voltage terminal (V-OUT) of the present utility model. The third capacitor C3 is connected to a fourth capacitor C4, and the fourth capacitor C4 is connected to a fifth capacitor C5. Such a third capacitor C3 and a fourth capacitor C4 replace the electrolytic capacitor (aluminum electrolytic capacitor) in the prior art, avoiding the high cost investment of using an electrolytic capacitor (aluminum electrolytic capacitor), and also being beneficial to avoiding the use of a liquid electrolyte for the electrolytic capacitor (aluminum electrolytic capacitor), thereby being beneficial to reducing the overall volume, which has a significant impact on electronic devices with limited space, and the reliability of the electronic device will not be affected at all. Secondly, it is also beneficial to avoid the situation where the service life of the electrolytic capacitor (aluminum electrolytic capacitor) is limited and the aging and corrosion of the electrolyte may cause the capacitor to fail, seriously affecting the normal use of the electronic device, and being more capable of meeting the requirements.
[0020] Second, a seventh capacitor C7 is connected in parallel between the VIN pin of the DC-DC chip U1 of the present utility model and the input voltage terminal. The seventh capacitor C7 is electrically connected to an eighth capacitor C8, and the eighth capacitor C8 is electrically connected to a diode D1. The diode D1 is used for the ground terminal. The EN pin of the DC-DC chip U1 is electrically connected to the seventh capacitor C7. When the device is hot-plugged in the present utility model, the hot-plugging brings electrostatic and surge effects. Using a TVS tube to achieve electrostatic protection and surge energy absorption, for a low working voltage circuit, the TVS tube can instantaneously suppress or absorb the peak voltage or abnormal current pulse energy generated by the electrostatic and surge effects. The waveform shows that the peak voltage is significantly suppressed, and it is more capable of meeting the requirements. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 is a circuit schematic diagram of the present utility model.
[0022] Figure 2 is a schematic diagram of the waveform captured by an oscilloscope before improvement in the prior art.
[0023] Figure 3 This is a schematic diagram reflecting the waveform captured by the oscilloscope after the improvement of the present utility model. Specific embodiments
[0024] In the description of the present utility model, it should be noted that when an element is referred to as "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.
[0025] In the description of the present utility model, it should be noted that the orientation or positional relationship indicated by the terms "center", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of this utility model is usually placed during use. It is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present utility model. In addition, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present utility model, "a plurality" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.
[0026] In the description of the present utility model, it should also be noted that unless otherwise clearly specified and limited, the terms "set", "installed", "connected", "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific situations.
[0027] To make the purpose, technical solutions and advantages of the present utility model clearer, the present utility model will be further described in detail below through the drawings and embodiments. However, it should be understood that the specific embodiments described herein are only used to explain the present utility model and do not limit the scope of the present utility model. In addition, in the following description, the descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present utility model.
[0028] Embodiment 1: Refer to Figure 1 , a module communication circuit on an Internet of Things device, which is applied to a board-level circuit in a DC-DC low working voltage loop. It includes a DC-DC chip U1. The DC-DC chip U1 is connected to an output voltage terminal (V-OUT) and an input voltage terminal (V-IN). A first capacitor C1 and an inductor L1 are sequentially arranged between the DC-DC chip U1 and the output voltage terminal (V-OUT). A first resistor R1 and a second capacitor C2 are sequentially connected between the inductor L1 and the output voltage terminal (V-OUT). A fifth capacitor C5 is connected in parallel between the inductor L1 and the output voltage terminal (V-OUT). The fifth capacitor C5 is electrically connected to a sixth capacitor C6, and the sixth capacitor C6 is used for the ground terminal (CND). It is characterized in that: the BST pin (the sixth pin) of the DC-DC chip U1 is sequentially connected to the first capacitor C1. A third capacitor C3 is connected in parallel between the inductor L1 and the output voltage terminal (V-OUT). The third capacitor C3 is connected to a fourth capacitor C4, and the fourth capacitor C4 is connected to the fifth capacitor C5. The ground pin (the first pin, GND pin) of the DC-DC chip U1 is connected to the ground terminal (GND). The FB pin (the fourth pin, FB pin) of the DC-DC chip U1 is respectively connected to the first resistor R1 and the second capacitor C2. Both the first resistor R1 and the second capacitor C2 are connected to a second resistor R2, and the second resistor R2 is connected to the ground terminal (GND). The SW pin (the second pin) of the DC-DC chip U1 is connected to the inductor L1. The VIN pin (the third pin, input voltage pin) and the EN pin (the fifth pin, enable pin) of the DC-DC chip U1 are both connected to the input voltage terminal (V-IN).
[0029] As Figure 1 shown, in the present utility model, a third capacitor C3 is connected in parallel between the inductor L1 and the output voltage terminal (V-OUT). The third capacitor C3 is connected to a fourth capacitor C4, and the fourth capacitor C4 is connected to the fifth capacitor C5. Such a third capacitor C3 and a fourth capacitor C4 replace the electrolytic capacitor (aluminum electrolytic capacitor) in the prior art, avoiding the high cost investment of using the electrolytic capacitor (aluminum electrolytic capacitor), and also being beneficial to avoiding the need to use liquid electrolyte for the electrolytic capacitor (aluminum electrolytic capacitor), thereby being beneficial to reducing the overall volume, which has a significant impact on electronic devices with limited space, and the reliability of the electronic device will not be affected in any way. Secondly, it is also beneficial to avoid the limited service life of the electrolytic capacitor (aluminum electrolytic capacitor) and the situation that the aging and corrosion of the electrolyte may cause the capacitor to fail, seriously affecting the normal use of the electronic device, and being more able to meet the requirements.
[0030] Embodiment 2: It can be described on the basis of Embodiment 1. As Figure 1As shown, a seventh capacitor C7 is connected in parallel between the VIN pin of the DC-DC chip U1 and the input voltage terminal (V-IN). The seventh capacitor C7 is electrically connected to an eighth capacitor C8, and the eighth capacitor C8 is electrically connected to a diode D1 (TVS tube). The diode D1 is used for the ground terminal (GND). The EN pin (the fifth pin, the enable pin) of the DC-DC chip U1 is electrically connected to the seventh capacitor C7. This kind of protection is achieved through the TVS tube and the capacitor. Currently, all electronic products will have the application scenario of hot plugging and unplugging. What hot plugging and unplugging bring are electrostatic effects and surge effects. During actual use, due to many spike voltages at the input voltage terminal (V-IN) when the device is hot plugged and unplugged, a relatively high spike voltage will be generated when the power supply terminal is directly plugged or unplugged with electricity. This spike voltage will directly cause the subsequent DC-DC chip to short circuit, which seriously affects the use. For example, some of these voltage spikes reach the place where the cursor 1 (21.1V) is located. The normal voltage should be around 12V (the waveform captured by the oscilloscope before improvement, as Figure 2 shown). In the present invention, when the device is hot plugged and unplugged, what hot plugging and unplugging bring are electrostatic effects and surge effects. The TVS tube is used to achieve electrostatic protection and surge energy absorption. For a low working voltage circuit, the TVS tube can instantaneously suppress or absorb the spike voltage or abnormal current pulse energy generated by the electrostatic effect and the surge effect. The waveform shows that the spike voltage is significantly suppressed (the waveform captured by the oscilloscope after improvement, as Figure 3 shown), which can better meet the requirements and is relatively ideal.
[0031] Such as Figure 1 shown, for further illustration, both the seventh capacitor C7 and the eighth capacitor C8 adopt the 0805 capacitor chip package. This kind of setting is not only relatively common but also cheap, reducing the cost input. Moreover, the capacitance values of both the seventh capacitor C7 and the eighth capacitor C8 are 22uF, which is convenient for implementation. The present invention can achieve electrostatic protection and surge energy absorption by using the seventh capacitor C7 and the eighth capacitor C8 with the 0805 package and a TVS diode. Especially for a low working voltage circuit, the TVS tube can instantaneously suppress or absorb the spike voltage or abnormal current pulse energy generated by the electrostatic effect and the surge effect. The waveform shows that the spike voltage is significantly suppressed, and at the same time, the problem of high cost is solved, which is efficient and practical.
[0032] Embodiment 3: It can be described on the basis of Embodiment 1 or Embodiment 2. Such as Figure 1As shown, both the third capacitor C3 and the fourth capacitor C4 are in 0805 chip capacitor package. This is not only quite common but also inexpensive, reducing cost input. By using this, it is possible to meet the power requirements of the subsequent circuit and achieve relatively stable power supply ripple. At the same time, the space requirement is not high, or rather, there is almost no requirement (a height of 2 - 3 mm is sufficient). Further explanation, the capacitance values of both the third capacitor C3 and the fourth capacitor C4 are 22 uF, which is convenient for implementation.
[0033] Among them, as Figure 1 shown, both the fifth capacitor C5 and the sixth capacitor C6 are in 0603 chip capacitor package. The capacitance value of the fifth capacitor C5 is 0.1 uF, and the capacitance value of the sixth capacitor C6 is 10 pF, which is convenient for implementation.
[0034] Among them, as Figure 1 shown, the model of the inductor L1 is WPN4020H100MT, and the inductance is 4.7 uH, which is convenient for better implementation.
[0035] Among them, as Figure 1 shown, the first capacitor C1 is in 0603 chip capacitor package, and the capacitance value is 0.1 uF, which is more conducive to implementation.
[0036] Among them, as Figure 1 shown, the second capacitor C2 is in 0603 chip capacitor package, and the capacitance value is 33 pF, which is more conducive to implementation.
[0037] Among them, as Figure 1 shown, the specification of the first resistor R1 is 0603 / 100K±1% (for a component with 0603 size, its length and width are 1.6 mm and 0.8 mm respectively; the impedance of the resistor is 100 kΩ; the deviation between the actual value and the nominal value of the resistor does not exceed 1% of the nominal value); the second resistor R2 is 0603 / 27K±1% (for a component with 0603 size, its length and width are 1.6 mm and 0.8 mm respectively; the impedance of the resistor is 27 kΩ; the deviation between the actual value and the nominal value of the resistor does not exceed 1% of the nominal value), which is convenient for implementation.
[0038] The standard parts used in this application document can all be purchased from the market. The internal components of resistors and capacitors all adopt conventional models in the existing technology, and their internal structures belong to the existing technology structure. Workers can complete normal operation on them according to the existing technology manuals. Coupled with the circuit connection adopting the conventional connection method in the existing technology, no specific description will be made here.
[0039] It should be noted that although the above embodiments have been described in this text, it does not thereby limit the patent protection scope of the present utility model. Therefore, based on the innovative concept of the present utility model, any changes and modifications made to the embodiments described in this text, or equivalent structural or equivalent process transformations made by using the content of the specification and drawings of the present utility model, and directly or indirectly applying the above technical solutions to other related technical fields, are all included within the patent protection scope of the present utility model.
Claims
1. A module communication circuit on an Internet of Things device, including a DC-DC chip U1, the DC-DC chip U1 is connected with an output voltage terminal and an input voltage terminal, a first capacitor C1 and an inductor L1 are sequentially arranged between the DC-DC chip U1 and the output voltage terminal, a first resistor R1 and a second capacitor C2 are sequentially connected between the inductor L1 and the output voltage terminal, a fifth capacitor C5 is connected in parallel between the inductor L1 and the output voltage terminal, the fifth capacitor C5 is electrically connected with a sixth capacitor C6, and the sixth capacitor C6 is used for a grounding terminal, and is characterized in that: The BST pin of the DC-DC chip U1 is sequentially connected to the first capacitor C1. A third capacitor C3 is connected in parallel between the inductor L1 and the output voltage terminal. The third capacitor C3 is connected to a fourth capacitor C4, the fourth capacitor C4 is connected to a fifth capacitor C5. The ground pin of the DC-DC chip U1 is connected to the ground terminal. The FB pin of the DC-DC chip U1 is connected to the first resistor R1 and the second capacitor C2 respectively. Both the first resistor R1 and the second capacitor C2 are connected to a second resistor R2, and the second resistor R2 is connected to the ground terminal. The SW pin of the DC-DC chip U1 is connected to the inductor L1. The VIN pin and the EN pin of the DC-DC chip U1 are both connected to the input voltage terminal.
2. The communication circuit of the upper module on the Internet of Things device according to claim 1, wherein: A seventh capacitor C7 is connected in parallel between the VIN pin of the DC-DC chip U1 and the input voltage terminal. The seventh capacitor C7 is electrically connected to an eighth capacitor C8, and the eighth capacitor C8 is electrically connected to a diode D1. The diode D1 is grounded, and the EN pin of the DC-DC chip U1 is electrically connected to the seventh capacitor C7.
3. The communication circuit of the upper module on the Internet of Things device according to claim 2, characterized in that: Both the seventh capacitor C7 and the eighth capacitor C8 are in the 0805 capacitor surface mount package, and the capacitance of both the seventh capacitor C7 and the eighth capacitor C8 is 22 uF.
4. The communication circuit of the upper module on the Internet of Things device according to claim 1 or 2 or 3, characterized in that: Both the third capacitor C3 and the fourth capacitor C4 to which it is connected are in the 0805 capacitor surface mount package.
5. The communication circuit of the upper module on the Internet of Things device according to claim 4, characterized in that: The capacitance of both the third capacitor C3 and the fourth capacitor C4 to which it is connected is 22 uF.
6. The module communication circuit on the Internet of Things device according to claim 1 or 2 or 3 or 5, characterized in that: Both the fifth capacitor C5 and the sixth capacitor C6 are in the 0603 capacitor surface mount package. The capacitance of the fifth capacitor C5 is 0.1 uF, and the capacitance of the sixth capacitor C6 is 10 pF.
7. The module communication circuit on the Internet of Things device according to claim 1 or 2 or 3 or 5, characterized in that: The inductor L1 has the model number WPN4020H100MT and an inductance of 4.7 uH.
8. The module communication circuit on the Internet of Things device according to claim 1 or 2 or 3 or 5, characterized in that: The first capacitor C1 is in the 0603 capacitor surface mount package with a capacitance of 0.1 uF.
9. The module communication circuit on the Internet of Things device according to claim 1 or 2 or 3 or 5, characterized in that: The second capacitor C2 is in the 0603 capacitor surface mount package with a capacitance of 33 pF.
10. The module communication circuit on the Internet of Things device according to claim 1 or 2 or 3 or 5, characterized in that: The specification of the first resistor R1 is 0603 / 100K±1%, and the second resistor R2 is in the 0603 / 27K±1% package.