Circuit board for optimizing impedance test line
By optimizing the layout of impedance test lines on the circuit board and concentrating traces of the same or different impedance values on the same test line, the cost increase and test efficiency reduction caused by the increase in types and quantities of impedance traces is solved, and cost reduction and efficiency improvement are achieved.
Patent Information
- Application Number
- CN202422107122.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-29
- Publication Date
- 2025-07-11
- Estimated Expiration
- 2034-08-29
AI Technical Summary
As impedance types are controlled more and more, the types and quantity of impedance traces are increased, resulting in an increase in PCB board cost, increase in test volume and decrease in test efficiency.
By designing several impedance traces of the same or different impedance values on the circuit board, the layout of the impedance test line is optimized, the number and area of impedance test lines are reduced, and the utilization rate of the board is improved.
Effectively reduce PCB costs, reduce testing workload, and improve testing efficiency and work efficiency.
Smart Images
Figure CN223093954U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of printed circuit boards, and specifically relates to a circuit board for optimizing impedance test lines. Background Art
[0002] When designing high-tech hardware devices, such as servers, communication, and medical devices, it is usually required that PCB processing factories manufacture according to the trace impedance values specified in the designed PCB files and control a certain error range. To ensure that the traces on the PCB meet the customer's requirements for impedance control, impedance bars are used for testing and verification during the production process in PCB processing factories. An impedance bar is a specially designed test structure, usually printed on the PCB board, used to verify whether the trace impedance on the PCB meets the design requirements. PCB processing factories will prepare impedance bars with different impedance values according to the PCB design files provided by customers, and these impedance values usually correspond to the impedance settings of the designed traces.
[0003] With the development and progress of technology, the signal rate is getting higher and higher, the chip manufacturing process is getting more and more precise, and the chip package size is getting larger and larger. As a result, the PCB board material grade is getting higher (more expensive), the impedance control accuracy is getting higher, the types of impedance control are getting more, and the number of PCB layers is getting more, resulting in a more complex impedance bar design. And as the types of impedance control increase, for example, in some 14-layer PCBs, 16 pairs of differential impedance traces need to be added for 85ohm differential impedance. The increase in the types and numbers of impedance traces requires an additional impedance bar area on the substrate, which increases the cost of the PCB board material. The increase in the types and numbers of impedance traces also leads to an increase in the test volume and a decrease in the test efficiency. Summary of the Utility Model
[0004] The purpose of the utility model is to provide a circuit board for optimizing impedance test lines to solve the problems raised in the above background art: as the types of impedance control increase, for example, in some 14-layer PCBs, 16 pairs of differential impedance test lines need to be added for 85ohm differential impedance. The increase in the types and numbers of impedance traces requires an additional impedance bar area on the substrate, which increases the cost of the PCB board material. The increase in the types and numbers of impedance traces also leads to an increase in the test volume and a decrease in the test efficiency.
[0005] To achieve the above object, the present disclosure provides a circuit board for optimizing impedance test lines, which is characterized in that it includes: a substrate, on which there are a plurality of impedance traces, the plurality of impedance traces have the same or different impedance values, and the plurality of impedance traces are arranged in the same or different regions, wherein the plurality of impedance traces with the same impedance value are placed on the same impedance test line or the plurality of impedance traces with different impedance values are placed on the same impedance test line.
[0006] In a possible implementation, the plurality of impedance traces are single - line impedance traces or differential impedance traces.
[0007] In a possible implementation, a plurality of impedance traces with different impedance values and different line widths are placed on the same impedance test line, and the impedance traces are single - line impedance traces.
[0008] In a possible implementation, a plurality of impedance traces with the same impedance value and different line widths and line spacings are placed on the same impedance test line, and the impedance traces are differential impedance traces.
[0009] In a possible implementation, a plurality of impedance traces with different impedance values and different line widths and line spacings are placed on the same impedance test line, and the impedance traces are differential impedance traces.
[0010] In a possible implementation, a plurality of impedance traces in the same area are placed on the same impedance test line or a plurality of impedance traces in different areas are placed on the same impedance test line.
[0011] In a possible implementation, the circuit board for optimizing the impedance test line further includes: a multi - layer circuit board, which is formed by stacking a plurality of the substrates.
[0012] In a possible implementation, a measurement port is provided at the end of the impedance test line.
[0013] One or more of the above - mentioned technical solutions in the embodiments of the present application have at least one or more of the following technical effects:
[0014] In a circuit board for optimizing an impedance test line provided in an embodiment of the present utility model, including: a substrate, a plurality of impedance traces are provided on the substrate. By placing a plurality of impedance traces with the same impedance value on the same impedance test line or a plurality of impedance traces with different impedance values on the same impedance test line, the number of impedance test lines can be effectively reduced, thereby reducing the impedance bar area, improving the utilization rate of the board material, further reducing the PCB cost, and at the same time reducing the impedance test workload and improving the work efficiency.
[0015] The above description is only an overview of the technical solutions of the present utility model. In order to be able to understand the technical means of the present utility model more clearly, it can be implemented according to the content of the description. And in order to make the above - mentioned and other purposes, features and advantages of the present utility model more obvious and understandable, the specific embodiments of the present utility model are hereinafter specifically exemplified. Description of the Drawings
[0016] Figure 1Schematic diagram of the structure where differential impedance traces with different line widths or line spacings on a circuit board for optimizing impedance test lines are placed on the same impedance test line provided by an embodiment of the present application;
[0017] Figure 2 Schematic diagram of the structure where single - line impedance traces with the same impedance value but in different regions on a circuit board for optimizing impedance test lines are placed on the same impedance test line provided by an embodiment of the present application;
[0018] Figure 3 Schematic diagram of the structure where single - line impedance traces with different impedance values and different line widths on a circuit board for optimizing impedance test lines are placed on the same impedance test line provided by an embodiment of the present application;
[0019] Figure 4 Schematic diagram of the structure where differential impedance traces with the same impedance value but in different regions on a circuit board for optimizing impedance test lines are placed on the same impedance test line provided by an embodiment of the present application.
[0020] Explanation of reference numerals: 100, substrate; 110, impedance trace; 120, measurement port; 130, trace in BGA area; 140, trace in normal area. Detailed implementation manners
[0021] To make the purpose, technical solutions, and advantages of the present disclosure clearer, the embodiments of the present disclosure will be further described in detail below in conjunction with the accompanying drawings.
[0022] Here, the exemplary embodiments will be described in detail, and their examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present disclosure. On the contrary, they are only examples of the structures and methods consistent with some aspects of the present disclosure as detailed in the appended claims.
[0023] Please refer to Figures 1 to 2 , the circuit board for optimizing impedance test lines includes:
[0024] A substrate 100, on which several impedance traces 110 are provided. The several impedance traces 110 have the same or different impedance values and are arranged in the same or different regions. Among them, several impedance traces 110 with the same impedance value are placed on the same impedance test line or several impedance traces 110 with different impedance values are placed on the same impedance test line.
[0025] Specifically, the substrate 100 refers to the basic layer of the circuit board, which is usually composed of materials such as dielectric and copper foil. The impedance traces 110 are used to test the impedance values of different areas on the circuit board. The impedance values of each impedance trace 110 can be the same or different, and each impedance trace 110 can be disposed in the same or different areas.
[0026] By placing a number of impedance traces 110 with the same impedance value on the same impedance test line, or a number of impedance traces 110 with different impedance values on the same impedance test line, the number of impedance test lines can be effectively reduced, thereby reducing the impedance bar area, improving the utilization rate of the board material, further reducing the cost of the PCB, and at the same time reducing the impedance test workload and improving the work efficiency.
[0027] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.
[0028] Furthermore, a number of impedance traces 110 are single - line impedance traces or differential impedance traces. In circuit board design, different types of impedance traces 110 can be flexibly selected to meet different electrical performance requirements. Single - line impedance traces are suitable for simple signal transmission, while differential impedance traces are suitable for applications that require higher signal integrity, such as high - speed data transmission.
[0029] Furthermore, please refer to Figure 3 , a number of impedance traces 110 with different impedance values and different line widths are placed on the same impedance test line, and the impedance traces 110 are single - line impedance traces. Specifically, in PCB design, the impedance value of the impedance trace 110 is usually related to its width, the thickness of the dielectric layer, and the electrical characteristics of the dielectric material. Therefore, impedance traces 110 with different impedances require different line widths to meet the design requirements.
[0030] Please refer to Figure 1 , a number of impedance traces 110 with the same impedance value, different line widths and different line spacings are placed on the same impedance test line, and the impedance traces 110 are differential impedance traces.
[0031] In another embodiment, a plurality of impedance traces 110 with different impedance values, line widths, and line spacings are placed on the same impedance test line, and the impedance traces 110 are differential impedance traces. Since the difference between the embodiment where a plurality of impedance traces 110 with different impedance values, line widths, and line spacings are placed on the same impedance test line and the embodiment where a plurality of impedance traces 110 with the same impedance values, line widths, and line spacings are placed on the same impedance test line lies in the sameness or difference of the impedance values, the illustration of this embodiment can be referred to Figure 1 .
[0032] It can be understood that differential impedance traces are usually used in applications that require high signal integrity, such as high-speed data transmission. They consist of a pair of lines that transmit signals with opposite phases, which helps to reduce noise and interference. By placing differential impedance traces with the same impedance value but different line spacings or line widths on the same impedance test line, or placing differential impedance traces with different impedance values but different line spacings or line widths on the same impedance test line, the space utilization of the circuit board can be further optimized, the required impedance bar area can be reduced, which helps to reduce the cost of the PCB and improve the efficiency of the overall test.
[0033] Please refer to Figure 2 , a plurality of impedance traces 110 with the same impedance value but in different regions are placed on the same impedance test line. More specifically, the impedance traces 110 can be single-line impedance traces or differential impedance traces. It can be understood that in PCB design, a region usually refers to a specific area or area segment on the board, where multiple signal lines or traces may be arranged. The region can include different types of regions, such as a normal region, a BGA region, etc. The normal region refers to a general signal routing area suitable for general signal transmission; the BGA region usually refers to a specific area used in PCB design or integrated circuit (IC) packaging, with BGA chip leads and a fan-out area. Its characteristics are that the signal holes are relatively dense and regular. For example, as Figure 2 the normal region trace 140 located in the normal region and the BGA region trace 130 located in the BGA region in are placed on the same impedance test line, where the normal region trace 140 and the BGA region trace 130 are single-line impedance traces; or as Figure 4 shown in, in another embodiment, the normal region trace 140 and the BGA region trace 130 are differential impedance traces. By centrally placing the impedance traces 110 of traces with the same impedance value but in different regions on the same impedance test line, the total number of impedance test lines can be reduced, thereby reducing the area of the impedance bar and improving the utilization rate of the board material. This helps to reduce the cost of the PCB, and due to the concentration of the impedance traces, the design and manufacturing processes can be simplified.
[0034] Furthermore, the circuit board for optimizing the impedance test line further includes: a multilayer circuit board, which is formed by stacking a plurality of substrate layers 100. Specifically, according to requirements, multiple substrate layers 100 can be stacked in the multilayer circuit board, and each layer can include different impedance trace configurations to meet more complex design requirements and higher impedance control accuracy.
[0035] Specifically, in the application of the multilayer circuit board, on the same substrate layer 100, by placing a number of impedance traces 110 with the same impedance value on the same impedance test line, or placing a number of impedance traces 110 with different impedance values on the same impedance test line, placing a number of differential impedance traces with the same impedance value but different line widths and line spacings on the same impedance test line, or placing a number of impedance traces 110 with the same impedance value but in different regions on the same impedance test line, the number and area of the impedance test lines can be reduced, the utilization rate of the board material can be improved, and thus the PCB manufacturing cost can be reduced. At the same time, the workload of impedance testing can be reduced, making the testing process more efficient. In addition, by centrally designing different types of impedance test lines, it is convenient for comparative analysis and optimized design, and the design and debugging efficiency can be improved.
[0036] Furthermore, a measurement port 120 is provided at the end of the impedance test line. The measurement port 120 is used for impedance matching and signal integrity analysis when testing and verifying the circuit board design.
[0037] Details not described in this utility model are all well-known techniques to those skilled in the art.
[0038] For those skilled in the art, it is obvious that this utility model is not limited to the details of the above exemplary embodiments, and without departing from the spirit or basic characteristics of this utility model, this utility model can be implemented in other specific forms. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-restrictive. The scope of this utility model is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in this utility model. Any reference signs in the claims should not be regarded as limiting the claimed rights.
Claims
1. A circuit board for optimizing impedance test lines, characterized in that, Including: A substrate, on which a plurality of impedance traces are provided, the plurality of impedance traces having the same or different impedance values, the plurality of impedance traces being disposed in the same or different regions, wherein the impedance traces with the same impedance value are placed on the same impedance test line or the impedance traces with different impedance values are placed on the same impedance test line.
2. The circuit board for optimizing an impedance test line according to claim 1, wherein The plurality of impedance traces are single-line impedance traces or differential impedance traces.
3. The circuit board for optimizing an impedance test line according to claim 1, wherein The impedance traces with different impedance values and different line widths are placed on the same impedance test line, and the impedance traces are single-line impedance traces.
4. A circuit board for optimizing an impedance test line according to claim 1, characterized in that, The impedance traces with the same impedance value, different line widths and line spacings are placed on the same impedance test line, and the impedance traces are differential impedance traces.
5. A circuit board for optimizing an impedance test line according to claim 1, characterized in that The impedance traces with different impedance values, different line widths and line spacings are placed on the same impedance test line, and the impedance traces are differential impedance traces.
6. The circuit board for optimizing an impedance test line according to claim 2, characterized in that The impedance traces in the same region are placed on the same impedance test line or the impedance traces in different regions are placed on the same impedance test line.
7. A circuit board for optimizing an impedance test line according to any one of claims 1 to 6, characterized in that, Further including: A multilayer circuit board, which is formed by stacking a plurality of layers of the substrates.
8. A circuit board for optimizing an impedance test line according to any one of claims 1 to 6, characterized in that, A measurement port is provided at the end of the impedance test line.