Power device packaging structure
The power device packaging structure addresses long interconnect issues by using copper re-distribution layers and pillars to enhance thermal conductivity and integration density, reducing parasitic inductance and improving heat dissipation.
Patent Information
- Application Number
- CN202422036296.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-21
- Publication Date
- 2025-07-15
- Estimated Expiration
- 2034-08-21
AI Technical Summary
In the prior art, the lead connection between GaN and Si chips leads to excessive parasitic resistance and poor heat dissipation performance, and the leads occupy the internal space of the package structure, limiting the high integration of multiple pairs of chips.
By adopting the copper rewiring layer and copper column or copper ball interconnection method, by growing a communication structure between the third rewiring layer and the first rewiring layer, electrical signals are drawn from the HEMT chip and the MOSFET chip to the first rewiring layer, and the copper rewiring layer is electroplated on the back of the chip to shorten the signal transmission distance and improve the heat dissipation performance.
It greatly reduces the internal space occupation of the package structure, reduces parasitic resistance, improves heat dissipation performance, and achieves a high degree of integration and switching performance improvement of multiple pairs of power devices in a limited-size package structure.
Smart Images
Figure CN223108890U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, and particularly relates to a power device packaging structure. Background Art
[0002] At present, the cascade GaN devices are usually packaged in a single-pair manner. For example, a single-pair chip composed of a GaN chip and a Si chip is packaged in the same package. The signal connection between the GaN and Si chips usually adopts wire bonding. However, there are the following two technical problems with wire bonding:
[0003] 1. The too long wire interconnection length introduces a large amount of parasitic inductance, resulting in switching losses. At the same time, in the wire interconnection process, since the chip is connected to the lead frame through the bonding glue, and the thermal conductivity of the bonding glue is relatively low, it seriously affects the heat dissipation performance of the packaging structure and reduces the service life of the power device.
[0004] 2. The wires themselves will occupy the internal space of the packaging structure. When several pairs of chips need to be packaged in a package with a fixed size, the wire connection method is not conducive to the high integration of multiple pairs of power devices in the package. Summary of the Utility Model
[0005] The utility model aims to improve the high integration of multiple pairs of power devices in the same package with a fixed size and ensure the heat dissipation effect, and provides a power device packaging structure.
[0006] To achieve this purpose, the utility model adopts the following technical solutions:
[0007] Provide a power device packaging structure, including:
[0008] A first redistribution layer, covering the back of the HEMT chip and / or the MOSFET chip and connecting to the pads;
[0009] The electrical signals of the HEMT chip and / or the MOSFET chip are led out to the first redistribution layer, and / or led out to the first redistribution layer through the third redistribution layer;
[0010] The third redistribution layer, covering the front of the HEMT chip and / or the MOSFET chip.
[0011] Preferably, the MOSFET chip includes a first MOSFET chip and a second MOSFET chip, and the gate electrical signals of the MOSFET chip are led out to the first redistribution layer through the third redistribution layer and connected to the gate pads corresponding to each gate respectively.
[0012] Preferably, the source electrical signals of the first MOSFET chip and the second MOSFET chip are led out to the first rewiring layer through the third rewiring layer and connected to the source pads respectively corresponding to each source.
[0013] Preferably, the HEMT chip includes a first HEMT chip and a second HEMT chip. The drain of the first HEMT chip is led out to the first rewiring layer through the third rewiring layer and connected to the drain pad.
[0014] The source of the first HEMT chip is led out to the third rewiring layer and then connected to the drain of the first MOSFET chip led out on the first rewiring layer.
[0015] The gate of the first HEMT chip led out on the third rewiring layer, the source of the first MOSFET chip, and the drain of the second HEMT chip are interconnected and connected to the first composite pad provided on the first rewiring layer.
[0016] The source of the second HEMT chip is led out to the third rewiring layer and then connected to the drain of the second MOSFET chip led out on the first rewiring layer.
[0017] The gate of the second HEMT chip is led out to the third rewiring layer and then connected to the source of the second MOSFET led out on the third rewiring layer and connected to the second composite pad provided on the first rewiring layer.
[0018] Preferably, the HEMT chip is a high-voltage horizontal structure GaN chip; the MOSFET chip is a low-voltage Si chip with a vertical structure.
[0019] Preferably, the first rewiring layer and / or the third rewiring layer is a copper rewiring layer.
[0020] Preferably, a gap is left between each HEMT chip or between each MOSFET chip or between each HEMT chip and each MOSFET chip, and the gap is filled with an insulating material.
[0021] Preferably, the electrical signals led out from the HEMT chip and / or the MOSFET chip to the third rewiring layer are connected to the first rewiring layer through a signal lead-out structure grown between the third rewiring layer and the first rewiring layer.
[0022] The utility model has the following beneficial effects:
[0023] 1. By growing a connection structure (such as copper pillars) between the third wiring layer and the first wiring layer, the electrical signals led out from the HEMT chip and / or MOSFET chip to the third wiring layer are connected to the first wiring layer, changing the lead connection method adopted in the existing packaging method, greatly reducing the occupation of the internal space of the packaging structure, and facilitating the high integration of multiple pairs of power devices in the same packaging structure with limited size. Most importantly, the signal is conducted through the copper wiring layer and copper pillars or copper balls in the package, and the transmission distance is greatly reduced compared with the lead transmission, and the parasitic inductance is greatly reduced. At the same time, by directly electroplating the copper wiring layer on the back of the chip, the thermal resistance caused by the materials such as bonding glue for fixing the chip on the lead frame is reduced, and the heat dissipation performance is enhanced.
[0024] 2. By guiding the heat generated in the third wiring layer downward to the first wiring layer and conducting heat through the pads, the overall heat dissipation performance of the packaging structure is improved, and the probability that each semiconductor device arranged on the front of the chip is damaged due to poor heat dissipation is greatly reduced.
[0025] 3. By setting corresponding source, drain, and gate connection relationships between the first HEMT chip, the second HEMT chip, the first MOSFET chip, and the second MOSFET chip and connecting them to the corresponding pads, independent heat dissipation channels are set for the first chip pair composed of the first HEMT chip and the first MOSFET chip and the second chip pair composed of the second HEMT chip and the second MOSFET chip respectively. And by controlling the first HEMT chip and the second HEMT chip to work alternately, the total thermal power is evenly distributed to the two GaN chips on average, and the heat generated by the two GaN chips is transferred to the back pads along themselves to achieve double heat dissipation. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.
[0027] Figure 1 is a structural diagram of a power device package provided by an embodiment of the present invention;
[0028] Figure 2 is a cross-sectional view of a power device package structure;
[0029] Figure 3 is a schematic diagram of a power device packaging process;
[0030] Figure 4It is a circuit schematic diagram in which two pairs of chip pairs composed of GaN chips and Si chips work alternately. Specific implementation mode
[0031] The technical solution of the present utility model will be further described below in conjunction with the accompanying drawings and through specific implementation modes.
[0032] Among them, the accompanying drawings are only for illustrative purposes, showing only schematic diagrams, not physical diagrams, and should not be construed as a limitation to the present utility model; in order to better illustrate the embodiments of the present utility model, some components in the accompanying drawings will be omitted, enlarged or reduced, and do not represent the dimensions of the actual product; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the accompanying drawings may be omitted.
[0033] In the accompanying drawings of the embodiments of the present utility model, the same or similar reference numerals correspond to the same or similar components; in the description of the present utility model, it should be understood that if terms such as "upper", "lower", "left", "right", "inner", "outer", etc. indicate the orientation or positional relationship, it is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms describing the positional relationship in the accompanying drawings are only for illustrative purposes and should not be construed as a limitation to the present utility model. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific circumstances.
[0034] In the description of the present utility model, unless otherwise clearly specified and limited, if terms such as "connection" indicate the connection relationship between components, this term should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection, an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and can be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.
[0035] The power device packaging structure provided by the embodiments of the present utility model includes Figure 2 The first rewiring layer 1 shown in the figure, covering the back of the chip 2 (including HEMT chips and / or MOSFET chips) and connecting to the Figure 3 The pad 4 shown in the figure; the electrical signals of the HEMT chips and / or MOSFET chips are led out to the first rewiring layer, and / or first led out to the third rewiring layer 3, and then by the one grown between the third rewiring layer 3 and the first rewiring layer 1 as shown in the Figure 2The through-hole or copper pillar, etc. in the connection structure 5 in 3 leads the electrical signal from the third wiring layer 3 to the first wiring layer 1, so as to realize the conduction and heat dissipation of the heat generated by the electrical signal through the pads arranged on the first wiring layer. The third wiring layer covers the front of the chip 2.
[0036] By growing a connection structure between the third wiring layer and the first wiring layer, the electrical signal led out to the third wiring layer from the HEMT chip and / or MOSFET chip is connected to the first wiring layer, which changes the lead connection method adopted in the existing packaging method, greatly reduces the occupation of the internal space of the packaging structure, and is conducive to the high integration of multiple pairs of power devices in the same packaging structure with limited size. The most crucial thing is that the connection structure grows on the plastic seal between the third wiring layer and the first wiring layer, basically does not introduce parasitic inductance and increase the packaging thermal resistance, and is conducive to increasing the service life of the power device. And the signal is conducted through the copper wiring layer and copper pillars or copper balls in the package, and the transmission distance is greatly reduced compared with the lead transmission, the parasitic inductance is greatly reduced. At the same time, by directly electroplating the copper wiring layer on the back of the chip, the thermal resistance brought by the materials such as bonding glue that fix the chip on the lead frame is reduced, and the heat dissipation performance is enhanced.
[0037] Taking two pairs of chip pairs composed of GaN chips and Si chips integrated in the same packaging structure as an example below, the technical principle that connecting electrical signals in the way of growing a connection structure (through-hole or copper pillar) between the third wiring layer and the first wiring layer is more conducive to the high integration of multiple pairs of power devices in the same packaging structure with limited size and has better heat dissipation effect compared with the lead connection method of the traditional scheme is described:
[0038] Figure 1 In it, the first chip pair composed of the first GaN chip 10 and the first Si chip 20 and the second chip pair composed of the second GaN chip 30 and the second Si chip 40 are integrated in the same packaging structure. The source electrical signals of the first Si chip 20 and the second Si chip 40 are first led out to Figure 2 the third wiring layer 3 shown in it and then led out to the first wiring layer 1 by the connection structure 5 and connected to Figure 1 the corresponding gate pads arranged on the first wiring layer shown in it. That is, the source S1 of the first Si chip 20 has a separate first source pad 201 as shown in Figure 1 it, and the source S3 of the second Si chip 40 has a separate second source pad 401 as shown in Figure 1 it.
[0039] Preferably, the gates of the first Si chip 20 and the second Si chip 40 also have separate pads. The gate electrical signals of the two Si chips are also first led out to the third rewiring layer 3 and then led out to the first rewiring layer 1 by the connection structure 5 and connected to the corresponding gate pads. For example, the gate G1 of the first Si chip 20 has a separate first gate pad 202 as shown in Figure 1 as shown, and the gate G3 of the second Si chip 20 has a separate second gate pad 402 as shown in Figure 1 as shown.
[0040] The electrical signal of the drain D2 of the first GaN chip 10 is first led out to the third rewiring layer and then led out to the first rewiring layer 1 through the connection structure 5 and connected to the drain pad 101 as shown in Figure 1 as shown;
[0041] The source S2 of the first GaN chip 10 is led out to the third rewiring layer and then connected to the drain D1 of the first Si chip 20 led out on the first rewiring layer 1;
[0042] The gate G2 of the first GaN chip 10, the source S1 of the first Si chip 20, and the drain D4 of the second GaN chip led out on the third rewiring layer 3 are connected to each other and connected to the first composite pad 50 as shown in Figure 1 as shown and provided on the first rewiring layer 1;
[0043] The source S4 of the second GaN chip 30 is led out to the third rewiring layer and then connected to the drain D3 of the second Si chip 40 led out on the first rewiring layer;
[0044] The gate G4 of the second GaN chip 30 is led out to the third rewiring layer and then connected to the source S3 of the second Si chip 40 led out on the third rewiring layer and connected to the second composite pad 60 as shown in Figure 1 as shown and provided on the first rewiring layer 1.
[0045] In the above solution, by setting corresponding source, drain, and gate connection relationships among the first GaN chip, the second GaN chip, the first Si chip, and the second Si chip and connecting them to corresponding pads, independent heat dissipation channels are respectively set for the first chip pair composed of the first GaN chip and the first Si chip and the second chip pair composed of the second GaN chip and the second Si chip, enabling the two pairs of chips highly integrated within a packaging structure with limited size to have better heat dissipation effects. Moreover, the mutual connection of the gates, sources, and drains among the chips is realized through connection structures 5 (such as copper pillars) grown on the plastic seal between the third wiring layer and the first wiring layer. Compared with the lead connection method, it does not increase the occupation of the internal space of the packaging structure by itself. Therefore, it is beneficial to the high integration of the two chip pairs within the same packaging structure with limited size. And through the copper re - wiring layer and the interconnection method of copper pillars or copper balls, the interconnection distance is greatly shortened compared with lead interconnection, the line parasitic inductance is greatly reduced, and the device switching performance is improved.
[0046] In the above solution, preferably, the HEMT chip is a high - voltage - level - structure GaN chip; the MOSFET chip is a low - voltage - vertical - type Si chip with a vertical structure. The first wiring layer and / or the third wiring layer are preferably copper wiring layers. There are gaps left between each HEMT chip, or between each MOSFET chip, or between each HEMT chip and each MOSFET chip, and the gaps are filled with insulating materials.
[0047] Through the above solution, in the packaging structure with limited size, the present utility model constructs independent heat dissipation channels for the two chip pairs respectively. When the two chips work alternately, the total thermal power is evenly distributed to the two GaN chips on average, and the heat generated by the two GaN chips is transferred along themselves to the back pads to achieve double heat dissipation.
[0048] The following describes how to implement the control of the alternate operation of the two chip pairs in this embodiment:
[0049] As Figure 4 shown, the gate - source voltage of the GaN HEMT chip is equal in magnitude and opposite in sign to the drain - source voltage of the Si MOSFET. Therefore, the turn - on and turn - off of the GaN HEMT chip are controlled by the drain - source voltage of the Si MOSFET chip. By applying a high or low level to the gate of the Si MOSFET chip, the conduction and cut - off between the drain and source of the Si MOSFET chip can be controlled. Therefore, by alternately inputting high and low levels to the gates of the two Si MOSFET chips, the alternate operation control of the two GaN HEMT chips can be realized.
[0050] The following describes the packaging method of the power device packaging structure provided in this embodiment:
[0051] Figure 3The encapsulation structures arranged from top to bottom correspond to the encapsulation processes from first to last in the encapsulation method. The encapsulation method includes the steps:
[0052] L1, fixing the back surface of at least one chip 2 (including HEMT chips and / or MOSFET chips) on the carrier board 100;
[0053] L2, growing signal lead-out structures 200 (preferably copper balls or copper pillars) on the chip 2 to lead out the poles generating electrical signals on the chip to the third-level wiring layer or the first-level wiring layer;
[0054] L3, filling the gaps left between the chips with an insulating material 300;
[0055] L4, removing the carrier board 100, and then arranging a plurality of connection structures 5 connecting the third-level wiring layer and the first-level wiring layer on the insulating material 300, and the electrical signals led out to the third-level wiring layer are connected to the first-level wiring layer through the connection structures;
[0056] L5, electroplating a third-level wiring layer 3 and a first-level wiring layer 1 on the front and back surfaces of each chip respectively;
[0057] L6, fixing pads 4 on the first-level wiring layer.
[0058] In addition, preferably, a solder mask layer 400 is grown on both sides of the chip (preferably the solder pad surface is covered with the solder mask layer, and the other side is protected with an insulating material).
[0059] In summary, in the present utility model, by growing a connection structure between the third-level wiring layer and the first-level wiring layer to connect the electrical signals led out from the HEMT chips and / or MOSFET chips to the third-level wiring layer to the first-level wiring layer, the lead connection method adopted in the existing encapsulation method is changed, the internal space occupation of the encapsulation structure is greatly reduced, which is beneficial to the high integration of multiple pairs of power devices in the same encapsulation structure with limited size; most importantly, through the interconnection method of the copper wiring layer and the copper pillars or copper balls, the interconnection distance is greatly shortened compared with the lead interconnection, the line parasitic inductance is greatly reduced, the switching performance of the device is improved, the two chips work alternately, the total thermal power is evenly distributed to the two GaN chips on average, and the heat generated by the two GaN chips is transferred along itself to the back pad to achieve double heat dissipation.
[0060] It should be noted that the above specific embodiments are only the preferred embodiments of the present utility model and the applied technical principles. Those skilled in the art should understand that various modifications, equivalent replacements, changes, etc. can be made to the present utility model. However, as long as these transformations do not deviate from the spirit of the present utility model, they should be within the protection scope of the present utility model. In addition, some terms used in the specification and claims of this application are not restrictive, but are only for the convenience of description.
Claims
1. A power device packaging structure, characterized in that, Comprising: A first-level wiring layer, covering the back surface of the HEMT chip and / or the MOSFET chip and connecting to the pads; The electrical signals of the HEMT chip and / or the MOSFET chip are led out to the first-level wiring layer, and / or are led out to the first-level wiring layer through a third-level wiring layer; The third-level wiring layer, covering the front surface of the HEMT chip and / or the MOSFET chip.
2. The power device packaging structure according to claim 1, characterized in that The MOSFET chip includes a first MOSFET chip and a second MOSFET chip. The gate electrical signals of the MOSFET chip are led out to the first-level wiring layer through the third-level wiring layer and connected to the gate pads corresponding to each gate respectively.
3. The power device packaging structure according to claim 2, wherein, The source electrical signals of the first MOSFET chip and the second MOSFET chip are led out to the first-level wiring layer through the third-level wiring layer and connected to the source pads corresponding to each source respectively.
4. The power device packaging structure according to any one of claims 1-3, characterized in that, The HEMT chip includes a first HEMT chip and a second HEMT chip. The drain of the first HEMT chip is led out to the first-level wiring layer through the third-level wiring layer and connected to the drain pad; The source of the first HEMT chip is led out to the third-level wiring layer and then connected to the drain led out on the first-level wiring layer of the first MOSFET chip; The gate of the first HEMT chip, the source of the first MOSFET chip, and the drain of the second HEMT chip led out on the third-level wiring layer are connected to each other and connected to the first composite pad provided on the first-level wiring layer; The source of the second HEMT chip is led out to the third-level wiring layer and then connected to the drain led out on the first-level wiring layer of the second MOSFET chip; The gate of the second HEMT chip is led out to the third-level wiring layer and then connected to the source led out on the third-level wiring layer of the second MOSFET and connected to the second composite pad provided on the first-level wiring layer.
5. The power device packaging structure according to claim 1, characterized in that, The HEMT chip is a high-voltage horizontal structure GaN chip; the MOSFET chip is a vertical structure low-voltage Si chip.
6. The power device packaging structure according to claim 1, characterized in that, The first-level wiring layer and / or the third-level wiring layer is a copper wiring layer.
7. The power device packaging structure according to claim 1, characterized in that, There are gaps between the HEMT chips, or between the MOSFET chips, or between the HEMT chips and the MOSFET chips, and the gaps are filled with insulating materials.
8. The power device packaging structure according to claim 4, characterized in that, The first HEMT chip and the second HEMT chip work alternately; the first HEMT chip or the second HEMT chip in the working state dissipates heat through itself and / or the pads covering the back surface of its chip.
9. The power device packaging structure according to claim 1, wherein, The electrical signals led out from the HEMT chip and / or the MOSFET chip to the third-level wiring layer are connected to the first-level wiring layer through a signal lead-out structure grown between the third-level wiring layer and the first-level wiring layer.