Multi-gear current clamping device, power supply board card and testing machine
The multi-level clamping device addresses slow clamping speeds in semiconductor testing by implementing separate current circuits with a switching mechanism for precise control, ensuring effective chip protection.
Patent Information
- Application Number
- CN202421848353.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-31
- Publication Date
- 2025-07-15
- Estimated Expiration
- 2034-07-31
AI Technical Summary
The existing power supply board lacks the fast clamping function of intermediate current gears and small current gears, resulting in slow overcurrent protection during chip testing, which may cause damage to the chip.
A multi-speed clamp flow device is adopted, and a positive current clamp flow circuit is formed by connecting the first clamp flow element to the gear switching circuit, and a negative current clamp flow circuit is formed by connecting the second clamp flow element to the gear switching circuit. The access resistor is selected by using the gear switching circuit to realize the hardware clamp flow method of multi-speed clamp flow, and quickly switch the current gear.
Faster clamp flow speed is achieved, effectively protecting the chip's overcurrent during testing and avoiding destructive overcurrent at the millisecond level.
Smart Images
Figure CN223109661U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip testing, and particularly to a multi-range current clamping device, a power supply board, and a testing machine. Background Art
[0002] In semiconductor automatic testing equipment products, the power supply board mainly has functions such as voltage application, current application, voltage measurement, and current measurement. Among them, overcurrent protection is a relatively important function.
[0003] In the prior art, the power supply board generally only has fast current clamping in one large current range, without fast current clamping in the intermediate current range and small current range. The current clamping in the intermediate current range and small current range relies on the loop to achieve. The current clamping speed in this control method is relatively slow, generally reaching the millisecond level. For chip testing, millisecond-level overcurrent is destructive. Summary of the Utility Model
[0004] Based on this, it is necessary to provide a multi-range current clamping device, a power supply board, and a testing machine for the above technical problems.
[0005] In a first aspect, an embodiment of the present application proposes a multi-range current clamping device, and the device includes:
[0006] A first power amplifier circuit for power amplifying and outputting a positive current;
[0007] A second power amplifier circuit connected to the first power amplifier circuit for power amplifying and outputting a negative current;
[0008] A first current clamping element connected to the first power amplifier circuit;
[0009] A second current clamping element connected to the second power amplifier circuit;
[0010] A gear shifting circuit connected to the first current clamping element and the second current clamping element, including a plurality of resistors with different resistances;
[0011] The first current clamping element and the gear shifting circuit are connected to form a first current clamping circuit for clamping the positive current, and the second current clamping element and the gear shifting circuit are connected to form a second current clamping circuit for clamping the negative current. The gear shifting circuit is used to select the connected resistor to select the current clamping gear of the positive current and the negative current.
[0012] In some embodiments, the first power amplifier circuit includes an NMOS transistor, and the gate and source of the NMOS transistor are connected to the first current clamping element;
[0013] The second power amplifier circuit includes a PMOS transistor, and the gate and source of the PMOS transistor are connected to the second current clamping element.
[0014] In some embodiments, the first current clamping element is a first triode, whose collector is connected to the gate of the NMOS transistor, the base is connected to the source of the NMOS transistor and the gear shifting circuit, and the emitter is connected to the gear shifting circuit;
[0015] The second current clamping element is a second triode, whose collector is connected to the gate of the PMOS transistor, the base is connected to the source of the PMOS transistor and the gear shifting circuit, and the emitter is connected to the gear shifting circuit.
[0016] In some embodiments, the gear shifting circuit includes a first resistor, a second resistor, a first switch circuit, a second switch circuit, and a plurality of gear shifting sub-circuits;
[0017] One end of the first resistor is connected to the source of the NMOS transistor and the base of the first triode, and the other end is connected to the first switch circuit and a plurality of gear shifting sub-circuits; One end of the second resistor is connected to the source of the PMOS transistor and the base of the second triode, and the other end is connected to the first switch circuit and a plurality of gear shifting sub-circuits; The first switch circuit is also connected to the emitter of the first triode and the emitter of the second triode;
[0018] The second switch circuit is connected to the emitter of the first triode, the emitter of the second triode, and a common terminal of the plurality of gear shifting sub-circuits, and the other common terminal of the plurality of gear shifting sub-circuits is connected to the first resistor and the second resistor.
[0019] In some embodiments, the first switch circuit includes a first switch and a second switch, and the first switch is connected between the first resistor and the emitter of the first triode; The second switch is connected between the second resistor and the emitter of the second triode.
[0020] In some embodiments, the second switch circuit includes a third switch and a fourth switch, and the third switch is connected between a common terminal of the plurality of gear shifting sub-circuits and the emitter of the first triode; The fourth switch is connected between a common terminal of the plurality of gear shifting sub-circuits and the emitter of the second triode.
[0021] In some embodiments, the gear shifting sub-circuit includes a third resistor and a fifth switch, and the third resistor and the fifth switch are connected in series; The resistance values of the third resistors included in each of the gear shifting sub-circuits are different.
[0022] In some embodiments, the gear shifting circuit further includes a first diode and a second diode. The anode of the first diode is connected to the emitter of the first triode, and the cathode is connected to a common terminal of the plurality of gear shifting sub - circuits; the anode of the second diode is connected to a common terminal of the plurality of gear shifting sub - circuits, and the cathode is connected to the emitter of the second triode.
[0023] In a second aspect, an embodiment of the present application provides a power supply board card, including the multi - gear current clamping device as described in the first aspect.
[0024] In a third aspect, an embodiment of the present application provides a testing machine, including the power supply board card as described in the second aspect.
[0025] Compared with the prior art, in the present technical solution, a first current clamping circuit for positive current clamping is formed by connecting a first current clamping element to the gear shifting circuit, a second current clamping circuit for negative current clamping is formed by connecting a second current clamping element to the gear shifting circuit, and the resistance connected is selected through the gear shifting circuit to select the current clamping gear for positive and negative currents. Compared with relying on a loop to achieve the switching of intermediate current gears and small current gears, the present technical solution uses a multi - gear hardware current clamping method, with a faster current clamping speed, to achieve over - current protection during the chip testing process. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 FIG. is a schematic structural diagram of a multi - gear current clamping device in an embodiment of the present application;
[0027] Figure 2 FIG. is a circuit diagram of a multi - gear current clamping device in an embodiment of the present application;
[0028] Figure 3 FIG. is an equivalent circuit diagram of the first current clamping gear in an embodiment of the present application;
[0029] Figure 4 FIG. is an equivalent circuit diagram of the second current clamping gear in an embodiment of the present application;
[0030] Figure 5 FIG. is an equivalent circuit diagram of the third current clamping gear in an embodiment of the present application;
[0031] Figure 6 FIG. is a circuit diagram of a multi - gear current clamping device in another embodiment of the present application;
[0032] Figure 7 FIG. is an equivalent circuit diagram of the second current clamping gear in another embodiment of the present application.
[0033] Among them, 100 is the first power amplifier circuit; 200 is the second power amplifier circuit; 300 is the first current clamping component; 400 is the second current clamping component; 500 is the gear shifting circuit; 510 is the first switching circuit; 520 is the second switching circuit; 530 is the gear shifting sub-circuit. Detailed implementation manners
[0034] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.
[0035] Obviously, the accompanying drawings in the following description are only some examples or embodiments of the present application. For those of ordinary skill in the art, without creative efforts, the present application can also be applied to other similar scenarios based on these drawings. In addition, it can also be understood that although the efforts made in this development process may be complex and lengthy, for those of ordinary skill in the art related to the content disclosed in the present application, some designs, manufacturing or production changes made based on the technical content disclosed in the present application are only conventional technical means and should not be understood as the content disclosed in the present application being insufficient.
[0036] When "embodiment" is mentioned in the present application, it means that the specific features, structures or characteristics described in combination with the embodiment can be included in multiple embodiments of the present application. The appearance of this phrase in various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those of ordinary skill in the art explicitly and implicitly understand that the embodiments described in the present application can be combined with other embodiments without conflict.
[0037] Unless otherwise defined, technical terms or scientific terms involved in this application shall have the ordinary meanings understood by those with ordinary skills in the technical field to which this application belongs. The words such as "a", "an", "one", "the" and the like involved in this application do not indicate a limitation in quantity and may represent a singular or plural number. The terms "comprise", "include", "have" and any variations thereof involved in this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may further include unlisted steps or units, or may further include other steps or units inherent to these processes, methods, products or devices. The words such as "connect", "be connected", "couple" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "plurality" involved in this application means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, "A and / or B" may represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the front and rear associated objects. The terms "first", "second", "third" and the like involved in this application are only used to distinguish similar objects and do not represent a specific order for the objects.
[0038] As Figure 1 shown, an embodiment of this application provides a multi-gear clamp current device, which includes: a first power amplifier circuit 100 for power amplifying and outputting a positive current; a second power amplifier circuit 200 connected to the first power amplifier circuit 100 for power amplifying and outputting a negative current; a first clamp current element 300 connected to the first power amplifier circuit 100; a second clamp current element 400 connected to the second power amplifier circuit 200; a gear switching circuit 500 connected to the first clamp current element 300 and the second clamp current element 400, including a plurality of resistors with different resistance values; the first clamp current element 300 and the gear switching circuit 500 are connected to form a first clamp current circuit for clamping the positive current, and the second clamp current element 400 and the gear switching circuit 500 are connected to form a second clamp current circuit for clamping the negative current. The gear switching circuit 500 is used to select the connected resistor to select the clamp current gears of the positive current and the negative current.
[0039] The gear switching circuit 500 includes a plurality of resistors with different resistance values corresponding to different clamp current gears. For example, the larger the resistance value of the selected connected resistor, the smaller the corresponding clamp current gear, that is, the smaller the positive current and negative current output by the first power amplifier circuit 100 and the second power amplifier circuit 200.
[0040] In this embodiment, a first current clamping circuit for positive current clamping is formed by connecting a first current clamping element 300 to a gear shifting circuit 500, and a second current clamping circuit for negative current clamping is formed by connecting a second current clamping element 400 to the gear shifting circuit 500. The resistance connected is selected through the gear shifting circuit 500 to select the current clamping gears for positive and negative currents. Compared with relying on a loop to achieve the switching of intermediate current gears and small current gears, this technical solution uses a multi-gear hardware current clamping method, with a faster current clamping speed, achieving overcurrent protection during the chip testing process.
[0041] The following will Figure 2 describe the specific circuit structure of the multi-gear current clamping device in an embodiment with reference to the attached drawings.
[0042] Among them, the first power amplifier circuit 100 includes an NMOS transistor Q1, and the gate and source of the NMOS transistor Q1 are connected to the first current clamping element 300; the second power amplifier circuit 200 includes a PMOS transistor Q2, and the gate and source of the PMOS transistor Q2 are connected to the second current clamping element 400.
[0043] The NMOS transistor Q1 and the PMOS transistor Q2 form a push-pull structure, alternately outputting positive current and negative current.
[0044] The first current clamping element 300 is a first triode Q3, whose collector is connected to the gate of the NMOS transistor Q1, the base is connected to the source of the NMOS transistor Q1 and the gear shifting circuit 500, and the emitter is connected to the gear shifting circuit 500.
[0045] The second current clamping element 400 is a second triode Q4, whose collector is connected to the gate of the PMOS transistor Q2, the base is connected to the source of the PMOS transistor Q2 and the gear shifting circuit 500, and the emitter is connected to the gear shifting circuit 500.
[0046] The gear shifting circuit 500 includes a first resistor R1, a second resistor R2, a first switch circuit 510, a second switch circuit 520, and multiple gear shifting sub-circuits 530.
[0047] One end of the first resistor R1 is connected to the source of the NMOS transistor Q1 and the base of the first triode Q3, and the other end is connected to the first switch circuit 510 and multiple gear shifting sub-circuits 530; one end of the second resistor R2 is connected to the source of the PMOS transistor Q2 and the base of the second triode Q4, and the other end is connected to the first switch circuit 510 and multiple gear shifting sub-circuits 530; the first switch circuit 510 is also connected to the emitter of the first triode Q3 and the emitter of the second triode Q4.
[0048] The second switch circuit 520 is connected to the emitter of the first triode Q3, the emitter of the second triode Q4, and a common terminal of a plurality of gear shifting sub-circuits 530. The other common terminal of the plurality of gear shifting sub-circuits 530 is connected to the first resistor R1 and the second resistor R2.
[0049] Each gear shifting sub-circuit 530 corresponds to a current clamping gear, and the number of gear shifting sub-circuits 530 can be set according to the requirements of the number of gear levels.
[0050] The first switch circuit 510 includes a first switch K1 and a second switch K2. The first switch K1 is connected between the first resistor R1 and the emitter of the first triode Q3; the second switch K2 is connected between the second resistor R2 and the emitter of the second triode Q4.
[0051] The second switch circuit 520 includes a third switch K3 and a fourth switch K4. The third switch K3 is connected between a common terminal of the plurality of gear shifting sub-circuits 530 and the emitter of the first triode Q3; the fourth switch K4 is connected between a common terminal of the plurality of gear shifting sub-circuits 530 and the emitter of the second triode Q4.
[0052] The first switch K1 and the second switch K2 are used to control the access of the first resistor R1 and the second resistor R2 respectively. The third switch K3 and the fourth switch K4 are used to control the access of the plurality of gear shifting sub-circuits 530. It should be noted that when the first switch K1 and the second switch K2 are in the closed state, the third switch K3 and the fourth switch K4 are in the open state; conversely, when the first switch K1 and the second switch K2 are in the open state, the third switch K3 and the fourth switch K4 are in the closed state.
[0053] The gear shifting sub-circuit 530 includes a third resistor and a fifth switch, and the third resistor and the fifth switch are connected in series; the resistance values of the third resistors included in each gear shifting sub-circuit 530 are different.
[0054] The fifth switch is used to control the access of the third resistor.
[0055] As Figure 2 shown, the gear shifting circuit 500 includes three gear shifting sub-circuits 530. The first gear shifting sub-circuit includes a resistor R3 and a switch K5 connected in series; the second gear shifting sub-circuit includes a resistor R4 and a switch K6 connected in series; the third gear shifting sub-circuit includes a resistor R5 and a switch K7 connected in series.
[0056] The switches K5, K6, and K7 are used to select one of the resistors R3, resistor R4, and resistor R5 for access respectively.
[0057] The working principle of the above multi-gear current clamping device will be described below.
[0058] The base-emitter voltages of the first triode Q3 and the second triode Q4 are 0.6 to 0.7V. When overcurrent occurs, the base-emitter of the triode linearly turns on, pulling the voltages of the gates of the NMOS transistor Q1 and the PMOS transistor Q2 close to the source voltage respectively, so as to reduce the conduction current and achieve the purpose of current limiting. Since the base-emitter voltages of the first triode Q3 and the second triode Q4 are fixed, when different resistance values are selected and connected through the gear switching circuit 500, the currents of the base-emitter of the first triode Q3 and the second triode Q4 change, thereby realizing the switching of the current clamping gears.
[0059] Taking the resistors R1 = R2 = 0.1Ω, R3 = 1Ω, R4 = 10Ω, and the base-emitter of the first triode Q3 and the second triode Q4 being 0.65V as an example, the different current clamping gears of the above multi-gear current clamping device will be described.
[0060] First current clamping gear: Close the switches K1, K2, and K5, and open the other switches. Its equivalent circuit is as Figure 3 shown. At this time, the resistance connected between the base-emitter of the first triode Q3 and the second triode Q4 is 0.1Ω, and a current clamping of 6.5A (0.65V / 0.1R) can be achieved.
[0061] Second current clamping gear: Close the switches K3, K4, and K5, and open the other switches. Its equivalent circuit is as Figure 4 shown. At this time, the resistance connected between the base-emitter of the first triode Q3 and the second triode Q4 is 1.1Ω (R1 + R3), and a current clamping of 0.59A (0.65V / 1.1R) can be achieved.
[0062] Third current clamping gear: Close the switches K3, K4, and K6, and open the other switches. Its equivalent circuit is as Figure 5 shown. At this time, the resistance connected between the base-emitter of the first triode Q3 and the second triode Q4 is 10.1Ω (R1 + R4), and a current clamping of 64mA (0.65V / 10.1) can be achieved.
[0063] Fourth current clamping gear: Close the switches K3, K4, and K7, and open the other switches. The principle is the same, so it will not be elaborated here.
[0064] The measured response speed of the above current clamping method is within 3us, and can even reach within 1us.
[0065] Next, in combination with the attached Figure 6 the specific circuit structure of the multi-gear current clamping device in another embodiment will be described.
[0066] Compared with the above embodiments, the gear shifting circuit 500 further includes a first diode D1 and a second diode D2. The positive electrode of the first diode D1 is connected to the emitter of the first triode Q3, and the negative electrode is connected to a common terminal of a plurality of gear shifting sub - circuits 530; the positive electrode of the second diode D2 is connected to a common terminal of a plurality of gear shifting sub - circuits 530, and the negative electrode is connected to the emitter of the second triode Q4.
[0067] To achieve different current clamping requirements, it is realized by adding diodes to the emitters of the first triode Q3 and the second triode Q4. As Figure 7 shown, for example, when the multi - gear current clamping device is in the second current clamping gear, a current clamping of 1.18 A (0.65 V * 2 / 1.1 Ω) can be achieved.
[0068] An embodiment of the present application also proposes a power supply board card, including the multi - gear current clamping device described in the above embodiments.
[0069] Since the power supply board card includes the multi - gear current clamping device in the above embodiments, it can solve the same technical problems and achieve the same technical effects, which will not be elaborated here.
[0070] An embodiment of the present application also proposes a testing machine, including the power supply board card described in the above embodiments.
[0071] Since the testing machine includes the power supply board card in the above embodiments, it can solve the same technical problems and achieve the same technical effects, which will not be elaborated here.
[0072] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combinations of these technical features do not conflict, they should be considered as the scope described in this specification.
[0073] The above embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the utility model patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.
Claims
1. A multi-gear clamp current device, characterized in that, The device includes: A first power amplifier circuit for amplifying and outputting a positive current; A second power amplifier circuit connected to the first power amplifier circuit for amplifying and outputting a negative current; A first current clamping element connected to the first power amplifier circuit; A second current clamping element connected to the second power amplifier circuit; A gear switching circuit connected to the first current clamping element and the second current clamping element, including a plurality of resistors with different resistances; The first current clamping element and the gear switching circuit are connected to form a first current clamping circuit for clamping the positive current, and the second current clamping element and the gear switching circuit are connected to form a second current clamping circuit for clamping the negative current. The gear switching circuit is used to select the connected resistor to select the current clamping gear of the positive current and the negative current.
2. The multi-gear clamp current device according to claim 1, wherein The first power amplifier circuit includes an NMOS transistor, and the gate and source of the NMOS transistor are connected to the first current clamping element; The second power amplifier circuit includes a PMOS transistor, and the gate and source of the PMOS transistor are connected to the second current clamping element.
3. The multi-range clamp current device according to claim 2, wherein The first current clamping element is a first triode, the collector of which is connected to the gate of the NMOS transistor, the base is connected to the source of the NMOS transistor and the gear switching circuit, and the emitter is connected to the gear switching circuit; The second current clamping element is a second triode, the collector of which is connected to the gate of the PMOS transistor, the base is connected to the source of the PMOS transistor and the gear switching circuit, and the emitter is connected to the gear switching circuit.
4. The multi-gear clamp current device according to claim 3, characterized in that, The gear switching circuit includes a first resistor, a second resistor, a first switch circuit, a second switch circuit and a plurality of gear switching sub-circuits; One end of the first resistor is connected to the source of the NMOS transistor and the base of the first triode, and the other end is connected to the first switch circuit and a plurality of gear switching sub-circuits; one end of the second resistor is connected to the source of the PMOS transistor and the base of the second triode, and the other end is connected to the first switch circuit and a plurality of gear switching sub-circuits; the first switch circuit is also connected to the emitter of the first triode and the emitter of the second triode; The second switch circuit is connected to the emitter of the first triode, the emitter of the second triode and a common terminal of the plurality of gear switching sub-circuits, and the other common terminal of the plurality of gear switching sub-circuits is connected to the first resistor and the second resistor.
5. The multi-gear clamp current device according to claim 4, characterized in that, The first switch circuit includes a first switch and a second switch. The first switch is connected between the first resistor and the emitter of the first triode; the second switch is connected between the second resistor and the emitter of the second triode.
6. The multi-gear clamp current device according to claim 4, wherein, The second switch circuit includes a third switch and a fourth switch. The third switch is connected between a common terminal of the plurality of gear switching sub-circuits and the emitter of the first triode; the fourth switch is connected between a common terminal of the plurality of gear switching sub-circuits and the emitter of the second triode.
7. The multi-gear clamp current device according to claim 4, wherein The gear switching sub-circuit includes a third resistor and a fifth switch, and the third resistor and the fifth switch are connected in series; the resistance values of the third resistors included in each gear switching sub-circuit are different.
8. The multi-gear clamp current device according to claim 4, characterized in that, The gear shifting circuit further includes a first diode and a second diode. The anode of the first diode is connected to the emitter of the first triode, and the cathode is connected to a common terminal of the plurality of gear shifting sub-circuits. The anode of the second diode is connected to a common terminal of the plurality of gear shifting sub-circuits, and the cathode is connected to the emitter of the second triode.
9. A power supply board, characterized in that, It includes the multi-gear current clamping device according to any one of claims 1-8.
10. A testing machine, characterized in that, It includes the power supply board according to claim 9.