SiC-MOS device, inverter and electronic equipment

Abstract

The utility model provides a SiC-MOS device, an inverter and an electronic device. The SiC-MOS device comprises a substrate; the drain electrode is connected with the substrate; the epitaxial layer and the drain electrode are arranged on the two opposite sides of the substrate, an N + region and a P-body region which are in one-to-one correspondence are arranged in the epitaxial layer, the N + region and the P-body region form a channel, the channel is electrically connected with the drain electrode, the diameter of the cross section of the P-body region is in uniform gradient change, and the diameter of the cross section of the end, close to the drain electrode, of the P-body region is minimum; and the current is conducted with the source electrode through the channel from the drain electrode. Through the specially designed P-body region, the conductivity of a channel is increased on the premise that the resistance of the junction field effect transistor region is not influenced and limited, so that the carrier mobility and the conductivity of the device are improved, and compared with the conventional SiC-MOS device at the present stage, the response speed of the device is higher, the on-resistance is smaller, and the performance of the device is improved. And therefore, the energy loss is lower, and outstanding advantages are achieved in the actual use process.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and specifically refers to a SiC-MOS device, an inverter and an electronic device. Background Art

[0002] Although Schottky Barrier Diode (SBD) devices have advantages in many application fields due to their low forward voltage drop, high switching speed, low power consumption, etc., the problems existing in existing devices during long-term operation limit the improvement of their performance and the wide range of applications. The specific problems are as follows:

[0003] In existing SBD devices, in order to limit the junction field effect transistor region resistance (JFET region resistance) to ensure device performance and reliability, it is necessary to strictly control the basic unit spacing (Pitch size) of the lattice structure in the semiconductor device. However, this results in relatively weak channel conductivity in the P-body region of conventional devices, which directly affects the overall conductivity of the device. In high-frequency and high-speed circuits, this problem is particularly prominent because it restricts the rapid flow of current and reduces the response speed of the device. Due to the insufficient channel conductivity in the P-body region, the on-resistance of the device increases in the on-state, which leads to additional energy loss and reduces the energy efficiency of the device. In high-power applications, this problem can cause the device to overheat, affecting its stability and lifespan.

[0004] The weakening of the conductivity in the P-body region makes the device more vulnerable to external electromagnetic interference, especially in application scenarios with complex electromagnetic environments, which can cause signal distortion and affect the reliability and stability of the device. Due to the decrease in the conductivity and response speed of the device, more noise and distortion may be introduced when processing high-speed signals, which is fatal for applications such as radio frequency signal detection and pulse interference suppression. In high-speed switching applications, the increase in power consumption of the device will lead to an extension of the charging and discharging time, affecting the overall power consumption performance. At the same time, the increase in power consumption will also exacerbate the thermal loss of the device, further affecting its performance and lifespan.

[0005] To overcome these challenges, the industry and researchers have been seeking new structural and material innovations to improve the performance of SBD devices. This includes optimizing the design of the device, using new semiconductor materials, and improving the manufacturing process to ensure the stability and efficiency of the device under high-speed operating conditions. However, until now, no comprehensive solution has been found that can significantly improve the channel conductivity in the P-body region without sacrificing other performance parameters of the device. Summary of the Invention

[0006] To this end, the technical problem to be solved by the present utility model is to overcome the problem of low channel conductivity in the P-body region in the prior art, and to provide a SiC-MOS device, an inverter and an electronic device.

[0007] To solve the above technical problem, the present utility model provides a SiC-MOS device, which includes: a substrate; a drain electrode, the drain electrode being connected to the substrate; an epitaxial layer, the epitaxial layer and the drain electrode being disposed on opposite sides of the substrate, and at least one N + region and at least one P-body region are provided inside, the N + regions are arranged in one-to-one correspondence with the P-body regions, and a channel is formed between the two, the channel being electrically connected to the drain electrode, wherein, in the thickness direction of the epitaxial layer, the cross-sectional diameter of the P-body region changes in a uniform gradient, and the cross-sectional diameter of the end close to the drain electrode is the smallest; a source electrode, the source electrode being disposed on the surface of the epitaxial layer, and current is conducted from the drain electrode through the channel and the source electrode.

[0008] In an embodiment of the present utility model, it further includes at least one gate electrode, and at least one of the gate electrodes is disposed between a corresponding one of the N + regions and a P-body region.

[0009] In an embodiment of the present utility model, the gate electrode includes a gate electrode body and a gate oxide layer, and the gate oxide layer is coated around the gate electrode.

[0010] In an embodiment of the present utility model, it further includes at least one P + region, and at least one of the P + regions is provided corresponding to at least one of the N + regions.

[0011] In an embodiment of the present utility model, the epitaxial layer includes a first epitaxial layer, a second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer which are connected in sequence, the first epitaxial layer is connected to the substrate, the P-body region penetrates through the second epitaxial layer and the third epitaxial layer, and extends to the first epitaxial layer, the source electrode is disposed on the fourth epitaxial layer, and the at least one N + region is disposed inside the fourth epitaxial layer.

[0012] In an embodiment of the present utility model, the P-body region includes a first P-body region, a second P-body region, and a third P-body region. The first P-body region is disposed in the first epitaxial layer, the second P-body region is disposed in the second epitaxial layer, the third P-body region is disposed in the third epitaxial layer, and the cross-sectional area of the first P-body region < the cross-sectional area of the second P-body region < the cross-sectional area of the third P-body region.

[0013] In an embodiment of the present utility model, in the thickness direction of the epitaxial layer, the P-body region has a funnel-shaped structure with a smooth transition at the edge.

[0014] In an embodiment of the present utility model, the source electrode is a metal deposition layer, and the substrate base material is silicon nitride.

[0015] The present utility model provides an inverter, which includes the above-mentioned SiC-MOS device.

[0016] The present utility model provides an electronic device, which includes the above-mentioned SiC-MOS device.

[0017] The above technical solution of the present utility model has the following advantages compared with the prior art:

[0018] For the SiC-MOS device, inverter, and electronic device of the present utility model, through the specially designed P-body region, the conductivity of the channel is increased without affecting the resistance of the junction field effect transistor region, thereby improving the carrier mobility and conductivity of the device. Compared with the conventional SiC-MOS devices at the present stage, the application makes the device have a faster response speed, a smaller on-resistance, and lower energy loss, thus having outstanding advantages in the actual use process. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to make the content of the present utility model easier to be clearly understood, the following further describes the present utility model in detail according to the specific embodiments of the present utility model in conjunction with the drawings.

[0020] Figure 1 is a schematic structural diagram of the SiC-MOS device in the preferred embodiment of the present utility model;

[0021] Figure 2 is Figure 1 a schematic structural diagram of the substrate, drain electrode, and first epitaxial layer in the preparation process of the shown SiC-MOS device;

[0022] Figure 3 is Figure 1Schematic diagram of the process structure for forming the first P-body region in the SiC-MOS device shown;

[0023] Figure 4 is Figure 1 Schematic diagram of the process structure for fabricating the second epitaxial layer in the SiC-MOS device shown;

[0024] Figure 5 is Figure 1 Schematic diagram of the process structure for forming the second P-body region in the SiC-MOS device shown;

[0025] Figure 6 is Figure 1 Schematic diagram of the process structure for forming the third epitaxial layer and the third P-body region in the SiC-MOS device shown;

[0026] Figure 7 is Figure 1 Schematic diagram of the process structure for fabricating the fourth epitaxial layer in the SiC-MOS device shown;

[0027] Figure 8 is Figure 1 Schematic diagram of the process structure for fabricating the N+ region in the SiC-MOS device shown;

[0028] Figure 9 is Figure 1 Schematic diagram of the process structure for etching to form a trench at the time of fabricating the gate in the SiC-MOS device shown;

[0029] Figure 10 is Figure 1 Schematic diagram of the process structure for fabricating the gate oxide layer in the SiC-MOS device shown;

[0030] Figure 11 is Figure 1 Schematic diagram of the process structure for fabricating the gate in the SiC-MOS device shown.

[0031] Description of the reference numerals in the drawings of the specification: 100, substrate; 200, drain; 300, epitaxial layer; 310, first epitaxial layer; 320, second epitaxial layer; 330, third epitaxial layer; 340, fourth epitaxial layer; 350, P-body region; 351, first P-body region; 352, second P-body region; 353, third P-body region; 360, P + region; 370, N+ region; 400, source; 500, gate; 510, gate oxide layer. Detailed implementation manners

[0032] The present utility model will be further described below in conjunction with the accompanying drawings and specific embodiments, so that those skilled in the art can better understand the present utility model and be able to implement it. However, the cited embodiments do not limit the present utility model.

[0033] Embodiment 1

[0034] See Figure 1 As shown, this embodiment provides a SiC-MOS device, which includes: a substrate 100; a drain 200, the drain 200 is connected to the substrate 100; an epitaxial layer 300, the epitaxial layer 300 and the drain 200 are disposed on opposite sides of the substrate 100, and at least one N + region 370 and at least one P-body region 350 are provided inside it. The N + region 370 is arranged in one-to-one correspondence with the P-body region 350, and a channel is formed between the two. The channel is electrically connected to the drain 200. Among them, in the thickness direction of the epitaxial layer 300, the cross-sectional diameter of the P-body region 350 changes uniformly in gradient, and the cross-sectional diameter of the end close to the drain 200 is the smallest; a source 400, the source 400 is disposed on the surface of the epitaxial layer 300, and current is conducted from the drain 200 through the channel to the source 400.

[0035] The SiC-MOS device described in this embodiment increases the conductivity of the channel without affecting the resistance of the junction field effect transistor region through the specially designed P-body region 350, thereby improving the carrier mobility and conductivity of the device. Compared with the current conventional SiC-MOS devices, this application makes the device have a faster response speed, a smaller on-resistance, and lower energy loss, so it has outstanding advantages in actual use.

[0036] In this embodiment, the substrate 100 is made of silicon nitride. Taking the SiC-MOS device shown as a reference, the epitaxial layer 300 in this embodiment is disposed above the substrate 100, the drain 200 is disposed below the substrate 100, at least one N Figure 1 region 370 and at least one P-body region 350 are both disposed in the upper part of the epitaxial layer 300, and the source 400 is connected to the top surface of the epitaxial layer 300. Further, at least one gate 500 is further included in this embodiment. At least one of the gates 500 is disposed between a corresponding N + region 370 and a P-body region 350. Based on this structural arrangement, when a positive voltage is applied to both the drain 200 and the gate 500 in this embodiment, relative to the potentials of the source 400 and the P-body region 350, the N + region 370 and a P-body region 350. Based on this structural arrangement, when a positive voltage is applied to both the drain 200 and the gate 500 in this embodiment, relative to the potentials of the source 400 and the P-body region 350, the N +More negative electrons will accumulate in region 370. Based on this potential difference, electrons will move from N + region 370 to P-body region 350, forming a channel. This channel is formed by holes in P-body region 350 and electrons in N + region 370. Once the channel is formed, electrons can flow from the drain 200 to the source 400, forming a current path. Therefore, in this state, the SBD (Schottky Barrier Diode) device is turned on. At this time, current can conduct from the drain 200 through the channel to the source 400, and at the same time, the gate 500 can control the on-off of the current at the channel, thereby realizing a flexible and precise control process of this device. Specifically, in this embodiment, N + region 370 refers to a region doped with a higher concentration of N-type impurities, which can change the conductivity, carrier concentration, and conductive performance of the device, while providing good electrical connection and reducing the contact resistance. The cross-sectional area of P-body region 350 determines the conductive ability of the channel: the wider the cross-sectional area of P-body, the stronger the conductive ability of the channel, the smaller the resistance. Correspondingly, when the cross-sectional area of P-body decreases, the conductive ability of the channel weakens and the resistance increases. In this embodiment, in order to make the current change more uniform, in the thickness direction of the epitaxial layer 300, P-body region 350 is a funnel-shaped structure with a smooth transition at the edge, thereby achieving the optimal effect.

[0037] In this embodiment, the source 400 is preferably a metal deposition layer, so as to have a good bonding strength with the epitaxial layer 300. The present invention does not limit the specific metal type of the source 400.

[0038] In this embodiment, the gate 500 includes a gate 500 body and a gate oxide layer 510, and the gate oxide layer 510 is coated around the gate 500. The gate oxide layer 510 acts as an insulating layer, located between the gate 500 of the transistor and the semiconductor channel. Its most basic function is to isolate the gate 500 metal and the semiconductor material, thereby preventing the gate 500 material from directly contacting the semiconductor, and thus avoiding unnecessary electron flow and maintaining a high-resistance state when the transistor is not activated. At the same time, the gate oxide layer 510 has a certain capacitance property, which can store charges and control the flow of current.

[0039] This embodiment also includes at least one P + region 360. At least one of the P + regions 360 is provided corresponding to at least one of the N + regions 370. The P + region 360 can enhance the carrier concentration, and it can also make the connection between the semiconductor device and the external circuit better, contributing to improving the conductivity and current control ability of the device.

[0040] In this embodiment, for the convenience of production and processing and to improve the precision of the preparation of the P-body region 350, the epitaxial layer 300 includes a first epitaxial layer 310, a second epitaxial layer 320, a third epitaxial layer 330, and a fourth epitaxial layer 340 that are sequentially connected. The first epitaxial layer 310 is connected to the substrate 100. The P-body region 350 penetrates the second epitaxial layer 320 and the third epitaxial layer 330 and extends to the first epitaxial layer 310. The source electrode 400 is disposed on the fourth epitaxial layer 340, and the at least one N + region 370 is disposed inside the fourth epitaxial layer 340. Correspondingly, the P-body region 350 includes a first P-body region 351, a second P-body region 352, and a third P-body region 353. The first P-body region 351 is disposed in the first epitaxial layer 310, the second P-body region 352 is disposed in the second epitaxial layer 320, and the third P-body region 353 is disposed in the third epitaxial layer 330, and the cross-sectional area of the first P-body region 351 < the cross-sectional area of the second P-body region 352 < the cross-sectional area of the third P-body region 353. Based on this structure, the P-body region 350 forms a stepped P + region 360 domain and a P-body region 350 domain. Thus, while reducing the Pitch size (minimum unit size), the original cross-sectional area of the J-FET (junction field effect transistor region resistance) remains unchanged. At the same time, when the cross-sectional area of the P-body region 350 domain increases, the leakage current of the SBD also decreases because the increase in the cross-sectional area of the P-body reduces the conductivity of the SBD and decreases the drift velocity of electrons in the structure, thereby reducing the magnitude of the leakage current. However, when the cross-sectional area of the P-body increases, the resistance of the JFET region also increases. This is because the increase in the cross-sectional area of the P-body increases the length of the channel in the JFET region, making the path for electrons to move in the channel longer, resulting in an increase in resistance. Therefore, the structural arrangement in this application can limit the resistance of the JFET region while ensuring a reduction in the SBD leakage current.

[0041] The preparation process of the SiC-MOS device in this embodiment includes the following steps:

[0042] S1. Prepare a silicon carbide substrate 100 and epitaxially grow a first epitaxial layer 310 on the silicon carbide substrate 100, as shown in Figure 2 shown;

[0043] S2. Etch away the redundant part on the first epitaxial layer 310 through an etching process to form a drift region N + region 370;

[0044] S3. Perform ion implantation on the first epitaxial layer 310 using a mask to form the first P-body region 351. See Figure 3 ;

[0045] S4. Epitaxially grow a second epitaxial layer 320 above the first epitaxial layer 310. See Figure 4 ;

[0046] S5. Perform ion implantation on the second epitaxial layer 320 using a mask to form the second P-body region 352. At this time, ensure that the cross-sectional area of the second P-body region 352 is larger than the cross-sectional area of the first P-body region 351. See Figure 5 ;

[0047] S6. Epitaxially grow a third epitaxial layer 330 above the second epitaxial layer 320. See Figure 6 ;

[0048] S7. Perform ion implantation on the third epitaxial layer 330 using a mask to form the third P-body region 353. At this time, ensure that the cross-sectional area of the third P-body region 353 is larger than the cross-sectional area of the second P-body region 352. See Figure 6 ;

[0049] S8. Epitaxially grow a fourth epitaxial layer 340 above the third epitaxial layer 330. See Figure 7 ;

[0050] S9. Inject N + ions into the fourth epitaxial layer 340 to form an N + region 370. At the same time, inject P + ions into the fourth epitaxial layer 340 to form a P + region 360. See Figure 8 and Figure 9 ;

[0051] S10. Etch the fourth epitaxial layer 340 to form a trench. See Figure 10 , set a gate oxide layer 510 in the trench, and then deposit an oxide layer into the trench to generate a gate 500. See Figure 11 ;

[0052] S11. Perform metal deposition to fabricate the source electrode 400. Thus, the fabrication process of the SiC-MOS device is completed.

[0053] Embodiment 2

[0054] This embodiment provides an inverter, which includes the SiC-MOS device described in Embodiment 1.

[0055] Embodiment 3

[0056] This embodiment provides an electronic device, which includes the SiC-MOS device described in Embodiment 1.

[0057] In summary, for the SiC-MOS device, inverter and electronic device of the present utility model, by means of the specially designed P-body region 350, the conductivity of the channel is increased without affecting the resistance of the junction field effect transistor region, thereby improving the carrier mobility and conductivity of the device. Compared with the conventional SiC-MOS devices at the present stage, the application makes the device have a faster response speed, a smaller on-resistance and lower energy loss, thus having outstanding advantages in the actual use process.

[0058] Obviously, the above embodiments are only examples for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or variations can be made on the basis of the above description. It is not necessary and impossible to enumerate all the implementation manners here. And the obvious changes or variations derived therefrom still fall within the protection scope of the present utility model.

Claims

1. A SiC-MOS device, characterized in that: Comprising: A substrate; A drain, the drain being connected to the substrate; Epitaxial layer, the epitaxial layer and the drain are disposed on opposite sides of the substrate, and at least one N + region and at least one P-body region are provided therein, and the N + regions are arranged in one-to-one correspondence with the P-body regions, and a channel is formed between the two, and the channel is electrically connected to the drain. Wherein, in the thickness direction of the epitaxial layer, the cross-sectional diameter of the P-body region changes uniformly in gradient, and the cross-sectional diameter of the end close to the drain is the smallest; A source, the source being disposed on the surface of the epitaxial layer, and current being conducted from the drain through the channel to the source.

2. The SiC-MOS device according to claim 1, wherein: It further includes at least one gate, and at least one of the gates is disposed between a corresponding one of the N + regions and a corresponding one of the P-body regions.

3. The SiC-MOS device according to claim 2, characterized in that: The gate includes a gate body and a gate oxide layer, and the gate oxide layer coats the periphery of the gate.

4. The SiC-MOS device according to claim 1, wherein: It also includes at least one P + region, and at least one of the P + regions corresponds to the setting of at least one of the N + regions.

5. The SiC-MOS device according to claim 1, characterized in that: The epitaxial layer includes a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, and a fourth epitaxial layer connected in sequence. The first epitaxial layer is connected to the substrate. The P-body region penetrates through the second epitaxial layer and the third epitaxial layer and extends to the first epitaxial layer. The source electrode is disposed on the fourth epitaxial layer. The at least one N + region is disposed inside the fourth epitaxial layer.

6. The SiC-MOS device according to claim 5, characterized in that: The P-body region includes a first P-body region, a second P-body region, and a third P-body region. The first P-body region is disposed in the first epitaxial layer, the second P-body region is disposed in the second epitaxial layer, and the third P-body region is disposed in the third epitaxial layer, and the cross-sectional area of the first P-body region < the cross-sectional area of the second P-body region < the cross-sectional area of the third P-body region.

7. The SiC-MOS device according to claim 1, characterized in that: In the thickness direction of the epitaxial layer, the P-body region is a funnel-shaped structure with a smooth transition at the edge.

8. The SiC-MOS device according to claim 1, characterized in that: The source is a metal deposition layer, and the substrate base material is silicon nitride.

9. An inverter, characterized in that: Comprising the SiC-MOS device according to any one of claims 1 to 8.

10. An electronic device, characterized in that: Comprising the SiC-MOS device according to any one of claims 1 to 8.

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